JPH0785140A - Simulation method for structure of semiconductor cross section - Google Patents

Abstract

PURPOSE:To accurately draw a structure of a cross section by drawing a diagram in a desired pixcel value to a desired position of a cross section display pattern to revise the shape of the cross section. CONSTITUTION:A resist display region 51 displayed as a mask pattern when the region is normal is displayed on an Al display region 43a indicating an Al layer being an Al wiring layer. When it is simulated that a residue remains by a defect of development in the case of patterning of the mask pattern, a resist display region 51a indicating the residue is additionally drawn to a location where no mask pattern is substantially in existence. A pattern where an Al display region 43b indicating a short-circuit part is drawn is obtained by drawing an upper layer based on the state. Thus, when residual development is in existence in the development of a resist pattern for patterning of the wiring layer, the short-circuit of the wiring layer is simulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a method for easily predicting the influence of a shape change in an intermediate step on a subsequent step in manufacturing a semiconductor device. The present invention relates to a semiconductor device cross-sectional structure simulation method which is widely used in fields such as development.

[0002]

2. Description of the Related Art A cross-sectional structure of a semiconductor device to be manufactured is to be drawn according to pattern data of a photomask used for manufacturing the semiconductor device and materials used for each layer, forming method, film forming conditions such as film thickness. Is possible. There are a method by a shape simulation and a method by a simple model for drawing a sectional structure of this semiconductor device (SI developed at the University of California, Berkeley).
MPL). Usually, the shape simulation is used when it is desired to know the cross-sectional shape of a narrow area accurately, and the simple model is used when the cross-sectional structure in a wide range is displayed at high speed.

In any of these methods of drawing the cross-sectional structure, the boundary of each layer is expressed by a polygonal line using vector data. For example, as shown in FIG. 7, a first material region 71, a second material region 72, a third material region 73, and an air region 74, which form a cross section of a semiconductor device to be drawn, are formed on a CRT of a shape simulation device.
Are the material boundary lines 75 and 76 and the surface boundary line 7, respectively.
It is expressed by dividing it by a polygon (a polygonal line) formed by 7.

When a new layer is formed on the material region 73, for example, when a state in which an insulating film of silicon oxide is formed is drawn, the formation state such as anisotropy of silicon oxide to be formed. In consideration of the above, the movement vector of each vertex of the polygonal line of the substance boundary line 77 showing the outermost surface is formed and moved to form a new boundary line. Here, the moving destination of each vertex is calculated in minute increments. When movement vectors intersect or one region is divided, graphic operation (calculation processing by a program) is performed on the shape data to generate consistent new data (new boundary line). The boundary line is drawn by this. Therefore, with respect to the process variation in the intermediate process, the cross-sectional shape corresponding to the variation is generated by changing the process condition input to the shape simulator according to the variation.

[0005]

Since the conventional method is as described above, only the shape variation corresponding to the variation of the process condition can be handled, and the shape variation due to a phenomenon not prepared in advance and the adhesion of the foreign matter can be dealt with. There is a problem that it is impossible to deal with such an accidental shape change.

The present invention has been made in order to solve the above problems, and does not use a complicated arithmetic process, does not take a long time for this process, and is a semiconductor suitable for an unprepared variation. The object is to enable accurate drawing of the cross-sectional structure of the device.

[0007]

A method for simulating a semiconductor device cross-section structure according to the present invention defines a substance type by a pixel value attached to each pixel of a display cross section of a drawing target displayed on a screen, Below the drawing layer, the processing characteristic figure that is determined by the process of determining the pixel whose pixel value is different from its own pixel value as the boundary pixel of the substance and the characteristic of the step of forming the drawing layer to be generated next Had a specific value on the specified display cross section that was displayed on the screen before the process of drawing at the pixel center on the surface boundary of the already displayed display layer and the process of drawing the processing characteristic figure The process of redrawing the pixel to return it to its specific value is repeated multiple times to generate the cross-section structure screen. To Nozomu position by drawing a shape with a desired pixel values and performing a simulation by changing the cross-sectional shape.

[0008]

[Function] Drawing the changed state of each layer constituting the cross-section without using the boundary line that shows the boundary of the substance,
When the display state is changed on the way, a cross-sectional state corresponding to this is drawn and generated.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory view schematically showing the definition of a material region and a material boundary in the method for displaying a semiconductor device sectional structure according to the present invention. In the figure, 1 is a first substance region, 2 is a second substance region, 3 is a third substance region, 4 is an air region, p1 is a pixel showing the first substance region 1, and p2 is a pixel. 2 is a pixel representing the material region 2, p3 is a pixel representing the third material region 3, and p4 is a pixel representing the air region 4. A pixel is a pixel of the minimum unit when displaying a drawing, and for example, the pixel p1 means that the pixel (pixel) at this position in displaying displays a value indicating the pixel p1.

Thus, for example, the third material region 3 is
It is represented by a set of pixels having a value indicating the pixel p3. Here, the value indicating the pixel p1 is, for example, a value at which the pixel emits “red”. Similarly, if the pixel p2 has a value of "blue", the pixel p3 has a value of "yellow", and the pixel p4 has a value of "white", the first substance region 1 is displayed in "red" in FIG. The second material region 2 is displayed in "blue", the third material region 3 is displayed in "yellow", and the air region 4 is displayed in "white".

Therefore, in such a display, the material region,
There is no material boundary data, and areas where pixels with the same pixel value continue on the screen are judged to be areas of the same material, and areas where the pixel values of adjacent pixels differ from their pixel values are the boundaries of that material ( Boundary pixel). Pixels corresponding to respective substances constituting the semiconductor device on the screen are called substance pixels, and all pixels existing in a space above the surface of the semiconductor device, for example, pixel p4 in FIG. 1 are defined as air pixels. Furthermore,
A material pixel that touches an air pixel is defined as a surface boundary pixel.

Next, a case will be described in which a state in which the fourth substance is newly deposited and formed on the third substance region 3 of the semiconductor device thus displayed by CVD is displayed. As shown in FIG. 2A, a “circle” having a radius corresponding to the deposited film thickness is drawn centered on all surface boundary pixels. The pixel p4 of the air region 4 in which this circle is drawn
Then, the pixel p3 of the third substance region 3 is changed to a pixel value indicating the fourth substance and displays, for example, "green". It should be noted that even if they have different pixel values, they can be displayed in the same color, and even if they have different display colors, they can have the same pixel value.

Finally, in order to restore the pixels in the substance area 3 which have been changed to the pixel value indicating the fourth substance, the portion which was the substance pixel on the original screen is redrawn with the original pixel value. To do. As a result, as shown in FIG. 2B, the fourth substance region 5 is displayed on the third substance region 3. The fourth substance region 5 is a region indicated by a pixel p5 having a pixel value indicating the fourth substance and displaying "green".

Further, in drawing a silicon oxide film by thermal oxidation or the like, a predetermined film thickness is virtually generated in consideration of the expansion coefficient of a layer to be formed, and the convolution integral using a Gaussian distribution function is based on this. This is performed by calculating the shape of the oxide film generated by the method and obtaining the shape suggestive line segment group. and again.
When the processing characteristic figure such as sputter etching is complicated, it is approximated by a plurality of basic figures, and by repeating the deposition and etching by these basic figures, the shape change and layer formation by the process Draw.

Example 1. FIG. 3 is a screen view showing a state in which the cross-sectional structure of the semiconductor device is formed and displayed as described above. In the figure, 31 is a substrate display area displaying a silicon substrate, and 32 is a silicon oxide display area displaying an element isolation film formed by selectively oxidizing the surface of the silicon substrate for element isolation. , 33 is a polysilicon display region displaying a gate electrode made of polysilicon formed by unwinding a thin oxide film at a predetermined position on a silicon substrate, and 34 is an oxide formed by thermal oxidation on the gate electrode. A silicon oxide display region displaying a film, and a first impurity display region 35 showing a first conductivity type impurity diffusion region formed in a silicon substrate in a self-aligned manner by using a gate electrode or the like as a mask.

Further, 36 is a second impurity display region showing an impurity diffusion region of the second conductivity type formed on the silicon substrate,
Reference numeral 37 is an oxide film display region displaying a silicon oxide film formed in a predetermined region by etching after being deposited by CVD or the like, and 38 is a state in which the silicon oxide film shown in the oxide film display region 37 is deposited. A BPSG display region displaying a BPSG film formed for planarization on the BPSG display region,
Reference numeral 39 denotes an Al display area showing an Al wiring layer formed in a predetermined area by etching after being deposited by a sputtering method or the like, and 40 is deposited and formed by a CVD method or the like on the Al wiring displayed in the Al display area 39. And an oxide film display region displaying a silicon oxide film.

Reference numeral 41 is an SOG display area displaying an SOG film formed to reduce the step of the silicon oxide film displayed in the oxide film display area 40, and 42 is an SOG display area.
An oxide film display region showing a silicon oxide film deposited by the CVD method or the like on the silicon oxide film shown in the oxide film display region 40 so as to sandwich the OG film, and 43 is an oxide film display region 42. An Al display region showing an Al wiring layer formed on the silicon oxide film,
Is CV on the Al wiring displayed in the Al display area 43.
An oxide film display region displaying a silicon oxide film deposited by the D method or the like, and 45 an SOG film formed to reduce the step difference of the silicon oxide film displayed in the oxide film display region 44. SOG display area.

Reference numeral 46 is an oxide film display region displaying a silicon oxide film deposited by the CVD method or the like on the silicon oxide film shown by the oxide film display region 44 so as to sandwich the SOG film, and 47 is An oxide film display region 46 is an Al display region showing an Al wiring layer formed on the silicon oxide film, and 48 is a silicon oxide film deposited and formed on the Al wiring film displayed in the Al display region 47 by a CVD method or the like. Oxide display area showing the film, 4
Reference numeral 9 denotes a silicon nitride display area displaying a passivation film made of silicon nitride formed on the uppermost layer of this semiconductor device, and 50 an air area displaying a space above the passivation film.

Here, the same material is displayed with pixels having the same pixel value. For example, since the oxide film display areas 40 and 42 are displayed by the same material, the pixel values thereof are the same. Therefore,
These will be displayed in the same color. Then, in the drawing, in order to make the distinction of each layer easy to understand, it is expressed by using a boundary line, but in reality, there is no boundary line, and each area is displayed in a different color. Therefore, in reality, the oxide film display regions 40 and 42 described above are used.
There is no boundary line between the oxide film display regions 46 and 48, and it is not possible to distinguish these layers on the display.

As described above, in contrast to the cross sectional display shown in FIG.
6 to 6 are in the intermediate manufacturing process of the semiconductor device to be displayed,
It is explanatory drawing which showed the example of the cross-section structure simulation screen when there exists a shape change. Example 2. FIG. 4 is an explanatory diagram showing a case where a completed semiconductor device is simulated when there is an abnormality in the patterning of a resist used in an intermediate step. Here, a case where a mask formed by patterning a photoresist is used as a mask for etching for forming a pattern of Al wiring will be described.

As shown in FIG. 4A, in a normal case, a resist display area 51 displaying a mask pattern is displayed on the Al display area 43a displaying an Al layer to be an Al wiring layer. Has been done. Here, when it is attempted to simulate the case where a residue remains due to defective development during patterning of the mask pattern, as shown in FIG. 4B, a resist display indicating the residue is shown where there is no mask pattern. The area 51a is additionally drawn. Then, if the upper layer is drawn based on this state, FIG.
As shown in, a screen is obtained in which the Al display area 43b showing the short circuit portion is drawn. Therefore, this
When the resist pattern for patterning the wiring layer is left undeveloped, it means that the wiring layer can be short-circuited.

Example 3. FIG. 5 is an example of simulating the case where a foreign substance has adhered immediately before depositing and forming a metal for a wiring layer. In this case, for example, the Al display area 4
In a state before the Al layer deposition for forming the Al wiring layer shown by 7 is performed, as shown in FIG. 5A, a foreign substance display area 52 indicating a foreign substance is additionally drawn at a desired position. Then, if the upper layer is drawn based on this state, FIG.
As shown in (b), the Al display region 47a for displaying the Al wiring layer formed so that the upper part of the foreign substance display region 52 is projected is drawn. From this, it is possible to simulate that if a foreign substance enters below, the wiring shape becomes a peculiar shape, the wiring resistance increases, and in some cases, a disconnection may occur.

Example 4. FIG. 6 is an example of simulating a case where a thin film portion is formed in a resist serving as an etching mask for forming a contact hole for connecting upper and lower wiring metal layers. In this case,
As shown in (a), the resist display region 53 showing the etching mask for forming the contact hole is redrawn with the pixel value of air according to the shape of the film at the corresponding place reduced. The etching mask shown in the resist display area 53 has a film thickness up to the area shown by the dotted line in FIG. 6A in a normal state.

If the upper layer is drawn based on this state, the interlayer films shown in the oxide film display region 44 and the SOG display region 45 are thinned and oxidized as shown in FIG. 6B. A screen is obtained in which a part of the interlayer film shown in the film display area 46 is lost. In this case, Al
The wiring displayed in the display area 43 and the Al display area 47
It can be seen that there is a possibility that the parasitic capacitance with the wiring layer indicated by is increased, or in some cases, a short circuit occurs between these wirings.

As described above, it is possible to predict the cross-sectional state of the semiconductor device at the time when the manufacturing is completed by redrawing the image in the desired state to be simulated on the screen of the intermediate state of manufacturing the semiconductor device. . Note that there is a method for drawing a figure corresponding to a shape change of a user, in which small squares having a specified pixel value are lined up and drawn on the movement trajectory of a mouse cursor. Here, the figure drawn on the moving path of the mouse cursor may be a circle or a point, or various methods conventionally used as a figure drawing method on a computer screen may be used.

[0026]

As described above, according to the present invention, the cross-sectional structure of the semiconductor device is complicated to cope with the shape variation due to a phenomenon not prepared in advance and the accidental shape variation such as adhesion of foreign matter. There is an effect that accurate drawing can be performed without using any arithmetic processing or taking time.
Therefore, the time required for failure analysis of the semiconductor device can be significantly reduced, and the development efficiency of the semiconductor device manufacturing process can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory view schematically showing the definition of a material region and a material boundary in a method for displaying a semiconductor device sectional structure according to the present invention.

FIG. 2 is an explanatory diagram for explaining the concept of the present invention.

FIG. 3 is a screen view showing a state in which a cross-sectional structure of a semiconductor device according to an embodiment of the present invention is formed and displayed.

FIG. 4 is an explanatory diagram showing a case where a completed semiconductor device is simulated when there is an abnormality in the patterning of a resist used in an intermediate step.

FIG. 5 is an explanatory diagram showing a case where a completed semiconductor device is simulated when foreign matter is mixed in an intermediate step.

FIG. 6 is an explanatory diagram showing a case where a completed semiconductor device is simulated when there is an abnormality in a resist used in an intermediate step.

FIG. 7 is an explanatory diagram showing a conventional drawing state.

[Explanation of symbols]

 1 First Material Area 2 Second Material Area 3 Third Material Area 4 Air Area 5 Fourth Material Area p1, p2, p3, p4, p5 Pixel 31 Substrate Display Area 32, 34 Silicon Oxide Display Area 33 Poly Silicon display region 35 First impurity display region 36 Second impurity display region 37, 40, 42, 44, 46, 48 Oxide film display region 38 BPSG display region 39, 43, 47 Al display region 41, 45 SOG display region 49 Nitriding Silicon display area 50 Air area

Claims (1)

[Claims] 1. A cross-sectional structure at a location designated based on process data and mask pattern data when manufacturing a semiconductor device is drawn on a computer screen by sequentially drawing layers constituting the cross-sectional structure from the lower layers. A method of simulating a semiconductor device cross-section structure by performing a display, wherein a type of substance is defined by a pixel value attached to each pixel of a display cross section of a drawing target displayed on the screen, and adjacent pixels are defined. A processing characteristic figure determined by the process of determining a pixel whose pixel value of is different from its own pixel value as the boundary pixel of the substance and the characteristic of the step of forming the drawing layer to be generated next, Before the process of drawing at the pixel center on the surface boundary of the already displayed display layer and the process of drawing the processing characteristic figure Generate a cross-section structure screen by repeating a process of redrawing a pixel having a specific value on the predetermined display cross-section displayed above so as to return to the specific value, the cross-section display screen The method for simulating the cross-sectional structure of a semiconductor device is characterized in that a simulation is performed by drawing a figure at a desired position on the cross-section display screen with a desired pixel value and changing the cross-sectional shape during the generation of.