JPH04218944A - Layout method and apparatus of integrated circuit mask - Google Patents

Abstract

PURPOSE:To reduce a chip area by detecting a dimensional change through a substrate shape and by changing layout data so that the dimensional change is corrected. CONSTITUTION:Layout data and process data are inputted by an information input means 1 composed of mouth, keyboard, etc. Then, the mask layout of each layer is generated by a mask layout means 2 composed of a layout editor on the basis of the layout data given from the information input means 1. Subsequently, a difference-in-level part detection means 3 detects a place having a difference in level exerting an influence upon dimensions out of points, where arbitrary layers cross each other, on the basis of the layout data. Further, a substrate shape detection means 4 computes the shape of the difference-in-level part detected by the detection means 3 to detect a substrate shape. After that, actual dimensions in the difference-in-level part are computed from dimensions in the layout based on shape data of the difference-in-level part by the detection means 4 so that a design rule is changed in that part.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits (hereinafter referred to as
It is called LSI. ) LSI mask layout method and apparatus for creating a mask pattern.

0002

2. Description of the Related Art Conventionally, LSI mask patterns have been created using a so-called layout editor. This layout editor is realized as software on a computer. The layout editor is used to input figures for each layer using an external input device such as a mouse or keyboard, and create a mask pattern for each layer of the LSI.

By the way, each layer has graphical restrictions called design rules. This design rule is LSI
The mask pattern for each layer is automatically created based on these design rules.

0004

[Problem to be solved by the invention] As mentioned above, LSI
In the layout of LSI design rules,
There are constraints due to the manufacturing process, and the layout is based on these design rules.

[0005] According to the above-mentioned design rule, the minimum size of each layer is determined at the part with the most severe conditions. For example, in a metal layer, there is a possibility of disconnection due to a step at the intersection with a polysilicon layer or field oxide film, so it is necessary to set a design rule that is thicker than the required line width in a flat area. be. Therefore, even in areas where the line width is originally narrow enough, the layout is designed with wide dimensions, resulting in a corresponding increase in chip area.

By the way, after a layout is created, it is determined whether the circuit characteristics are suitable or not by prototyping and evaluating the pattern of the created layout and measuring the circuit characteristics. Then, when the circuit characteristics are not suitable, input data such as layout data and process data are changed and the layout is created again.

[0007] This method has a problem of inefficiency because it takes time to prototype and evaluate the created layout pattern.

[0008] The purpose of the first integrated circuit mask layout method and the integrated circuit mask layout apparatus according to the present invention is to select optimal dimensions for each region of a layer and perform layout to reduce the chip area. It is in.

It is an object of the second integrated circuit mask layout method and the integrated circuit mask layout apparatus according to the present invention to speed up the prototyping and evaluation of created layout patterns and to provide desired circuit characteristics. The goal is to create layouts efficiently.

0010

[Means for Solving the Problems] A first integrated circuit mask layout method according to the present invention is a system for creating an integrated circuit mask layout based on inputted figures of each layer, which comprises: After creating the layer, based on the layout data, from among the points where arbitrary layers intersect, locations with steps that affect the dimensions are detected, and the shape of the detected steps is calculated to determine the base shape. The method is characterized in that the layout dimensions of the layer are changed based on the detected base shape.

A first integrated circuit mask layout device according to the present invention is a device that creates a layout of an integrated circuit mask based on input figures of each layer, and inputs layout data and process data. an input means, a means for creating a mask layout based on data from the input means, and a means for detecting, based on the layout data, a point having a step that affects dimensions from among points where arbitrary layers intersect. and means for detecting the shape of the base by calculating the shape of the stepped portion detected by the detection means, and means for changing the layout dimensions of the layer based on the detected base shape. It is characterized by

A second integrated circuit mask layout method according to the present invention is a method for creating an integrated circuit mask layout based on the inputted figures of each layer, and the method includes inputting layout data and process data. 1st
a second step of creating data regarding the cross-sectional structure of the device based on the layout data and process data; and a second step of creating data regarding the cross-sectional structure of the device based on the layout data and process data; a third step of creating data regarding the characteristics; a third step of creating data regarding the circuit characteristics based on the spice parameters extracted from the data regarding the electrical characteristics of the device and the netlist extracted from the layout data; a fourth step of determining whether the circuit characteristic is a desired characteristic; and a fifth step of changing one or both of layout data and process data if the circuit characteristic is not a desired characteristic.
and a sixth step in which the processes of the second to fifth steps are repeated until the circuit characteristics become desired characteristics.

A second integrated circuit mask layout device according to the present invention is a device that creates a layout of an integrated circuit mask based on input figures of each layer, and inputs layout data and process data. an input means, a cross-sectional structure data creation means for creating data regarding the cross-sectional structure of the device based on the layout data and the process data; Create data on circuit characteristics based on an electrical property data creation means that creates data on the electrical properties of the device, spice parameters extracted from the data on the electrical properties of the device, and a netlist extracted from the layout data. a determining means for determining whether the circuit characteristics are desired characteristics; and, if the circuit characteristics are not the desired characteristics, one or both of layout data and process data; data changing means for changing the circuit characteristics; and means for repeatedly performing processing by the cross-sectional structure data generating means, the electrical characteristic data generating means, the circuit characteristic data generating means, the determining means, and the data changing means until the circuit characteristics become desired characteristics. It is characterized by comprising the following.

Further, the integrated circuit mask layout device according to the present invention performs the following operations based on the input figures of each layer.
A device for creating an integrated circuit mask layout, the device comprising:
input means for inputting layout data, inputting process data, inputting designation of data that can be changed among these data, and inputting change priority for the designated data; cross-sectional structure data creation means for creating data regarding the cross-sectional structure of the device; and electrical property data creation means for creating data regarding the electrical characteristics of the device based on the data regarding the cross-sectional structure of the device and preset bias conditions. a circuit characteristic data creation means for creating data regarding circuit characteristics based on spice parameters extracted from data regarding electrical characteristics of the device and a netlist extracted from layout data; a determining means for determining whether or not the circuit characteristic is the desired characteristic; a data changing means for changing the specified input data when the circuit characteristic is not the desired characteristic; The data changing means processes the specified input data in the order of change priority. It is characterized by changing one of the data.

[0015]

In the first integrated circuit mask layout method and apparatus according to the present invention, a dimensional change due to the underlying shape is detected, and layout data is changed to correct the dimensional change. Therefore, the design rules can be laid out using the minimum rules for each area, and the chip area can be reduced.

In the second integrated circuit mask layout method according to the present invention, first, layout data and process data are input (first step). Next, data regarding the cross-sectional structure of the device is created based on the layout data and process data (second step). Next, data regarding the electrical characteristics of the device is created based on data regarding the cross-sectional structure of the device and preset bias conditions (third step). Next, data regarding the circuit characteristics is created based on the spice parameters extracted from the data regarding the electrical characteristics of the device and the netlist extracted from the layout data (fourth step).

Next, it is determined whether or not the circuit characteristics are the desired characteristics, and if the circuit characteristics are not the desired characteristics, one or both of the layout data and the process data is changed (first step). 5 steps).

[0018] Then, the processes from the second step to the fifth step are repeated until the circuit characteristics become the desired characteristics (sixth step).

A second integrated circuit mask layout apparatus according to the present invention implements the above method.

Further, in the integrated circuit mask layout apparatus according to the present invention, the input means includes layout data input, process data input, designation input of changeable data among these data, and change priority input for the designated data. It is carried out by

The cross-sectional structure data creating means creates data regarding the cross-sectional structure of the device based on the data and the process data.

The electrical characteristic data creating means creates data regarding the electrical characteristics of the device based on data regarding the cross-sectional structure of the device and preset bias conditions.

The circuit characteristic data creation means creates data regarding circuit characteristics based on spice parameters extracted from data regarding electrical characteristics of the device and netlists extracted from layout data.

[0024] The determining means determines whether the circuit characteristic is a desired characteristic. If the circuit characteristic is not the desired characteristic, the data changing means changes the specified input data. Then, until the circuit characteristics become the desired characteristics, the cross-sectional structure data creation means,
Electrical characteristic data creation means, circuit characteristic data creation means,
Processing by the determining means and data changing means is repeated.

Data modification by the data modification means is carried out by modifying one of the specified input data in the order of modification priority.

[0026]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 to 6 show a first embodiment of the present invention.

FIG. 1 is a block diagram showing the configuration of the system of the first embodiment. Reference numeral 1 denotes an information input means consisting of a mouse, a keyboard, etc., which inputs layout data such as elements, configurations, and design rules of each layer. Enter.

Reference numeral 2 denotes a mask layout means consisting of a layout editor, which creates a mask layout for each layer based on the layout data given from the information input means 1. When creating this mask layout, in this embodiment, the dimensions required for the flat portion are set as a given design rule. For example, in a metal layer, the line width is set to the minimum required in a flat part.

The mask layout data created by the mask layout means 1 is temporarily stored in a data storage means 7 such as a hard disk.

Reference numeral 3 denotes a step detecting means, which detects an intersection of layers, that is, a step, based on the layout data provided by the mask layout means 2. Reference numeral 4 denotes a base shape detecting means composed of a shape simulator or the like that detects the base shape of the step portion detected by the step detecting means 3, and the base shape is determined by simulating the base shape using the given layout data of the step portion. The shape of the stepped portion can be derived. This base shape detection means 4
Among the LSI manufacturing processes, photolithography, deposition,
It simulates processes related to shape changes such as etching, and data on the base shape of this simulation is stored in a database.

Reference numeral 5 denotes a means for detecting dimensional changes due to the shape of the base, and based on the shape data of the stepped portion obtained by the base shape detecting means 4, the actual dimensions of the stepped portion are calculated from the dimensions on the layout, and the actual dimensions of the stepped portion are calculated from the dimensions on the layout. The design rule is changed and the changed data is provided to the information output means 6.

This calculation method may be configured to use a shape simulator or to accumulate actual measurement data of changes in dimensions due to the underlying shape and to calculate based on empirical rules. The above-mentioned change data is supplied from the information output means 6 to the data storage means 7, and the corresponding portion of the layout stored in the data storage means 7 is rewritten.

Each of the above-mentioned operations is performed under the control of control means 8 consisting of a CPU.

Next, the operation of the present invention will be further explained with reference to FIGS. 2 to 5. FIG. 2 is a flowchart showing the operating procedure of the present invention, FIG. 3 is a schematic diagram showing the data flow of this embodiment,
FIG. 4 is a plan view showing an example of the stepped portion, and FIG. 5 is A-A in FIG.
6 is a plan view of the main part of the stepped portion.

In this embodiment, as shown in FIG.
An example will be explained in which the first metal layer 18 crosses over the polysilicon layer 17.

FIG. 5 shows the shape when two layers intersect in this way. As shown in FIG. 5, a polysilicon layer 17 is provided on a substrate 15, and a first metal layer 18 is provided thereon with a PSG film 21 as an interlayer insulating film interposed therebetween. The region indicated by 19 in this figure gives the metal layer 18 an influence due to the difference in level. Therefore, it is necessary to increase the line width in order to prevent the metal wiring from forming a dashed line in this portion.

Furthermore, a second metal layer is provided on this metal layer 18 with an interlayer insulating film 23 interposed therebetween in order to connect this second metal layer and the first metal layer 18 through a through hole. , a through hole is formed in the interlayer insulating film 23. In order to form this through hole, a resist 22 is provided on the interlayer insulating film 23, and this resist 22 is patterned by a photolithography process.

This photoengraving process is also affected by the stepped portion. That is, in the area indicated by 20 in the figure, the through hole 24 of the mask pattern formed in the resist 22 is enlarged by the amount indicated by a in the figure, as shown in FIG. Become. However, this is a case where the resist 22 is a positive type resist. Therefore, regarding this portion, the layout of the through holes 24 may be done in consideration of the influence of the difference in level. In other words, if the layout of the through holes 24 is made smaller by that portion in consideration of the increase in size due to the reflection of light, the pattern of the through holes 24 formed in the register 22 will be adjusted to the actual required size. You can get the size.

Therefore, if the through holes in the area indicated by 20 in the figure are formed using the initial layout data, "
Since it is larger by "a", you can correct the initial layout data to make it smaller by "a".However, if you make the mask smaller by "a", the mask will actually become smaller by "a", and photolithography When the amount of light decreases, the dimension does not increase by the expected width of "a".Therefore, when the layout data is made smaller by "a", it is necessary to further apply a correction value.

FIG. 3 is a schematic diagram showing the flow of each data in this embodiment. In this diagram, 20 is a layout editor as a mask layout means, and 21 is a layout data conversion device for changing dimensions depending on the underlying shape. ,2
2 is a shape simulator. These layout editor 20, layout data conversion device 21, and shape simulator 22 are configured by computer software.

Reference numerals 23 to 26 indicate storage means such as a hard disk in which each data is stored, and the layout data created by the layout editor 20 is first stored in the step layout data storage means 23. Layout data is provided from the step layout data storage means 23 to the shape simulator 22 and the layout data conversion device 21.

The shape simulator 22 simulates the cross-sectional shape of the base based on the provided layout data and various setting conditions such as etching and deposition.
The simulation data is provided to the base cross-sectional shape storage means 24 which stores the base cross-sectional shape.

The base cross-sectional shape storage means 24 stores each base cross-sectional shape based on simulation data, and this cross-sectional shape data is given to the shape simulator 22. The shape simulator 22 performs lithography simulation based on the given cross-sectional shape data,
Data affected by the step is provided to resist dimension storage means 25 that stores resist dimensions.

The resist data from the resist dimension storage means 25 is provided to the layout data conversion device 21.

The layout data conversion device 21 changes the layout dimensions based on the data from the step layout data storage means 23 and the resist dimension storage means 25, and supplies the changed data to the layout data storage means 26 as new layout data.

Next, the operation of this embodiment will be further explained with reference to the flowchart shown in FIG. First, a layout for each layer is created using the layout editor 20 based on layout data such as design rules (step S1).
.

Next, based on the layout data from the layout editor 20, the intersection of the layout data, that is, the stepped portion is detected by the step detecting means 3 (
Step S2).

Thereafter, the base shape is detected based on the base shape data stored in the database 14 (step S3).

[0050] After that, the dimensions of the layout are changed based on the data stored in the database 15 that requires changing the dimensions of each layer based on the base shape (step S4), and the layout data is changed. (Step S5), and the operation ends.

[0051] In the above-mentioned embodiment, a case was explained in which the dimensions of the layout were changed by the stepped portion, but in addition, in the portion where a large current flows in circuit operation, taking into consideration the influence of the current, The configuration may be such that the width of the wiring etc. is changed.

FIGS. 7 and 8 show a second embodiment of the invention.

FIG. 7 is a block diagram showing the configuration of a system according to the second embodiment. Reference numeral 31 denotes information input means consisting of a mouse, a keyboard, etc., into which layout data and process data are input. Layout data includes elements, configurations, design rules, etc. of each layer. The process data includes process parameters such as impurity energy, dose amount, and diffusion time, process flow, and the like.

A layout editor 32 creates a mask layout for each layer based on the layout data given from the information input means 31. The mask layout data created by this layout editor 32 is temporarily stored in a data storage means 37 such as a hard disk.

Reference numeral 33 denotes a process simulator, which generates data regarding the device cross-sectional structure, such as oxide film thickness and impurity diffusion depth, based on the mask layout data given by the layout editor 32 and the process data given by the information input means 31. Create.

A device simulator 34 creates data regarding the electrical characteristics of the device based on data on the device cross-sectional structure and bias conditions provided by the process simulator 33.

A circuit simulator 35 calculates delay times, output waveforms, etc. based on spice parameters extracted from device electrical characteristic data given by the device simulator 34 and a netlist extracted from mask layout data. Create data regarding circuit characteristics.

A display device 36 displays a layout screen and the results of each simulator.

Each of the above-mentioned operations is performed under the control of a control means 38 consisting of a CPU.

Next, the operation of this embodiment will be further explained with reference to the flowchart of FIG.

First, the user inputs layout data and process data from the information input means 31 (step S11).

Next, the process simulator 33 creates data regarding the cross-sectional structure of each device based on the layout data and process data (step S12). At this time, there is no need to simulate all parts of the layout;
We simulate parts such as field oxidation parts,
Expand throughout.

Next, the device simulator 34 creates data regarding the electrical characteristics of each device based on the data regarding the cross-sectional structure of each device obtained by the process simulator 33 and preset bias conditions. (Step S13).

Next, the circuit simulator 35 calculates the delay time, Data regarding circuit characteristics such as output waveforms are created (step S14).

Next, it is determined whether the circuit characteristics obtained by the circuit simulator 35 are the desired characteristics (
Step S15): If the desired characteristics are obtained, this process ends.

If the circuit characteristics obtained by the circuit simulator 35 are not the desired characteristics, one or both of the layout data and process data is changed (step S16), the process returns to step S12, and steps S12 to S15 are performed. processing is performed. Then, the processes of steps S12 to S15 are repeated until the circuit characteristics obtained by the circuit simulator 35 become the desired characteristics.

The layout data and process data in step S16 may be changed manually by the user or automatically.

To automatically change the layout data and process data, when inputting the layout data and process data in step S11 above, specify the changeable parameters and input the change priority of the specified parameters. Then, when the process of step S16 is performed, one parameter may be automatically changed in order of priority.

[0069]

Effects of the Invention According to the first integrated circuit mask layout method and the integrated circuit mask layout apparatus according to the present invention, a dimensional change due to the underlying shape is detected, and the layout data is adjusted so as to correct the dimensional change. By changing the design rules, it is possible to perform layout in that area using the minimum rules. Therefore,
A layout with a small chip area can be achieved.

According to the second integrated circuit mask layout method according to the present invention and the integrated circuit mask layout apparatus according to the present invention, it is possible to rapidly prototype and evaluate the created layout pattern, and it is possible to quickly produce and evaluate a created layout pattern, and to obtain a pattern having desired circuit characteristics. You can create layouts efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the system configuration of a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing the data flow of the system according to the first embodiment of the present invention.

FIG. 4 is a plan view showing the layout shape of an LSI.

[Figure 5] A-A' in Figure 4 showing the layout shape of the LSI
FIG.

FIG. 6 is an enlarged plan view of main parts showing the layout shape of the LSI.

FIG. 7 is a block diagram showing the system configuration of a second embodiment of the invention.

FIG. 8 is a flowchart illustrating the operation of a second embodiment of the invention.

[Explanation of symbols]

2 Mask layout means 3 Step detection means 4 Base detection means 5 Dimensional change detection means 8 Control means 31 Information input means 32 Layout editor 33 Process simulator 34 Device simulator 35 Circuit simulator 38 Control means

Claims (5)

[Claims] Claim 1: A method for creating a layout of an integrated circuit mask based on input figures of each layer, the method comprising: creating a layout of an integrated circuit mask, and then creating a layout between points where arbitrary layers intersect based on the layout data; Detecting a location with a step that affects the dimensions, detecting the base shape by calculating the shape of the detected step, and changing the layout dimensions of the layer based on the detected base shape. An integrated circuit mask layout method characterized by: 2. An apparatus for creating a layout of an integrated circuit mask based on input figures of each layer, comprising: input means for inputting layout data and process data; and data from the input means. means for creating a mask layout; means for detecting a location with a step that affects dimensions from points where arbitrary layers intersect based on the layout data; A layout device for an integrated circuit mask, comprising means for detecting a base shape by calculating the shape, and means for changing layout dimensions of a layer based on the detected base shape. 3. A method for creating a layout of an integrated circuit mask based on input figures of each layer, the method comprising a first step of inputting layout data and process data.
a second step of creating data regarding the cross-sectional structure of the device based on the layout data and the process data; a third step of creating data regarding the characteristics; a third step of creating data regarding the circuit characteristics based on the spice parameters extracted from the data regarding the electrical characteristics of the device and the netlist extracted from the layout data; a fourth step of determining whether the circuit characteristic is a desired characteristic, and a fifth step of changing one or both of the layout data and the process data if the circuit characteristic is not the desired characteristic. , until the circuit characteristics become the desired characteristics.
A method for layout of an integrated circuit mask, comprising a sixth step in which the processes from the second step to the fifth step are repeated. 4. An apparatus for creating a layout of an integrated circuit mask based on the input figures of each layer, the apparatus comprising: input means for inputting layout data and process data; and input means for inputting layout data and process data; cross-sectional structure data creation means for creating data on the cross-sectional structure of the device based on the data on the cross-sectional structure of the device; and electrical characteristics for creating data on the electrical characteristics of the device based on the data on the cross-sectional structure of the device and preset bias conditions. a data creation means; a circuit property data creation means for creating data on circuit characteristics based on spice parameters extracted from data on electrical characteristics of the device and a netlist extracted from layout data; a determining means for determining whether the circuit characteristic is a desired characteristic; a data changing means for changing one or both of layout data and process data when the circuit characteristic is not the desired characteristic; An integrated circuit mask layout device comprising: means for repeatedly performing processing by a cross-sectional structure data generating means, an electrical characteristic data generating means, a circuit characteristic data generating means, a determining means, and a data changing means until desired characteristics are achieved. . 5. An apparatus for creating a layout of an integrated circuit mask based on the inputted figures of each layer, the apparatus comprising inputting layout data, inputting process data, and inputting designation of changeable data among these data. an input means for inputting change priority for specified data; a cross-sectional structure data creation means for creating data regarding the cross-sectional structure of the device based on layout data and process data; and data regarding the cross-sectional structure of the device. an electrical characteristic data creation means for creating data regarding the electrical characteristics of the device based on the bias conditions set in advance; and a spice parameter extracted from the data regarding the electrical characteristics of the device and the layout data. a circuit characteristic data creation means for creating data regarding circuit characteristics based on a netlist, a determining means for determining whether or not the circuit characteristics are desired characteristics, and when the circuit characteristics are not the desired characteristics; includes a data changing means for changing the specified input data, a cross-sectional structure data generating means, an electrical characteristic data generating means, a circuit characteristic data generating means, a determining means, and a cross-sectional structure data generating means until the circuit characteristics become the desired characteristics. 1. A layout device for an integrated circuit mask, comprising means for repeatedly performing processing by the data changing means, wherein the data changing means changes one of the specified input data in order of change priority.