JP3223718B2 - How to create mask data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lithography technique for producing semiconductors.

[0002]

[Prior Art] In recent years, the miniaturization of semiconductors has progressed more and more,
The processing rules are approaching the wavelength of the light to be transferred. Accordingly, the difference between the design dimension and the processing dimension due to the optical proximity effect cannot be ignored. For this reason, it is necessary to correct the mask once formed, which is burdened both in terms of time and cost. In recent years, with the increase in the number of masks due to the complexity of the process and the increase in the mask price due to the enlargement of the mask size, the problem has been increasing.

Hereinafter, an example of the above-described conventional mask repair method will be described with reference to the drawings.

FIG. 32 shows a flowchart of a conventional mask correcting method. In FIG. 32, 1 is design data, 2 is a mask created from the design data, 3 is a processed pattern exposed by the mask, and 4 is the processed data. Reference numeral 22 denotes a mask fed back by the processing data 4, and reference numeral 33 denotes a pattern processed as designed.

[0005] The operation of the mask repair method configured as described above will be described below. First, in order to design an LSI chip, the design data 1 of each layer is
Created on AD. Next, a mask 2 for actually transferring the data to a pattern is created from the data. The mask 2
Is used to transfer the pattern to the chips on the wafer. The dimension data 4 of the transferred pattern 3 is measured, the data portion at a location different from the designed dimension is improved to a desired dimension, and a new mask 22 is created again.

[0006]

However, in the above configuration, the time required to measure the transferred pattern data, the time required to create a new mask, and the cost thereof increase, and a large burden is imposed on product development. There was a problem that.

The present invention has been made in view of the above-described problems, and when design data is created, a portion where a desired dimension value cannot be obtained in advance is determined.
Locate, there is provided a mask data creation method for creating a mask to correct the data.

[0008]

In order to solve the above-mentioned problems, the present invention provides a step of inputting mask design data to a mask data input section, and a step of inputting a gate wiring pattern and an active region from the input mask design data. Extracting the overlapped portion as a gate pattern; extracting a gate edge from the gate pattern; calculating a light intensity value in the vicinity of the gate edge of the gate pattern; Calculating the size shift amount of the gate line width due to the effect, extracting the gate pattern in which the size shift amount is larger than a predetermined value, and calculating the gate pattern in which the size shift amount is larger than a predetermined value. Defining a correction amount of the gate line width of the gate pattern based on the size shift amount, and correcting the specified gate line width. Line width of the gate pattern based on
Is corrected to create a mask data of a gate wiring pattern. A step of inputting mask design data to a mask data input unit; a step of extracting a portion where a gate wiring pattern and an active region overlap with each other as a gate pattern from the input mask design data; Extracting the light intensity value on the gate edge, and calculating the light intensity value on the gate edge when the difference between the light intensity value on the gate edge and a predetermined threshold is smaller than a predetermined value. Outputting mask data and correcting the mask data of the gate wiring pattern when the difference between the light intensity on the gate edge and a predetermined threshold value is larger than a predetermined value. modification, the line correction of line width of the gate pattern until the difference between the light intensity and the threshold value on the gate edge becomes smaller than a predetermined value ,
After that, a method of generating mask data for outputting the mask data of the corrected gate wiring pattern is adopted.

[0009]

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

According to the present invention , the dimensions of each gate are determined by the above configuration.
The dimensions corresponding to the shift amount can be corrected for each gate.
For LSIs with reduced gate line width variation
Mask data can be created. Further, the present invention provides the above-described configuration.
The amount of dimensional shift between adjacent gate patterns
Have a high-density gate pattern
LSI with reduced gate line width variation
Disc data can be created.

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

【Example】

(Embodiment 1) The configuration of a mask data verification device according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a mask data verification device according to a first embodiment of the present invention. In FIG. 1, 102 is a mask data input unit, 103 is an inspection area extraction unit, 104 is a light intensity calculation unit, 105 is a shape calculation unit, 10
Reference numeral 6 denotes a developing / dissolving speed calculating unit, 107 denotes an inspection unit, 108 denotes a warning point extracting unit, and 109 denotes a display unit.

FIG. 2 is a flowchart of an operation method of the mask data verification device configured as described above.

The operation of the mask data verifying apparatus will now be described.
A method of verifying mask data according to the present embodiment will be described.

First, the mask data input unit 102
The mask data designed by a predetermined design device is input. Next, an inspection area is extracted from the mask data input from the mask data input section 102 by the inspection area extraction section 103. Next, the light intensity calculation unit 104 calculates the light intensity distribution in the inspection area extracted by the inspection area extraction unit 103. Next, the development dissolution rate calculation unit 106 calculates the development dissolution rate distribution of the resist. Next, the shape calculation unit 10
5 by calculating the machining shape in a more lithographic process <br/> combining the developing dissolution rate distribution and the light intensity distribution.
Next, the inspection unit 107 inspects a margin in the lithography process of the processed shape calculated by the shape calculation unit 105. Next, the inspection unit 107 is output by the warning location extraction unit 108.
Extracts portions where the margin in the lithography process satisfies the regulation. Finally, the display unit 109 displays the portion extracted by the warning location extraction unit 108 as a warning location on a CRT or the like, and ends the operation of the mask data verification device.

As described above, according to this embodiment, the light intensity
By combining the cloth and the development dissolution rate distribution, the margin in the lithography process is evaluated from the design data, and LSI
Can be found at the stage of design data, and mask data corrected by a design change can be created.

(Embodiment 2) The configuration of a mask data generating apparatus according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a configuration of a mask data generating apparatus according to a second embodiment of the present invention.

In FIG. 3, reference numeral 202 denotes a mask data input unit, 203 denotes an inspection area extraction unit, 204 denotes a light intensity calculation unit,
205 is a shape calculation unit, 206 is a development dissolution rate calculation unit, 2
Reference numeral 07 denotes an inspection unit, and the above configuration is the same as the configuration of the first embodiment shown in FIG.

The difference from the first embodiment is that a mask data correction unit 208 and a mask data output unit 209 are provided.

FIG. 4 is a flowchart of an operation method of the mask data generating apparatus configured as described above.

The operation of the mask data generating apparatus will be described below.
A method of creating mask data according to the present embodiment will be described.

First, the mask data input unit 202
The mask data designed by a predetermined design device is input. Next, the inspection region is extracted from the mask data input from the mask data input unit 202 by the inspection region extraction unit 203. Next, the light intensity calculation unit 204 calculates a light intensity distribution in the inspection area extracted by the inspection area extraction unit. Next, the development dissolution rate calculation unit 206 calculates the development dissolution rate distribution of the resist. Next, the processed shape in the lithography process is calculated by combining the light intensity distribution and the development dissolution rate distribution by the shape calculation unit 205. Next, the inspection unit 207 inspects a margin in the lithography process of the processed shape calculated by the shape calculation unit 205, and extracts a portion where the margin in the lithography process does not satisfy the regulation. The above operation is the same as in the first embodiment.

Next, the mask data correcting section 208 corrects a portion in the lithography process where the margin does not satisfy the regulation so as to satisfy the regulation. Next, the processing shape in the lithography process is calculated again for the mask data newly corrected by the shape calculation unit 205, and the correction by the inspection unit 207 and the mask data correction unit 208 is performed in the following manner. Repeat until you are satisfied. Finally, when the margin in the lithography process satisfies the regulation in all the patterns, the mask data output unit 209 outputs the corrected mask data, thereby ending the operation of the mask data verification device.

As described above, according to the present embodiment, the margin in the lithography process is evaluated from the design data, and the part in which the margin in the lithography process does not satisfy the regulation is corrected until the margin is satisfied. It is possible to create mask data in which quality deterioration has been corrected.

(Embodiment 3) A configuration of a mask data verifying apparatus according to a third embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows the configuration of a mask data verifying apparatus according to a third embodiment of the present invention. This embodiment is a mask data verifying apparatus focusing on a gate whose dimension is particularly important.

In FIG. 5, reference numeral 302 denotes a mask data input unit, 303 denotes a gate region extraction unit, 304 denotes a gate edge extraction unit, and 305 denotes a size shift calculation unit for each gate line width.
08 is a warning item extraction unit, and 309 is a display unit.

FIG. 6 is a flowchart of an operation method of the mask data verifying apparatus configured as described above.

The operation of the apparatus for verifying the variation of the gate line width and the method of verifying the mask data in this embodiment will be described below with reference to FIGS.

First, the mask data input unit 302
The mask data designed by a predetermined design device is input. Next, a gate pattern 313 is extracted by the gate region extracting unit 303 from the overlap of the gate wiring pattern 311 and the active region 312 of the mask data input from the mask data input unit 302. Next, the gate edge extraction unit 304 extracts a gate edge 314 that is the opposite side of the gate length from the gate pattern extracted by the gate region extraction unit 303. Next, the gate line pattern 311 is input from the mask data input unit 302 by the dimension shift amount evaluation unit for each gate line width, and the gate edge 3 is input from the gate edge extraction unit 304.
14 is input, the light intensity near the gate edge is calculated, and the dimensional shift amount due to the proximity effect is evaluated based on the light intensity value.

As an example, evaluation points 315 spaced apart from each other by 0.1 to 0.2 μm are set on the gate edge and on both sides thereof, and the light intensity distribution 316 at each evaluation point is calculated. Threshold 3 which becomes critical resolution intensity from the slope of distribution
There is a method of calculating the dimensional shift amount 318 from 17.

Next, the gate line pattern 311 is input from the mask data input unit 302 by the warning point extraction unit 308, and the dimensional shift amount 318 of the gate line width is input from the dimensional shift amount evaluation unit 305 of each gate line width. If the shift amount is larger than the predetermined value, 319 is extracted. Finally, the display unit 309 displays the portion 319 extracted by the warning location extraction unit 308 as a warning location on a CRT or the like, and ends the operation of the mask data verification device.

According to the present embodiment as described [0047] above, extracts the gate edge, the dimensional shift of only the gate line width calculating the light intensity in the vicinity thereof can be evaluated, the variation of the gate line width due to the proximity effect Degradation of LSI quality due to the design data, and the change in gate line width due to design change
It becomes possible to create the mask data of the gate wiring corrected so as to suppress the crack .

(Embodiment 4) A configuration of a mask data generating apparatus according to a fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 9 shows the configuration of a mask data generating apparatus according to the fourth embodiment of the present invention.

In FIG. 9, reference numeral 402 denotes a mask data input unit, 403 denotes a gate region extraction unit, 404 denotes a gate edge extraction unit, and 405 denotes a dimension shift calculation unit for each gate line width. This is the same as the configuration of the mask data creation device in the embodiment.

The difference from the configuration of FIG. 5 is that a line width correction amount defining section 406, a mask data correction section 408, and a mask data output section 409 are provided.

FIG. 10 is a flow chart of an operation method of the mask data generating apparatus configured as described above.

The operation of the gate line width correcting apparatus configured as described above and the method of creating gate wiring mask data in the present embodiment will be described with reference to FIGS.

First, the mask data input unit 402
The mask data designed by a predetermined design device is input. Next, a gate pattern is extracted by the gate region extraction unit 403 from the overlap of the gate wiring pattern of the mask data input from the mask data input unit 402 and the active region. Next, the gate edge which is the opposite side of the gate length is extracted by the gate edge extraction unit 404 using the gate pattern extracted by the gate region extraction unit 403. Next, the mask data input unit 4 is operated by the dimension shift amount evaluation unit 405 for each gate line width.
02, the gate wiring pattern is input, the gate edge is input from the gate edge extraction unit 404, the light intensity near the gate edge is calculated, and the dimensional shift amount due to the proximity effect is evaluated based on the light intensity value. The above operation is the same as in the third embodiment.

Next, the line width correction amount specifying unit 406 specifies the correction amount for each gate pattern edge based on the size shift amount calculated by the size shift amount evaluation unit. Here, the correction amount for each gate pattern edge portion is defined by the gate edge and the line width parameter 419. For example, when correcting the gate line width to be 0.1 μm thicker, a line width parameter +0.1 is given to the gate edge. Conversely, when correcting the gate line width to be 0.1 μm thinner, a line width parameter −0.1 is given to the gate edge.

Next, the mask data of the gate wiring corrected by the mask data correcting unit 408 based on the gate line width correction amount set by the correction amount defining unit 406 is created. Here, first, the gate edge 414 and the line width parameter 41
From FIG. 9, the gate line width corrected graphic 4 having a width twice the value specified by the line width parameter centering on the gate edge portion
Create 20. Next, the gate line width correction graphic having the line width parameter having a positive value was added to the gate wiring mask data, and the gate line width correction graphic having the negative value was corrected by subtracting it from the gate wiring mask data. The mask data 421 of the gate wiring is created. Finally, the mask data output unit 409 outputs the corrected mask data, thereby ending the operation of the mask data creation device.

As described above, according to the present embodiment, by setting the line width correction amount defining section by the proximity effect and the mask data correction section, the correction is made so as to suppress the variation of the gate line width due to the proximity effect. It becomes possible to create mask data of the gate wiring.

Here, the light intensity in the vicinity of the gate edge was calculated, and the dimensional shift amount due to the proximity effect was evaluated from the light intensity value. However, the dimensional shift amount was evaluated using the light intensity calculation and the development dissolution rate calculation. Is also good.

(Embodiment 5) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 13 shows the configuration of a mask data generating apparatus according to the fifth embodiment of the present invention.

In FIG. 13, reference numeral 502 denotes a mask data input unit, 503 denotes a gate region extraction unit, 504 denotes a gate edge extraction unit, and 505 denotes a size shift calculation unit for each gate line width.
Reference numeral 09 denotes a mask data output unit, which has the same configuration as that of the fourth embodiment shown in FIG. 9 is different from FIG. 9 in that a waveform edge graphic generation unit 507 is provided instead of the line width correction amount defining unit 406, and a mask data correction unit 508 corresponds thereto.

As a result, a function of adjusting the line width formed in the lithography process by changing the pitch of the waveform of the waveform edge figure instead of changing the line width of the actual mask data is provided.

FIG. 14 is a flowchart of an operation method of the mask data creating apparatus configured as described above.

The operation of the gate line width correcting apparatus configured as described above and the method of creating gate wiring mask data in the present embodiment will be described with reference to FIGS.

First, the mask data input unit 502
The mask data designed by a predetermined design device is input. Next, a gate pattern is extracted by the gate region extraction unit 503 from the overlap of the gate wiring pattern of the mask data input from the mask data input unit 502 and the active region. Next, the gate edge which is the opposite side of the gate length is extracted by the gate edge extraction unit 504 using the gate pattern extracted by the gate region extraction unit 503. Next, the mask data input unit 5 is operated by the dimension shift amount evaluation unit 505 for each gate line width.
02, a gate wiring pattern is input from the gate edge extraction unit 504, and a light intensity near the gate edge is calculated, and a dimensional shift amount due to the proximity effect is evaluated from the light intensity value. The above operation is performed in the fourth operation.
This is the same as the embodiment.

Next, each gate pattern is transformed into a waveform edge graphic 521 by the waveform edge graphic creation unit 507 based on the dimension shift amount calculated by the dimension shift amount evaluation unit 505, and parameters representing the waveform edge are set.

As shown in FIG. 17, the relationship between the parameter representing the waveform edge and the line width dimension formed in the lithography process is such that the line width formed in the lithography process can be changed by changing the pitch width of the waveform edge figure. Can be modified.
In FIG. 17, reference numeral 522 denotes a dimension Dw of the amplitude of the waveform edge.
523 is the pitch width Pw of the waveform edge,
Numeral 24 denotes the size Ow of the peak of the waveform edge. Here, as an example, when the dimension Dw of the amplitude of the waveform edge is fixed to 0.05 μm and the dimension Ow of the peak portion of the waveform edge is fixed to 0.2 μm in a waveform edge figure having a line width W of 0.4 μm, The line width dimension calculated from the light intensity when the pitch width Pw is changed from 0.20 μm to 0.25 μm is shown at 525. However, the calculation condition is that the light source is i-line and the interference is
The numerical aperture is 0.6 at 0.6.

As described above, when the waveform edge figure is used, the value of 0.
By using a pitch figure that can be created with dimensional control of about 05 μm (actually, 0.25 μm if a 5 × mask is used), it is possible to correct the dimension of about 0.01 μm to the pattern formed in the lithography process.

In order to control a dimension of about 0.01 μm (actually, 0.05 μm if a 5-fold mask is used) in the preparation of a mask, it is necessary to prepare a very expensive mask. In the method used, a sufficient effect can be obtained without using an expensive mask.

Next, the mask data correction unit 508 creates mask data 521 of the gate wiring corrected so that the waveform edge figure created by the waveform edge figure creation unit 507 becomes a gate pattern. Finally, the mask data output unit 509 outputs the corrected mask data, thereby ending the operation of the mask data creation device.

As described above, according to the present embodiment, it is possible to create mask data of a gate wiring corrected so as to suppress variations in gate line width due to the proximity effect without using an expensive mask. Become.

Here, the dimension adjustment using the waveform edge figure was performed by changing the pitch width of the waveform edge.
The size of the peak of the waveform edge or the size of the amplitude of the waveform edge may be changed individually or in combination.

[0073] Incidentally, the light intensity calculated at the gate edge near here, has been evaluated dimensional shift due to the proximity effect than its intensity value, and evaluates the dimensional shift amount using the developer dissolution rate calculation and light intensity calculation You may.

(Embodiment 6) Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 18 shows the configuration of a mask data generating apparatus according to the sixth embodiment of the present invention.

In FIG. 18, 602 is a mask data input unit, 603 is a gate region extracting unit, 604 is a gate edge extracting unit, 605 is a size shift calculating unit for each gate line width, and 6
Reference numeral 09 denotes a mask data output unit, which has the same configuration as that of the fourth embodiment shown in FIG.

The difference from the fourth embodiment shown in FIG.
7 is provided in place of the line width correction amount defining unit 406, and the mask data correcting unit 608 corresponds thereto.

Thus, instead of directly changing the mask pattern serving as the gate region, an auxiliary pattern parallel to the mask pattern serving as the gate region is added.
It has a function of suppressing the proximity effect due to the pattern density.

FIG. 19 is a flow chart of the operation method of the mask data generating device configured as described above.

The operation of the mask data generating apparatus configured as described above and the method of generating the gate wiring mask data in the present embodiment will be described with reference to FIGS.

First, the mask data input unit 602
The mask data designed by a predetermined design device is input. Next, a gate pattern is extracted by the gate region extracting unit 603 from the overlap of the gate wiring pattern of the mask data input from the mask data input unit 602 and the active region. Next, a gate edge which is the opposite side of the gate length is extracted by the gate edge extraction unit 604 using the gate pattern extracted by the gate region extraction unit 603. Next, the mask data input unit 6 is operated by the dimension shift amount evaluation unit 605 of each gate line width.
02, a gate wiring pattern is input, a gate edge is input from the gate edge extraction unit 604, light intensity near the gate edge is calculated, and a dimensional shift amount due to the proximity effect is evaluated based on the light intensity value. The above operation is the same as in the fourth embodiment.

Next, an auxiliary pattern 619 parallel to the mask pattern serving as the gate region is created by the parallel auxiliary pattern creation section 607 based on the dimension shift amount calculated by the dimension shift amount evaluation section 605. As the relationship of the line width to be formed in a lithography process is shown in Figure 22 when adding the parallel auxiliary pattern, the line width formed in a lithography process can be modified by adding a parallel auxiliary patterns. Next, the mask data 621 of the gate wiring corrected by the mask data correction unit 608 is created. Finally, the mask data output unit 609 outputs the corrected mask data, thereby ending the operation of the mask data creation device.

As described above, according to the present embodiment, a gate wiring mask modified to suppress variations in gate line width by adding an auxiliary pattern parallel to a mask pattern serving as a gate region. Data can be created.

[0084] Incidentally, the light intensity calculated at the gate edge near here, has been evaluated dimensional shift due to the proximity effect than its intensity value, and evaluates the dimensional shift amount using the developer dissolution rate calculation and light intensity calculation You may.

The gate line width may be adjusted by a combination of a plurality of methods including the method according to the present embodiment, the line width parameter method according to the fourth embodiment, and the waveform edge graphic method according to the fifth embodiment.

(Embodiment 7) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 23 shows the configuration of a mask data creation device according to the seventh embodiment of the present invention.

In FIG. 23, 702 is a mask data input unit, 703 is a gate region extraction unit, 704 is a gate edge extraction unit, 707 is a line width correction amount defining unit, 708 is a mask data correction unit, and 709 is a mask data output unit. The above is the same as the configuration of the fourth embodiment shown in FIG.

The difference from the fourth embodiment shown in FIG.
705 instead of the size shift calculator for each gate line width
Is that a light intensity calculation unit on the gate edge of (1) and a determination unit (706) are provided. This provides a function that can correct the individual gate line width with almost the same accuracy.

FIG. 24 is a flow chart of the operation method of the mask data creating apparatus configured as described above.

The operation of the mask data creating apparatus configured as described above and the method of creating the gate wiring mask data in this embodiment will be described.

First, the mask data input unit 702
The mask data designed by a predetermined design device is input. Next, a gate pattern is extracted by the gate region extracting unit 703 from the overlap of the gate wiring pattern of the mask data input from the mask data input unit 702 and the active region. Next, a gate edge which is the opposite side of the gate length is extracted by the gate edge extraction unit 704 using the gate pattern extracted by the gate region extraction unit 703. The above operation is the same as in the fourth embodiment.

Next, a light intensity calculator 705 on the gate edge
To calculate the light intensity on the gate edge. this is,
Simply set some evaluation points on the gate edge and calculate the light intensity at that point. Next, the light intensity on the gate edge calculated by the light intensity calculation unit on the gate edge by the determination unit 706 is compared with a predetermined threshold value, and whether the difference between each light intensity and the threshold value is smaller than a predetermined value is determined. Is determined.
At this time, if the difference is smaller than the predetermined value, the process shifts to the mask data output unit and ends. If not, the process shifts to the line width correction amount defining unit 707. Line width correction amount defining unit 70
In step 7, a line width correction value proportional to the difference between the light intensity on the gate edge and a predetermined threshold is set. That is, when using a positive resist in the lithography process,
When the light intensity is larger than the threshold value, the correction amount is changed so that the gate line width becomes large in the gate line width correction amount. When the light intensity is smaller than the threshold value, the correction amount is changed so that the gate line width becomes smaller in the gate line width correction amount. However,
When using a negative resist in the lithography process
Oite is, and vice versa to. The method of defining the amount of correction is the second
In the same manner as in the embodiment, it may be expressed by the gate edge data and the line width parameter. Further, after defining the line width correction amount, the mask data of the gate wiring corrected by the mask data correction unit is created. The method of creating the corrected gate wiring mask data is the same as that of the fourth embodiment. Further, thereafter, the light intensity on the gate edge is calculated again by the light intensity calculation unit on the gate edge using the corrected mask data of the gate wiring created by the mask data correction unit. The operation from the determination unit to the light intensity calculation unit on the gate edge is repeated until the difference between the light intensity on each gate edge and a predetermined threshold value becomes smaller than a predetermined value.

As described above , according to the present embodiment , the line widths of adjacent gates can be simultaneously and accurately corrected, and mask data of a corrected gate wiring effective for an LSI having a structure in which gates are densely formed is created. It becomes possible.

The gate line width may be adjusted by using the waveform edge figure shown in the fifth embodiment.

FIG. 25 shows the configuration of a mask data generating apparatus when a waveform edge figure is used in this embodiment. FIG. 26 is a diagram showing a flowchart of an operation method of the mask data creating apparatus when a waveform edge figure is used.

As a result, even for an LSI having a structure in which gates are densely arranged without using an expensive mask, individual gate line widths can be corrected more accurately.

The parallel auxiliary pattern of the sixth embodiment may be used for adjusting the gate line width. FIG. 27 shows the configuration of a mask data creation device when a parallel auxiliary pattern is used in this embodiment. As a result, a gate having a large line width becomes thin, and variations in the line width can be suppressed as a whole. FIG. 28 shows a result of a simulation and an experimental value of a parameter for arranging the auxiliary pattern and how the isolated line width changes according to the parameter. It can be seen that the line width can be controlled by adjusting the parameters W and S1. FIG. 29 is a diagram showing a flowchart of an operation method of the mask data creation device when the parallel auxiliary pattern is used.

The adjustment of the gate line width may be performed by combining a plurality of methods of the method of the present embodiment, the method of the waveform edge figure of the fifth embodiment, and the method of the parallel auxiliary pattern of the sixth embodiment.

Embodiment 8 Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 30 is a flowchart for creating a parallel auxiliary pattern. FIG. 31 is a simplified diagram of a series of these processes. First, gate design data is input. Next, mask data 1 is created by enlarging and resizing the data by a predetermined amount. When the size is reduced and resized again by a predetermined amount, the gate and the gate wiring having an interval of half or less of the predetermined amount are connected to one (FIG. 31B). Next, the mask data 2 is created by resizing the mask data 1 by the width W of the auxiliary pattern and the interval S1 between the auxiliary pattern and the gate. Next, mask data 3 is created by enlarging and resizing the mask data 1 by the gate interval S1 with the auxiliary pattern. When the logical processing of subtracting the mask data 3 from the mask data 2 is performed, mask data 4 in which an auxiliary pattern is formed around the mask data 1 is generated (FIG. 31C). Next, by performing an AND process between the mask data 4 and the active region, mask data 5 for forming an auxiliary pattern on the active region is obtained. Finally, the mask of the parallel auxiliary pattern is formed by combining the design data with the mask data 5 (FIG. 31).
(D)).

[0102]

As described above, according to the present invention, the gate line
Mask mask modified to suppress variations in width
Data can be created. In addition,
The line width can be corrected accurately at the same time, and the gate
Corrected gate wiring mask data effective for LSI having
Data can be created.

[0103]

[0104]

[0105]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a mask data verification device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a mask data verification method in the embodiment.

FIG. 3 is a configuration diagram of a mask data creation device according to a second embodiment of the present invention;

FIG. 4 is a flowchart of a mask data creation method in the embodiment.

FIG. 5 is a configuration diagram of a mask data verification device according to a third embodiment of the present invention.

FIG. 6 is a flowchart of a mask data verification method according to the embodiment.

Shows a mask pattern for 7 process described in the same embodiment

Enlarged view of a mask pattern for 8 processing in the embodiment described

FIG. 9 is a configuration diagram of a mask data creation device according to a fourth embodiment of the present invention.

FIG. 10 is a flowchart of a mask data creating method in the embodiment.

FIG. 11 is a view showing a mask pattern for explaining processing in the embodiment.

Enlarged view of a mask pattern for FIG. 12 process described in the same embodiment

FIG. 13 is a configuration diagram of a mask data creation device according to a fifth embodiment of the present invention.

FIG. 14 is a flowchart of a mask data creation method in the embodiment.

FIG. 15 is a view showing a mask pattern for explaining processing in the embodiment.

Enlarged view of a mask pattern for [16] processing in the embodiment described

FIG. 17 is a diagram showing specifications and effects of a waveform edge figure in the embodiment.

FIG. 18 is a configuration diagram of a mask data creation device according to a sixth embodiment of the present invention.

FIG. 19 is a flowchart of a mask data creation method in the embodiment.

FIG. 20 is a diagram showing a mask pattern for describing processing in the embodiment.

Enlarged view of a mask pattern for FIG. 21 process described in the same embodiment

FIG. 22 shows the specifications and the effect of the parallel auxiliary patterns definitive in the Examples

FIG. 23 is a configuration diagram of a mask data creation device according to a seventh embodiment of the present invention.

FIG. 24 is a flowchart of a mask data creating method in the embodiment.

FIG. 25 is a configuration diagram when a waveform edge figure is used in the mask data creation apparatus of the embodiment.

FIG. 26 is a flowchart in the case of using a waveform edge figure in the mask data creation method of the embodiment.

FIG. 27 is a configuration diagram when a parallel auxiliary pattern is used in the mask data creation device of the embodiment.

FIG. 28 is a view showing the operation of the parallel auxiliary pattern of the embodiment.

FIG. 29 is a flowchart in the case where a parallel auxiliary pattern is used in the mask data creation method of the embodiment.

FIG. 30 is a flowchart of a parallel auxiliary pattern creation method according to an eighth embodiment of the present invention;

FIG. 31 is a diagram showing a method for creating a parallel auxiliary pattern according to the embodiment.

FIG. 32 is a flowchart of a conventional mask correction method.

[Explanation of symbols]

1,101,201,301,401,501,601,701,711,721 Design data 2,22 Mask 3,33 Processing pattern 4 Processing pattern measurement data 102,202,302,402,502,602,702,712,722 Mask data input 103,203 Inspection area extraction 303,403,503,603,703,713,723 Line width dimension shift amount calculation unit 705,715,725 Light intensity calculation unit on gate edge 106,206 Development dissolution speed calculation unit 406 Line width correction amount definition unit 706,716,726 Judgment unit 107,207 Inspection unit 507,717 Waveform edge figure creation unit 607,727 Parallel auxiliary pattern creation unit 707 Line width correction amount defining section 108,308 Warning point extracting section 208,408,508,608,708,718,728 Mask data correcting section 109,309 Display section 209,409,509,609,709,719,729 Mask data output section 210,410,510,610,710,720,730 Mask data 311,411,511,611,911 Gate wiring pattern 312,412,512,612,912 12 Active area 313,413,513,613,813 Gate pattern 314,414,514,614 Gate edge 315,415,515,615 Evaluation point 316,416,516,616 Light intensity distribution at evaluation point 317,417,517,617 Threshold for critical resolution 318,418,518,618 Dimension shift amount 319 Warning point extraction part 419 Gate width auxiliary pattern 619 421,521,621 Modified mask data of gate wiring 522 Dimension of waveform edge amplitude Dw 523 Pitch width of waveform edge Pw 524 Dimension of peak portion of waveform edge Ow 525 Line width when Pw of waveform edge is changed 826 Parallel auxiliary pattern Width W 827 Interval S1 between parallel auxiliary pattern and gate

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-83030 (JP, A) JP-A-7-65055 (JP, A) JP-A-7-306523 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G03F 1/00-1/16

Claims (2)

(57) [Claims] A step of inputting mask design data into a mask data input unit; a step of extracting a portion where a gate wiring pattern and an active region overlap with each other as a gate pattern from the input mask design data; Extracting a gate edge from, a step of calculating a light intensity value in the vicinity of the gate edge of the gate pattern, and a step of calculating a dimensional shift amount of a gate line width due to a proximity effect based on the light intensity value, Extracting a gate pattern in which the size shift amount is larger than a predetermined value; and for a gate pattern in which the size shift amount is larger than a predetermined value, a gate line width of the gate pattern based on the size shift amount. And the line width of the gate pattern is corrected based on the specified correction amount of the gate line width.
Correction, a method of creating mask data for creating mask data of a gate wiring pattern. 2. A step of inputting mask design data to a mask data input unit; a step of extracting a portion where a gate wiring pattern and an active region overlap from each other as a gate pattern from the input mask design data; Extracting a gate edge from: calculating a light intensity value on the gate edge; and a gate when the difference between the light intensity value on the gate edge and a predetermined threshold is smaller than a predetermined value. Outputting mask data of the wiring pattern; and correcting the mask data of the gate wiring pattern when the difference between the light intensity on the gate edge and a predetermined threshold value is larger than a predetermined value. The correction of the mask data is performed by changing the line width of the gate pattern until the difference between the light intensity on the gate edge and the threshold becomes smaller than a predetermined value. Modify the line
After that, a method of creating mask data for outputting the mask data of the corrected gate wiring pattern.