JP2004163472A - Method for designing photomask, photomask, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing a photomask by which OPC can be easily carried out and the time required for designing can be decreased while the accuracy of the OPC is maintained, and to provide a photomask produced by the above method and a semiconductor device manufactured by using the photomask. <P>SOLUTION: In a model base OPC, the result of measuring the line width of a test pattern is compared with the calculation result of the model to judge whether or not the fitting residual falls within the tolerance of error (-a, +a). When the residual exceeds the tolerance, the influences of the fitting residual on characteristics such as the connection relation of the pattern with upper and lower layers and the connection are analyzed to determine practically necessary tolerance (-b, +c), wherein each of a, b, c is a constant. If the measurement point shows the fitting difference exceeding the range of (-a, +a) but within the range of (-b, +c), the fitting accuracy is regarded sufficiently high, and inspection of the model is completed. <P>COPYRIGHT: (C)2004,JPO

Description

同様にして、Ｌ６＝４８９５ｎｍ，Ｌ７＝４７４０ｎｍ，Ｌ８＝４４９０ｎｍとなる。
即ち、ポイント５〜８のいずれも、式２を満たしている。そのため、配線パターン２４とコンタクトホール１６の合わせずれは問題が無いことを判明した。
【００８８】
このように、モデル抽出及び検証の際に、配線間スペースのフィッティング残差は許容範囲を超えたとしても、デバイス特性に影響を与えない範囲であれば、許容できる。実際に、上記のように、ＯＰＣを施した後の配線パターンとコンタクトホールの合わせずれを確認すると、配線パターンとコンタクトホールとの接続を十分確保でき、問題は生じないことが分かる。そのため、フィッティング精度が十分に高いと言える。
したがって、全てのテストパターン及び測長ポイントについて、モデルとして十分な精度が得られ、精度の良いモデルである。
その結果、測定された残差を減らすためにパターンの修正とシミュレーションを繰り返すことは必要がない。これによって、モデル抽出及び検証に要する時間を短縮できる。
【００８９】
以上のモデルを用いて、テストパターン１、２、３によって構成される配線層を形成するためのマスクパターンデータを用い、光強度シミュレーションを行ない、配線層における各パターンの形状、寸法、分布を計算する。シミュレーションで得られたパターンと設計パターンとの差より補正量が算出され、ＯＰＣ補正マスクパターンが得られる。
【００９０】
以上に説明した、テストパターンを用いて、配線層を形成するためのＯＰＣ補正マスクパターンを求めるモデルを抽出する処理を図２０のフローチャートでまとめる。なお、図２０において、図１３と同じ内容について説明を適宜に省略する。
図２０は、第２の実施形態において、モデルベースＯＰＣにおけるモデル抽出及び検証における処理の一例を示すフローチャートである。
【００９１】
ステップＳ３１：
第１のテストパターン１、第２のテストパターン２、第３のテストパターン３を形成する。
ステップＳ３２：
各テストパターンにおけるパターン幅や、パターン間のスペース距離を測定する。
ステップＳ３３：
モデルを抽出する為に、モデルに用いられる各種ファイルを作成する。
ステップＳ３４：
抽出されたモデルにより、テストパターンデータを用い、第１、第２、第３のテストパターン３におけるパターン線幅を計算する。
【００９２】
ステップＳ３５：
測定結果とシミュレーション値を比較し、フィッティング残差が誤差許容範囲以内になっているかどうかを判断する。
具体的に、ライン状パターンとライン端パターンに分け、そのそれぞれについて誤差許容範囲を−ａ≦Ｓ≦＋ａとした。ここで、Ｓはフィッティング残差を表わし、ａは定数である。
残差が誤差許容範囲以内になっている場合は、ステップ３９に進み、モデルの検証が終了し、モデルが完成する。
残差が誤差許容範囲以内になっていない場合は、ステップＳ３６に進む。
【００９３】
ステップＳ３６：
残差が（−ａ、＋ａ）範囲を超えたポイントについて、関わるパターンの特性を確認し、残差が負の方向および正の方向を（−ａ、＋ａ）の範囲を超えた場合、デバイスへの影響を分析する。
例えば、配線パターンの場合は、配線パターンの幅が細くなり、または、太くなる場合に、配線パターンと上下層のコンタクトホールとの接続への影響を分析する。
これによって、両者の接続を確保できる上限と下限を見出し、新しい残差許容範囲−ｂ≦Ｓ≦＋ｃを決定する。ここで、ｂとｃは定数である。
【００９４】
ステップＳ３７：
残差が（−ａ、＋ａ）範囲を超えた各ポイントについて、その残差は残差許容範囲−ｂ≦Ｓ≦＋ｃに入っているかどうかを確認する。
ステップＳ３８：
残差が−ｂ≦Ｓ≦＋ｃに入っていれば、ステップ３９に進み、モデルの検証が終了し、モデルが完成する。
残差が−ｂ≦Ｓ≦＋ｃに入っていなければ、ステップＳ３３に戻し、シミュレーションを実施する際の各種設定項目を修正し、再びシミュレーションを行なう。残差が−ｂ≦Ｓ≦＋ｃに入るまで、ステップＳ３３〜ステップＳ３８を繰り返す。
【００９５】
このように、モデル抽出及び検証が完成する。
以上のモデルを用いて、半導体基板上に目標のパターンのシミュレーションを行ない、マスクパターン各辺の補正量を求めることから、ＯＰＣ補正マスクパターンが得られる。
【００９６】
以上の本実施の形態によれば、フィッティング残差が規定された許容範囲を超えた場合であっても、フィッティング精度を不十分とせず、実際にＯＰＣを施した時に、残差の超過がパターンのデバイスにおける特性、例えば配線層とコンタクトホールの接続状態にどのような影響を与えるかを判断し、フィッティング残差の許容範囲を再評価する。これによって、超過した残差を減らすためにモデルの修正などの処理を繰り返すことは必要がなく、合理なモデル評価が容易に達成でき、モデル抽出及び検証に要する時間を短縮できる。
【００９７】
第３の実施形態
本実施形態において、第１と第２の実施形態で説明した手法でテストパターンを用いてモデル抽出及び検証を行ない、モデルベースＯＰＣでＯＰＣ補正マスクパターンを得る。そして、このＯＰＣ補正マスクパターンを用い、半導体装置を製造する例を述べる。
本実施形態において、まずは、モデル抽出と検証を行なう。モデル抽出と検証の方法は、第１と第２の実施形態で説明した方法と同様である。
即ち、形成するパターンの半導体装置における特性、及びパターン線幅の変動が半導体装置特性に与える影響から、フィッティング残差の許容範囲を評価し、短い時間で容易に合理なモデル評価を達成する。
例えば、配線パターン及び配線間スペースの場合は、配線パターンと上下の層のコンタクトホールとの接続関係から、配線パターン及び配線間スペースの誤差の許容範囲を決める。
このように得られたモデルによって、ＯＰＣ補正マスクパターンを作成し、半導体装置を製造する。
【００９８】
図２１は、図１７に示された半導体装置を製造するプロセスを示す部分断面図である。
図２１（ａ）は、例えば、開口パターン３２が形成されたフォトマスク３１と、露光装置における光学系３３を示す。
フォトマスク３１には、以上のように得られたモデルを用いて、モデルベースＯＰＣによって、ＯＰＣを施したフォトマスクである。
図示しない光源からのレーザ光４０は、フォトマスク３１を通過して、光学系３３を経由して下方の半導体基板へ照射する。
【００９９】
図２１（ｂ）は、例えば、酸化膜からなる絶縁層１１を示す。図示しないが、絶縁層１１上にフォトレジスト膜を塗布し、図２１（ａ）の露光装置からの光はフォトレジスト膜を照射し、露光を行ない、フォトマスク３１上の開口パターン３２を絶縁層１１に成形し、コンタクトホール１２を形成する。その後フォトレジストを除去する。
コンタクトホール１２に、例えば、Ｗなどの金属を堆積する。
次に、図２１（ｃ）に示すように、絶縁層１１上に、例えば酸化膜からなる第２の絶縁層１３を形成し、第２の絶縁層１３に配線層を形成するための開口部１４ｂを露光によって形成する。なお、この時、用いるフォトマスクが図２１（ｂ）の工程で用いたものと異なるが、便宜上、フォトマスク３１と記す。
【０１００】
次に、図２１（ｄ）に示すように、開口部１４ｂに、例えば、Ｗなどの金属を堆積し、配線層１４を形成する。
そして、第２の絶縁層１３と配線層１４を覆って第３の絶縁層１５を形成する。そして、図２１（ｂ）と同じように露光を行ない、フォトマスク３１上の開口パターン３２を絶縁層１５に転写し、コンタクトホール１６を形成する。
図２１（ｃ）と同じように、この時に用いるフォトマスクが図２１（ｂ）と（ｃ）の工程で用いたものと異なるが、便宜上、フォトマスク３１と記す。
【０１０１】
ＯＰＣ補正フォトマスクであるフォトマスク３１のマスク補正量は、形成するパターンの半導体装置における特性及びパターン線幅の変動が半導体装置特性に与える影響から、フィッティング残差の許容範囲を評価して求められた。例えば、配線パターンの場合は、配線パターンと上下の層のコンタクトホールとの接続関係から、配線パターン及び配線間スペースの誤差の許容範囲を決めた。そのため、配線パターン１４と上下の層のコンタクトホール１２，１６との接続を十分確保されている。
【０１０２】
本実施形態によれば、モデルベースＯＰＣにより、マスク補正量を求める時間を短縮でき、形成された配線パターンと上下の層のコンタクトホールとの接続を確保できる。
【０１０３】
以上、本発明を好ましい実施の形態に基づき説明したが、本発明は以上に説明した実施の形態に限られるものではなく、本発明の要旨を逸脱しない範囲で、種々の改変が可能である。
例えば、上記の実施形態でパターンと他の層との接続関係から、残差の許容範囲を評価するとしたが、他のデバイス特性でもよい。
また、上記の実施形態でフィッティング残差が負となる例を挙げたが、残差が正となっても、同様にデバイス特性を分析し、残差の許容範囲を評価することができる。
【０１０４】
【発明の効果】
以上説明した本発明のフォトマスクの設計方法、フォトマスク、及び半導体装置によれば、シミュレーション誤差の許容範囲は、パターンのデバイスにおける特性、及びこのパターンの誤差がデバイス特性に与える影響から決めることから、各パターンが実際に要求するシミュレーション精度を満たせば良いので、単にシミュレーション誤差を減らすためにモデルに対する修正などの不自然な操作を必要以上に行なう必要がなくなり、十分な精度を確保しながら、合理なモデル評価が容易に達成でき、モデル抽出及び検証に要する時間を短縮できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態において、モデルベースＯＰＣに関する処理の概略を示すフローチャートである。
【図２】本発明の第１の実施形態において、モデルベースＯＰＣにおけるモデルフィッティング処理を概略的に示す図である。
【図３】本発明の第１の実施形態において、モデルベースＯＰＣを用いて、実回路に対してシミュレーションを行なう処理を概略的に示す図である。
【図４】本発明の第１の実施形態において、モデルベースＯＰＣを施した、実回路のレイアウトデータを転写・加工後の形状を概略的に示す図である。
【図５】本発明の第１の実施形態において、モデルベースＯＰＣにおけるモデル抽出と検証に関する処理の概略を示すフローチャートである。
【図６】本発明の第１の実施形態において用いられたテストパターンの第１の例を示している。
【図７】本発明の第１の実施形態において用いられたテストパターンの第２の例を示している。
【図８】本発明の第１の実施形態において用いられたテストパターンの第３の例を示している。
【図９】本発明の実施形態において用いられるフィッティング残差の定義を説明する図である。
【図１０】図９に続いて、本発明の実施形態において用いられるフィッティング残差の定義を説明する図である。
【図１１】本発明の第１の実施形態において、テストパターンを用いて測定した線幅とシミュレーションの結果を比較する図である。
【図１２】本発明の第１の実施形態において、テストパターンにおける線幅のシミュレーション結果と測定結果との残差を示す図である。
【図１３】本発明の第１の実施形態において、モデルベースＯＰＣにおけるモデル抽出及び検証において処理の一具体例を示すフローチャートである。
【図１４】本発明の第２の実施形態において、テストパターンを用いて測定した線幅とシミュレーションの結果を比較する図である。
【図１５】本発明の第２の実施形態において、テストパターンにおける線幅のシミュレーション結果と測定結果との残差を示す図である。
【図１６】本発明の第２の実施形態において、配線層のシミュレーションでは、配線パターンの線幅の変動とコンタクトの関係及び影響を示す図である。
【図１７】本発明の第２の実施形態にかかる半導体装置の部分断面図である。
【図１８】本発明の第２の実施形態において、配線層のシミュレーションでは、配線間スペースの変動がコンタクトの関係及び影響を示す図である。
【図１９】本発明の第２の実施形態において、配線パターンとコンタクトホールの合わせずれを示す図である。
【図２０】本発明の第２の実施形態において、モデルベースＯＰＣにおけるモデル抽出及び検証において処理の一具体例を示すフローチャートである。
【図２１】本発明の第３の実施形態にかかる半導体装置を製造するプロセスを示す部分断面図である。
【符号の説明】
１、２，３…テストパターン、１ａ…パターン、１ｂ…測定箇所、１ｃ…実パターン、１ｄ…シミュレーションパターン、２ａ…開口部、２ｂ…パターン、２ｃ…測定箇所、３ａ、３ｂ…パターン、３ｃ…測定箇所、３ｄ…パターン線幅、４…設計配線パターン、５…シミュレーションパターン、６…ＯＰＣ補正マスク、１１…絶縁層、１２、１２ａ、１２ｂ…コンタクトホール、１３…絶縁層、１４…配線層、１５…絶縁層、１６、１６ａ、１６ｂ…コンタクトホール、２１ａ、２１ｂ…設計配線パターン、２１ｃ…設計配線間スペース、２２ａ、２２ｂ…シミュレーション配線パターン、２２ｃ…シミュレーション配線間スペース、２３…ＯＰＣ補正マスク、２３ａ、２３ｂ…補正後配線パターン、２３ｃ…補正後配線間スペース、２４ａ、２４ｂ…形成された配線パターン、２４ｃ…形成された配線間スペース、３１…フォトマスク、３２…開口パターン、３３…光学系、１０１…テストパターン・レイアウトデータ、１０２…テストパターン・フォトマスク、１０３…ウェハ、１０４…テストパターン、１０５…プロセスモデル、１０６…実回路のレイアウトデータ、１０７…シミュレーション・パターン、１０８…ＯＰＣ補正パターン、１０９…目標パターン。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for designing a photomask used for manufacturing a semiconductor device and the like, a photomask formed using the method, and a semiconductor device manufactured using the photomask.
[0002]
[Prior art]
With miniaturization of electronic devices and high integration of integrated circuits, the dimensions of semiconductor design patterns have become shorter than the exposure wavelength. For example, the gate length of a gate electrode of a MOS transistor is a so-called deep submicron fine width, and further reduction in the width and pitch of a contact hole and via hole pattern is required in an electronic device.
[0003]
In order to improve the degree of integration and to be able to process large-capacity data at high speed, in a semiconductor device, for example, a memory element such as a DRAM and a logic element are simultaneously formed on the same chip. In recent years, consolidation has been performed. In such a semiconductor device, it is necessary to form a dense pattern and a sparse pattern on the same chip. Specifically, while the patterns of the memory elements are densely and regularly arranged, the patterns of the logic elements are relatively sparsely arranged at random.
[0004]
When the pattern of a semiconductor device is miniaturized and complicated, the processing accuracy of a circuit pattern is reduced. For example, when a gate pattern is formed on a photomask at the same design interval and design width, and is transferred to a wafer by exposure and etching using the photomask, the size and interval of the gate pattern formed on the wafer are different. Become. As a result, the characteristics of the semiconductor device fluctuate, and the performance and yield as an integrated circuit decrease.
[0005]
Factors that lower the processing accuracy include, for example, line width fluctuations due to process instability, line width fluctuations on the photomask, and line width fluctuations on the photomask and the semiconductor substrate due to the dependence on pattern density. And the like. These are caused by manufacturing techniques mainly used in the semiconductor device manufacturing process, for example, photolithography and etching.
[0006]
The photolithography technique is a technique mainly used for forming a pattern for a semiconductor element on a semiconductor substrate in a manufacturing process of a semiconductor device. In photolithography, a photomask (an exposure original plate on which a pattern composed of a transparent area and a light-shielding area is formed by a reduction projection exposure apparatus. When the reduction ratio is not 1: 1, it is particularly called a reticle. The pattern (referred to as a mask), that is, the mask pattern is transferred onto the semiconductor substrate coated with the photosensitive resin, and a predetermined pattern of the photosensitive resin, that is, a photosensitive resin pattern can be obtained by development.
[0007]
In the conventional photolithography technology, the resolution has been improved mainly by the development of an exposure apparatus, in particular, by shortening the wavelength and increasing the NA of the projection lens system, and has responded to the miniaturization of semiconductor elements. Here, NA is called the numerical aperture, and the higher the value, the higher the resolution.
As is generally well known as Rayleigh's equation, assuming that the wavelength of light in photolithography is λ, the critical resolution R (dimension of the fine pattern at the limit of resolution) and NA of the exposure apparatus are: There is a relationship of R = k1.lambda. / NA, and the larger the NA, the finer the limit resolution. Here, the coefficient k1 is a constant depending on the performance of the resist and the like.
[0008]
However, when a pattern is formed on a semiconductor substrate, a surface to be exposed often has a step. In order to form a fine pattern on such a stepped surface, it is important to ensure not only the resolution but also the depth of focus.
The depth of focus DOF (Depth of Focus) is a range of allowable shift of the focal position, and k₂・ Λ / (NA)²Is determined. Coefficient k₁As in₂Is a constant depending on the characteristics of the resist and the like.
As can be seen from the definitions of the resolution R and the depth of focus DOF, the resolution is improved by shortening the wavelength and increasing the NA, but at the same time, the depth of focus DOF sharply decreases in proportion to the square of (NA). That is, as the NA is increased, the depth of focus becomes narrower, and a slight shift of the focal position cannot be tolerated. Therefore, further miniaturization is difficult in terms of the depth of focus.
[0009]
Therefore, various super-resolution techniques have been studied to secure both resolution and depth of focus in response to pattern miniaturization. In general, the super-resolution technique is a technique for improving the light intensity distribution on the image plane by controlling the transmittance and the phase on the pupil plane of the illumination optical system, the photomask, and the projection lens system.
Among various super-resolution methods, improvement in resolution characteristics by optimizing an illumination optical system, that is, a so-called deformed illumination method has high feasibility and has attracted particular attention in recent years.
Generally, an illumination optical system of an exposure apparatus illuminates a photomask with a circular light source (effective light source). A method of controlling the shape of the effective light source to improve the resolution characteristics is a super-resolution method generally called a modified illumination method, an oblique incidence illumination method, or a two-beam illumination method. In the modified illumination, since the incident angle of light for illuminating the photomask is limited, a depth of focus for a fine pattern can be ensured.
[0010]
In photolithography, with respect to light to be vertically irradiated on a photomask, diffracted light of 0th order, ± 1st order, ± 2nd order, etc., due to a fine pattern on the photomask surface irradiates a pupil of a projection optical system for lithography. In general, if the second-order and subsequent diffracted lights are set to be cut by the pupil, an image is formed on the wafer by interference of the 0th-order and ± 1st-order diffracted lights, which is so-called three-beam interference.
In the case of light that illuminates the photomask obliquely, either the + 1st order or the -1st order is cut by the pupil and an image is formed by two-beam interference, which is so-called two-beam interference. Since the resolution of the two-beam interference is higher than that of the three-beam interference and the convergence angle of the wavefront on the wafer surface is small, the obtained depth of focus DOF is large.
[0011]
As means for changing the shape of the effective light source and using the modified illumination method, usually, apertures or filters of various shapes are arranged immediately after the fly-eye lens. Note that this method is distinguished by the shape of the effective light source (the shape of the stop). For example, an illumination method using a ring-shaped illumination light source while shielding the center of the stop from light is called an annular illumination method.
An illumination method using an aperture having openings only at four peripheral corners is called a quadrupole illumination method.
When the central portion of the light source is shielded, the angle of incidence on the photomask is limited, so that the image component due to three-beam interference is reduced and the two-beam interference component due to off-axis illumination is increased. Thereby, the resolution is improved while securing the depth of focus for the fine pattern.
[0012]
In addition to the modified illumination method, a phase shift mask, which is a super-resolution method by improving the photomask side, has been actively studied. In particular, the halftone phase shift mask has attracted particular attention because it has an advantage that the manufacturing method is easier than other phase shift masks and the design of mask data is easier.
Here, the halftone method generally uses a translucent film instead of a light-shielding film of a mask so that a phase difference of 180 degrees occurs between light transmitted through the translucent film and light transmitted through a transparent region around the translucent film. This is a set phase shift mask. As a material of the translucent film, chromium oxynitride, molybdenum oxynitride silicide, chromium fluoride, or the like is used, and its transmittance is generally in the range of 4% to 10%.
[0013]
In the halftone type phase shift mask, the light intensity decreases at the boundary between the transparent region and the translucent region due to interference between lights having phases different by 180 degrees, and the light intensity distribution becomes steeper. That is, the resolution of photolithography is improved. However, since the light intensity is reduced due to the interference (in the vicinity of the boundary between the transparent region and the translucent region), in order to obtain the desired size of the photosensitive resin pattern, correction (mask bias) for increasing the size of the transparent region is required. Will be needed.
[0014]
In addition to these super-resolution techniques, in the formation of a pattern near the resolution limit, the influence of an optical proximity effect (Optical Proximity Effect) becomes significant, and the mask pattern of a photomask cannot be accurately transferred to a wafer.
Specifically, in photolithography, when a layout pattern miniaturized to near the limit resolution of an exposure apparatus is exposed and transferred to a photoresist film or the like, adjacent light beams passing through the fine pattern on the photomask cause optical interference. However, the exposure image is distorted, the mask pattern of the photomask cannot be transferred accurately, and the shape and dimensions of the pattern on the wafer change. Further, the optical proximity effect is affected by the arrangement of peripheral patterns, and appears more prominently as the patterns are denser.
[0015]
The phenomena observed by the optical proximity effect include cornering of a right-angle pattern (cornerrounding), line-shortening of a line pattern (line shortening), pattern thinning, pattern thickening, and pattern coarse / dense dependency.
[0016]
In order to suppress the influence of the optical proximity effect, a so-called optical proximity effect correction (hereinafter, referred to as OPC) technique of performing correction for compensating the optical proximity effect on a photomask in advance is actively studied. It is becoming. This method is a method in which design data is corrected in advance in consideration of the optical proximity effect (referred to as an OPC pattern) and layout data is deformed to obtain a desired photosensitive resin pattern.
Such an OPC method includes a method of simply changing the size of a mask pattern (referred to as a mask bias; a method of changing the size of a part of the pattern is particularly referred to as a jog), and a method of resolving at a corner of the pattern. There are methods such as hat and self for arranging a fine pattern below the limit.
[0017]
OPC is generally classified into a rule-based OPC and a model-based OPC according to a method of determining a correction bias amount (hereinafter, referred to as a correction amount).
In the rule-based OPC, the correction amount for each edge of the mask pattern is determined for each pattern exposure step from the mask pattern attributes such as the size and shape of the mask pattern, the proximity to the adjacent mask pattern, and other process conditions. I do.
In the rule-based OPC, a pattern is formed on a wafer using a photomask for preparing a correction rule prepared in advance, the line width of the formed pattern is measured, and a correction table is prepared based on the measurement result. Next, a new design photomask is manufactured by correcting the layout pattern data using the correction table.
[0018]
In contrast, in the model-based OPC, a function for calculating a correction amount is extracted using an arithmetic device.
First, a pattern is formed on a wafer using a “test pattern” prepared in advance, and the line width and the like of the formed pattern are measured. The measurement result is input to an arithmetic unit, and the semiconductor device (semiconductor device) To create a mathematical model that simulates the manufacturing process, ie, to extract the model. In an actual semiconductor device circuit, various shapes and sizes of patterns exist. In a model-based OPC, a collection of simplified patterns that can represent any layout pattern permitted in design is used. Used as a test pattern.
Next, using the extracted model, the arithmetic unit simulates a pattern formed on the wafer using layout data corresponding to the target pattern, and extracts deformation and dimensional variation of the simulated pattern. Based on the result, the correction amount of each side of the correction mask pattern that can form the target pattern is determined for the layout data.
[0019]
2. Description of the Related Art Simulation of a manufacturing process of a semiconductor device (semiconductor device), that is, a process simulation, calculates each process in a semiconductor device manufacturing process such as a photolithography process, an ion implantation process, and a diffusion process without actually manufacturing the semiconductor device. Simulation is performed using an apparatus to predict the shape of each part, the concentration distribution of impurities, and the like. As a result of the process simulation (hereinafter, simulation) in the present invention, the dimensions after the pattern is formed and the necessary correction amount are calculated by a mathematical model called a process model. That is, the ideal correction and confirmation of the photomask can be executed in advance by the simulation.
[0020]
In the rule-based OPC, the calculation processing time of the OPC is fast, and the data amount of the pattern data does not increase so much. However, the accuracy of the pattern formed on the wafer may not be ensured in some cases. Further, it is necessary to finely define items such as the attribute of the mask pattern and the positional relationship with the peripheral mask pattern, which is complicated.
In the model-based OPC, each side of the mask pattern is subdivided to perform pattern edge division, simulation is performed, a correction amount is determined based on the result, and a corrected OPC pattern is generated. It is possible to reproduce the shape of the mask pattern on the photomask with high accuracy without specifying the positional relationship with the mask pattern.
[0021]
However, mask pattern data is very complicated and enormous in the actual manufacture of semiconductor devices, and usually consists of hundreds of thousands to millions of figures. In order to optimize the fine processing accuracy for such a pattern having an enormous amount of data, it is time-consuming and costly to perform simulations on all mask patterns and on the entire mask pattern and to perform OPC. It is naturally impossible from the point of view, and as described above, a general-purpose model is extracted within a certain range using a test pattern, and a pattern to be formed is simulated using the general-purpose model to obtain an OPC correction mask.
[0022]
For example, in the method disclosed in Patent Document 1, a simulation is performed on specific pattern data, and a pattern distribution formed when exposure is performed using the specific pattern data is simulated, and these are compared. By doing so, the pattern data is corrected such that these differences are equal to or smaller than the allowable value.
[0023]
[Patent Document 1]
JP-A-11-184064
[0024]
[Problems to be solved by the invention]
However, since high integration and high-speed operation of semiconductor devices are required, pattern line widths are becoming finer, and circuits are also complicated, such as simultaneously creating a memory portion and a logic portion having different pattern densities. . Therefore, there are many mask pattern shapes required to establish a model for performing OPC, the processing is complicated, and the situation where enormous time is required for performing OPC has not been improved.
[0025]
The present invention has been made in view of the above circumstances, and a purpose of the present invention is to provide a photomask designing method capable of easily performing OPC while reducing the time required for OPC while maintaining the accuracy of OPC, and a photomask produced using the method. A mask and a semiconductor device manufactured using the photomask.
[0026]
[Means for Solving the Problems]
A photomask designing method according to the present invention includes a step of forming a plurality of test patterns that can form a target pattern to be formed, measuring a size of the test pattern, and a measurement result of the test pattern dimension. Extracting a model for calculating a dimension, and adjusting parameters in the model until a difference between a calculation result of the test pattern dimension by the model and a measurement result of the test pattern dimension is within a predetermined error range. And correcting the photomask for forming the target pattern using the adjusted model. The error range is determined based on characteristics of the target pattern in the semiconductor device.
Preferably, the error range is from a predetermined minimum value to a maximum value, and the minimum value and the maximum value are independently determined according to characteristics of the target pattern in the semiconductor device.
[0027]
Preferably, the target pattern includes a linear pattern serving as a wiring pattern in a semiconductor device, and sets a minimum value and a maximum value of the error range according to a connection state between the wiring pattern and a contact hole connected to the wiring pattern. Decide.
Alternatively, the target pattern includes a groove-shaped line pattern serving as a groove between wiring patterns in a semiconductor device, and sets the minimum value and the maximum value of the error range to the wiring pattern and the wiring pattern on both sides of the groove-shaped line pattern. Determined according to the connection state with the contact hole to be connected.
[0028]
Preferably, optical proximity effect correction (OPC) for a photomask for forming a target pattern is determined by the model.
[0029]
A photomask according to the present invention is a photomask that has been corrected to form a target pattern, and the amount of correction is based on a measurement result of dimensions of a plurality of test patterns formed in advance and the test pattern based on a model. Are calculated so as to fall within an error range determined by the characteristics of the target pattern in the semiconductor device.
The error range is from a predetermined minimum value to a maximum value, and the minimum value and the maximum value are independently determined by characteristics of the target pattern in the semiconductor device.
[0030]
A semiconductor device according to the present invention is a semiconductor device including a target pattern formed using a corrected photomask, wherein the amount of correction is based on a measurement result of dimensions of a plurality of test patterns formed in advance. The difference between the calculation results of the dimensions of the test pattern by the model is determined to be within the error range determined by the characteristics of the target pattern in the semiconductor device.
Preferably, the error range is from a predetermined minimum value to a maximum value, and the minimum value and the maximum value are independently determined by characteristics of the target pattern in the semiconductor device.
[0031]
According to the present invention described above, when a test pattern is formed, its dimensions are measured, a process model is extracted using the measurement results, and correction for a photomask is determined, the dimensions of the test pattern obtained by calculation are calculated. And the size of the measured test pattern are determined in consideration of the influence of the error of the related target pattern on the characteristics of the semiconductor device. If the allowable range of the error in the model calculation of the pattern is rationally determined from the characteristics of the target pattern in the semiconductor device, a reasonable model extraction can be easily achieved, and the time required for designing the photomask pattern is reduced.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the following embodiments, an OPC correction photomask for performing OPC will be described as an example.
First embodiment
In order to perform optical proximity correction (OPC), the amount of correction for each side of the photomask is determined. In the present embodiment, it is a so-called model-based OPC in which the correction amount is obtained by a model.
[0033]
FIG. 1 is a flowchart illustrating an outline of processing in the model-based OPC according to the present embodiment.
Step S1:
A model for performing a simulation of a semiconductor device manufacturing process is extracted and verified.
The extraction and verification of the model are performed based on the measurement results of the line width of the test pattern actually formed on the semiconductor substrate. Various parameter data used in the model is corrected so that the difference between the measurement result of the pattern line width of the test pattern and the simulation result by the extracted model is within a specified error range.
This establishes a model used for simulation. This process is called model fitting.
[0034]
FIG. 2 is a diagram conceptually showing the process of extracting the process model.
FIG. 2 shows, as an example, a method of extracting a process model after transfer and processing.
First, a photomask 102 (hereinafter, referred to as a test mask) of a test pattern is prepared using layout data 101 which is a design value of the test pattern 104. As the test pattern, a pattern representing all layout patterns permitted in design is used.
Subsequently, for example, a photosensitive resin is applied on the wafer 103, and the test mask 102 is transferred to the photosensitive resin to form a photosensitive resin pattern. Next, using the photosensitive resin pattern as a mask, an etching process is performed on the wafer 103 to form a test pattern 104.
[0035]
Then, the pattern width of the test pattern 104 and the space distance between the patterns are actually measured. After that, a process model 105 that derives this measurement result from the design value 101 of the test mask is extracted.
The process model 105 calculates and obtains the measurement result, the design value 101 of the test mask, and the exposure condition. This ends the model extraction.
By applying the design values of the semiconductor device to the process model 105 obtained in this way, it is possible to simulate the line width of the layout pattern to be formed. The optical proximity correction of the photomask can be executed based on the simulation result.
[0036]
Step S2:
When a circuit pattern (referred to as a target pattern) in an actual semiconductor device is formed on a wafer using the process model 105, the shape of the formed pattern is simulated and predicted.
FIG. 3 is a diagram conceptually showing this simulation processing.
As shown in FIG. 3, a simulation is performed by inputting layout data 106 of a target pattern into a process model 105, and a pattern such as a simulation pattern 107 is predicted to be formed on a wafer.
In this simulation, the measurement results of the dimensions of the test pattern 104 and the optical conditions in lithography are input to the model 105 as input data together with the layout data 106, and the simulation pattern 107 is output.
In the simulation, each side of the pattern serving as the simulation target area is subdivided according to the accuracy and the amount of calculation.
[0037]
Step S3:
Comparing the shapes of the simulation pattern 107 and the photomask generated from the layout data 106, and calculating the OPC correction to be performed on the photomask generated from the layout data 106 when forming a target pattern on the wafer 103; From the result, the correction amount of each side of the mask pattern is determined, and an OPC correction mask for forming a target pattern is obtained. Then, OPC correction is performed using the OPC correction mask to form a target pattern in an actual circuit on the wafer.
FIG. 4 illustrates this OPC process. FIG. 4 shows an OPC correction mask 108 on which OPC has been performed. When the correction mask 108 is transferred onto the wafer 103, a target pattern 109 is obtained.
[0038]
FIG. 5 is a flowchart showing the model extraction processing (model fitting) in the model-based OPC in detail.
Step S11:
First, a test pattern for extracting a model is formed.
As described above, for example, after forming a layer of a material to be etched to be a gate layer on a wafer with a thin film, a photosensitive resin is further applied, and the above-described test mask is transferred to the photosensitive resin. Form a pattern. Next, an etching process is performed using the photosensitive resin pattern as a mask to form a gate layer having a test pattern shape.
[0039]
Step S12:
The pattern width of each formed test pattern and the space distance between the patterns are actually measured using a scanning electron microscope (SEM) or the like, and the measurement results are obtained.
At this time, if there is a possibility that the actual size may be different due to the process processing after the etching or the like, the measurement result may be further processed. As an example of the process processing, CMP (Chemical Mechanical Polishing: chemical mechanical polishing) and the like can be mentioned.
[0040]
Step S13:
A file necessary for extracting a model for simulating a semiconductor device manufacturing process is created.
In the present invention, a commercially available model creation tool is used. At that time, the following information is required. In addition to the test pattern layout data (GDSII format), coordinates, weighting, and length measurement results, a file is created that describes various setting items for designating the exposure and optical conditions for the lens and mask, the calculation method during simulation, and the like.
[0041]
Step S14:
By inputting the above-mentioned file into the model creation tool, a formula for calculating a pattern dimension prediction after formation when a manufacturing process is used is created from the relationship between the input test pattern and the measurement result of the test pattern (model Extraction or model fitting).
Based on the created model, using the layout data of the test pattern, when the test pattern is formed on the wafer in the above manufacturing process, the shape and line width of the formed pattern are predicted, and the photoresist after exposure and development Calculate what the shape of will be.
[0042]
Step S15:
The measurement result is compared with the simulation result, and the difference between the measurement result, the simulation result, and the measurement result (hereinafter, referred to as a simulation residual, a fitting residual, or simply a residual. The fitting residual is mainly used hereinafter) is defined. Judge whether it is within the error range.
If the fitting residual is within the error range, the process proceeds to step S16, where the study on the accuracy of the model ends, and the model is established.
If the fitting residual is larger than the error range, the process returns to step S13, where various setting items for performing the simulation are corrected, and the test pattern is simulated again. Steps S13, S14, and S15 are repeated until the fitting residual falls within the error range.
Step S16:
In this way, the accuracy of the model used for the simulation is examined and the model is established.
[0043]
There are various layouts for circuit patterns in an actual semiconductor device, but when extracting a model for simulation, a simplified specific pattern that can represent any layout pattern actually formed is used. That is, model extraction is performed based on the test pattern measurement results described here.
[0044]
As described above, in the model-based OPC, a test pattern is formed in accordance with a process of manufacturing an actual semiconductor device, a process model for simulation is extracted based on a measurement result of the test pattern, and mask correction is performed using the model. Find the quantity. Therefore, when extracting a model, it is important how to accurately match the experimental result of the test pattern with the simulation result of the model.
As an index for evaluating the fitting residual, the error between the simulation result and the measurement result is used as described above.
[0045]
Next, a specific example of model extraction and examination of accuracy using a test pattern will be described. For example, consider the case where an OPC correction mask pattern is obtained when a gate layer is formed in a transistor or the like.
The gate layer of the transistor includes various gate dimensions, densities, and shapes, and a pattern as shown in FIGS. 6 to 8 is used as a part of a test pattern that can represent these patterns of the gate layer. A model for performing a simulation is extracted from the dimensions of these test patterns and the measurement results.
[0046]
FIG. 6 shows layout data (design values) of the first test pattern used in the present embodiment.
The first test pattern 1 shown in FIG. 6 is a basic line-space pattern (L / S pattern) for forming a gate layer, and the line width or space is varied according to a design rule. And five bar-like patterns (shaded portions) as shown in FIG. The bar-shaped pattern is formed after processing, and serves as a space therebetween.
For example, the line width of each bar pattern is fixed to 150 nm, and four patterns in which the space distance between each bar pattern is 150 nm, 200 nm, 500 nm, and 1000 nm are considered.
In FIG. 6, for example, the line width of the bar-shaped pattern 1a in the first test pattern 1 is measured at the indicated measurement point (hereinafter, referred to as a length measurement point or simply a point) 1b.
[0047]
FIG. 7 shows layout data (design values) of the second test pattern used in the present embodiment.
After the formation of the second test pattern 2 shown in FIG. 7, one opening 2a is formed in the layered pattern 2b (hatched portion). The shaded portion 2b is formed after processing to form a pattern, and the opening 2a is a space between the patterns. For example, consider four patterns in which the line width of the opening 2a, that is, the space line width is 150 nm, 200 nm, 500 nm, and 1000 nm. In FIG. 7, the line width of the space in the second test pattern 2 is measured at the indicated measurement point 2c.
[0048]
FIG. 8 shows layout data (design values) of the third test pattern used in the present embodiment.
The third test pattern 3 shown in FIG. 8 is a line end correction pattern in which the ends of the line patterns 3a and 3b are abutted. The model created using the third test pattern 3 has, for example, four types of distances 3c between the ends of the line patterns 3a and 3b of 150 nm, 200 nm, 500 nm, and 1000 nm, and a fixed line width 3d of 150 nm. .
[0049]
According to the semiconductor device manufacturing process, a layer of a material to be etched to be a gate layer is formed on a wafer having a thin film, and then a photosensitive resin is applied, and the above-described test patterns 1, 2, and 3 are transferred to the photosensitive resin. To form a photosensitive resin pattern. Next, an etching process is performed using the photosensitive resin pattern as a mask to form a gate layer having a test pattern shape.
In each of the formed test patterns, the gate pattern, the space, and the space at the pattern end are measured at four measurement points.
Here, it is actually difficult to manufacture a photomask according to the layout pattern, but for convenience, the pattern dimensions of the test patterns 1, 2, and 3 on the photomask are assumed to be the same as the layout data. That is, the test patterns 1, 2, and 3 are formed as designed.
[0050]
The simulation is performed using a commercially available photolithography simulation tool. First, model creation will be described.
By inputting layout data of a test pattern, measurement results, process conditions (exposure apparatus conditions, etc.), setting conditions at the time of simulation, and the like to the simulation tool, it is expressed by a mathematical expression for calculating a pattern size after processing. Output model.
The process condition is a condition used when a mask pattern is actually transferred onto a semiconductor substrate by exposure, for example, an illumination condition (light source wavelength λ, numerical aperture NA, coherence factor σ, annular shielding ratio or annular ratio ε, And the setting conditions at the time of the simulation include a grid required for data display.
[0051]
Next, the measurement result of the test pattern and the calculation result are compared to determine a model. An error between the measurement result and the simulation result is also called a fitting residual, fitting accuracy, or model accuracy, but is hereinafter referred to as a fitting residual and used as an index. If the fitting residual is small, the processed shape of the layout pattern can be accurately calculated.
First, the allowable value of the fitting residual is determined based on the minimum rule of the pattern. For example, the residual when the gate length is 150 nm is ± 5 nm for the line pattern and ± 20 nm for the line end pattern.
[0052]
The first test pattern 1 shown in FIG. 6 is classified as a line pattern, and the third test pattern 3 shown in FIG. 8 is classified as a line end pattern. The second test pattern 2 shown in FIG. 7 has a linear opening 2a, and is not a linear pattern like the first test pattern 1, but is regarded as an inverted linear pattern for measuring a space. , And a line pattern.
Therefore, for the first test pattern 1 and the second test pattern 2, the allowable value of the fitting residual is ± 5 nm, and for the third test pattern 3, the allowable value of the fitting residual is ± 20 nm.
[0053]
Next, the fitting residual is checked.
First, the definition of the amount used for evaluating the fitting residual will be described with reference to FIGS.
FIG. 9 shows the layout data (design value) of the first test pattern 1 consisting of the five bar patterns shown in FIG. 6, and the center 1b of the bar pattern 1a is a measurement point for measuring the line width. It is. Further, a pattern actually formed based on the layout data of the first test pattern 1 shown is simulated by 1c, and a simulation is performed by the layout data of the first test pattern 1, and the obtained simulation pattern is shown by 1d. Have been.
[0054]
FIG. 10 is an enlarged view of a portion of the length measurement point 1b.
FIG. 10A shows the line width R of the simulation pattern 1d, the measured value S of the line width of the actually formed pattern 1c, and the designed value T of the line width of the bar-shaped pattern 1a.
FIG. 10B is a diagram in which a part of FIG. 10A is further enlarged, and EPE1 which is half of the difference between the simulation value R and the design value T, and half of the difference between the measurement value S and the design value T are shown in FIG. EPE2, and the difference EPE between EPE1 and EPE2. EPE is defined as the fitting residual.
The fitting residual is confirmed using such a definition.
[0055]
FIG. 11 is a diagram comparing a measurement result of a line width in a test pattern with a simulation result.
In FIG. 11, the vertical axis shows half EPE2 of the difference between the measurement result and the design value and the half EPE1 of the difference between the simulation result and the design value, and the horizontal axis shows the length measurement point. The black square symbols represent simulation results. As described above, the difference between EPE1 and EPE2 is the fitting residual.
The measurement points 1 to 4 are measurement points of four patterns having different design line widths in the first test pattern 1, and the measurement points 5 to 8 have the design space width in the second test pattern 2. The measurement points of four different patterns are measured points, and the measurement points 9 to 12 are the measurement points of the four test patterns 3 in the third test pattern 3 having different design line ends.
[0056]
As shown in FIG. 11, in many cases, the fitting residuals are not zero, ie, the simulation cannot accurately reproduce the measurement results. In addition, the difference between the simulation result and the measurement result varies depending on the target pattern (dimensions of the dimensions and area).
However, if the fitting residual is smaller than the specified value, the processed pattern shape can be faithfully calculated with desired fitting accuracy.
[0057]
FIG. 12 is a diagram illustrating a fitting residual which is a difference between a simulation result and a measurement result of the line width in the three test patterns illustrated in FIG.
In FIG. 12, the vertical axis represents the fitting residual (unit: nm), the horizontal axis represents the length measurement point, and the black diamond symbol represents the fitting residual that is the simulation result-the measurement result.
As in FIG. 11, the length measurement points 1 to 4 correspond to the first test pattern 1, the length measurement points 5 to 8 correspond to the second test pattern 2, and the length measurement points 9 to 12 correspond to the third test pattern. This is a measurement location in test pattern 3.
[0058]
As shown in FIG. 12, the fitting residuals at the measurement points 1 to 4 in the first test pattern 1 are distributed in a range of 0 to 2 nm. As described above, since the pattern in the first test pattern 1 is a linear pattern, the allowable value of the fitting residual is ± 5 nm. Therefore, the fitting accuracy of the first test pattern 1 is sufficiently high, and the pattern shape after processing can be calculated faithfully.
Residuals at the measurement points 5 to 8 in the second test pattern 2 are distributed in a range of -4 to 1 nm. Since the pattern in the second test pattern 2 is an inverted linear pattern, the allowable value of the fitting residual is ± 5 nm. Therefore, the fitting accuracy of the second test pattern 2 is also sufficiently high.
Further, the residual at the measurement points 9 to 12 in the third test pattern 3 is distributed in the range of -12 to -8 nm. Since the pattern in the third test pattern 3 is a line end pattern, the allowable value of the fitting residual is ± 20 nm. Therefore, the fitting accuracy is also sufficiently high for the third test pattern 3.
[0059]
Therefore, as shown in FIG. 12, for all test patterns and length measurement points, the fitting residuals are sufficiently smaller than the prescribed tolerances and sufficiently satisfy the accuracy of the manufacturing process. Therefore, the extracted model can obtain sufficient accuracy, can accurately calculate the pattern shape after processing, and is an accurate model.
Using the above model, using the layout data of the circuit pattern in the semiconductor device, when forming the circuit pattern on the semiconductor substrate, a simulation is performed on the formed pattern, and the shape, size, and distribution of the formed pattern are performed. Is calculated. The mask correction amount is calculated from the difference between the pattern obtained by the simulation and the target pattern to obtain an OPC correction mask pattern.
[0060]
The process of extracting a model for obtaining an OPC correction mask pattern for forming a gate layer using the test pattern described above is summarized in the flowchart of FIG. 13, the description of the same contents as in FIG. 5 will be omitted as appropriate.
FIG. 13 is a flowchart illustrating an example of processing in model extraction and verification in model-based OPC in the first embodiment.
Step S21:
A first test pattern 1, a second test pattern 2, and a third test pattern 3 are formed.
Step S22:
The pattern width and the space distance between the patterns in each test pattern are measured.
Step S23:
To extract the model, create various files used for the model.
Step S24:
After the extraction of the model for calculating the pattern dimension prediction after formation using the manufacturing process is completed, the line width for forming the first, second, and third test patterns to form the test pattern is calculated using the model. .
[0061]
Step S25:
It is determined whether the fitting residual is within an error tolerance.
Specifically, the pattern was divided into a line pattern and a line end pattern, and the allowable error range was set to -a≤S≤ + a for each of them. Here, S represents a fitting residual, and a is a constant.
If the residual is within the allowable error range, the verification of the model ends, and the model is completed.
If the residual is not within the allowable error range, the process returns to step S23, where various setting items for performing the simulation are corrected, and the simulation is performed again. Steps S23, S24, and S25 are repeated until the residual falls within the allowable error range.
By simulating the gate layer on the semiconductor substrate using the above model and obtaining a model for calculating a necessary correction amount for each side of the mask pattern, an OPC correction mask pattern can be obtained.
[0062]
In the example described above, the target pattern is each pattern in the gate layer. In order to be directly connected to the electrical characteristics, variations in OPC due to fitting accuracy and errors in the formed target pattern line width must be minimized. Therefore, as described above, since the absolute value becomes a problem during model extraction and verification, the allowable range of the fitting residual is specified as −a to + a, that is, the positive direction and the negative direction are symmetrically specified.
[0063]
According to the above-described embodiment, the allowable range of the fitting residual is specified symmetrically between positive and negative during model extraction and verification due to the characteristics of the gate layer described above. Is an appropriate process.
[0064]
Second embodiment
Next, another example of model extraction and verification will be described for a method of expanding the allowable value of the fitting residual by considering matching with layers existing above and below a layer to be subjected to OPC correction.
As described in the first embodiment, in model-based OPC, at the time of model extraction and verification, it is important how to accurately match the experimental result of the test pattern with the simulation result of the model.
[0065]
However, as described above, the pattern line width is becoming finer with the increase in the integration and speed of the semiconductor device, and the memory portion and the logic portion having different pattern densities are mixed. Is complicated. At the time of model creation and verification, experimental results and simulation results must be combined for each process such that such patterns do not depend on line width and pattern density. In this case, there is a limit to improving the model accuracy by the above method.
[0066]
In the first embodiment, since a gate layer is assumed, high-precision gate line width controllability is desired. Therefore, regardless of time and labor, fitting accuracy must be kept within specified values as much as possible. Specifically, the allowable range of the residual is set in a positive-negative symmetry with -a to + a (a is a constant).
However, with respect to other layers, there is a case where it is not necessary to specify the allowable range of the fitting residual with positive / negative symmetry depending on the correlation with the peripheral pattern. In this case, if the allowable range of the fitting residual is specified with positive / negative symmetry, the allowable range of the model does not match the actual situation, it is difficult to obtain a reasonable evaluation, and there is a possibility that it takes more time than necessary for model extraction. .
In the present embodiment, each pattern defines the allowable range of the fitting residual while considering the characteristics of the semiconductor device, thereby facilitating rational model evaluation and shortening the required time.
[0067]
Next, a specific example of model extraction and verification using a test pattern will be described. For example, consider the case where an OPC correction mask pattern is obtained by focusing on matching with a contact when forming a wiring layer in a semiconductor device or the like.
In a wiring layer in a semiconductor device or the like, contact holes are usually formed in upper and lower layers, and a wiring pattern must secure connection with these contact holes.
In order to extract a model for simulating a wiring layer, the patterns shown in FIGS. 6 to 8 are used as test patterns as in the first embodiment. However, it is understood that each pattern (hatched portion) in FIGS. 6 to 8 is a wiring pattern.
[0068]
As in the first embodiment, test patterns 1, 2, and 3 are formed in accordance with the semiconductor device manufacturing process, and the dimension of each length measurement point is measured.
Note that, similarly to the first embodiment, for convenience, the layout patterns 1, 2, and 3 on the photomask are formed as designed values.
Next, layout data, measurement results, and various condition files of the test patterns 1, 2, and 3 are input to the lithography simulation tool to create a model.
[0069]
Next, the model is determined based on the fitting result of the model. The fitting residual is used as an index.
First, a specified value of a fitting residual is determined from a design rule of a circuit pattern of an actual semiconductor device.
For example, in the present embodiment, the minimum rule of the wiring pattern is 200 nm, and the allowable value of the residual is ± 5 nm for the line pattern and ± 20 nm for the line end pattern, as in the first embodiment. Therefore, for test pattern 1 and test pattern 2, the allowable value of the fitting residual is ± 5 nm, and for test pattern 3, the allowable value of the fitting residual is ± 20 nm.
[0070]
Next, the fitting residual is checked.
FIG. 14 is a diagram for comparing a measurement result of a line width in a test pattern with a simulation result.
In FIG. 14, the vertical axis indicates half EPE2 of the difference between the measurement result and the design value and the half EPE1 of the difference between the simulation result and the design value, and the horizontal axis indicates the length measurement point. The definition of the symbols is the same as in FIG.
FIG. 15 is a diagram showing fitting residuals, in which the vertical axis represents fitting residuals (unit: nm), the horizontal axis represents length measurement points, and the definition of symbols is the same as in FIG.
[0071]
As shown in FIGS. 14 and 15, the simulation result is smaller than the measurement result, that is, the simulation pattern is thinner than the actually formed pattern.
Specifically, the length measurement points 1 to 4 measure the central part of the center pattern of the five bar-shaped patterns in the test pattern 1. Because of the line-shaped pattern, the allowable value of the residual is ± 5 nm. For example, a residual of −6 nm occurs at the measurement point 1 and a residual of −7.8 nm occurs at the measurement point 4.
As for the test pattern 2, all of the four length measurement points 5 to 8 exceed the allowable value of -5 nm to -16 nm.
Since the length measurement points 9 to 12 have a tolerance of ± 20 nm because of the line end pattern, there is no problem.
[0072]
Normally, when the fitting residual exceeds an allowable range, the fitting accuracy is determined to be insufficient, various setting items in the model are corrected, and the test pattern simulation is performed again. Conventionally, the correction and the re-simulation were repeated until the fitting residual was within the allowable range. However, in the present embodiment, when the OPC is actually performed, each pattern whose residual exceeds the allowable value is replaced by another pattern. From the correlation with the layers, the fitting residual is reevaluated, and the number of times of correcting the mask pattern data and repeating the simulation is reduced or omitted.
[0073]
Next, for each point where the fitting residuals confirmed above exceed the allowable value, the fitting residuals are determined from the correlation with other layers when the OPC is actually performed.
For the test pattern 1, a fitting residual is generated in a direction in which the line width of the simulation result is smaller than the measurement result at both the point 1 and the point 4.
Each bar-shaped pattern in the test pattern 1 is a wiring pattern in a wiring layer. The wiring pattern is always connected to the contact holes in the upper and lower layers. This must be taken into account when simulating the wiring layer.
[0074]
FIG. 16 shows the relationship and influence between a wiring pattern and a contact in a simulation of a wiring layer.
Here, it is assumed that the measurement result of the test pattern is the same as the design value. That is, the experimental results are as desired.
FIG. 16A shows a wiring pattern 4 whose line width is a measurement result (= design value), and two broken lines on both sides show the width of the wiring pattern 4 (measurement result = design value).
FIG. 16B shows a wiring pattern 5 whose line width is a simulation value. As shown, the wiring pattern 5 is thinner than the wiring pattern 4.
FIG. 16C shows the pattern 6 after the correction. Specifically, the target wiring pattern is corrected with the model that has output the wiring pattern 5 without performing further model adjustment on the wiring pattern 5.
FIG. 16D shows a wiring pattern 14 formed on a semiconductor substrate, a contact hole 16 formed on an upper layer of the wiring pattern 14, and a wiring pattern 14 formed on a lower layer of the wiring pattern 14 using the OPC correction photomask 6. FIG.
[0075]
FIG. 17 is a partial cross-sectional view of the semiconductor device including the wiring layer 14 and its upper and lower layers shown in FIG.
The semiconductor device shown in FIG. 17 includes an insulating layer 11, a contact hole 12 formed in the insulating layer 11, a second insulating layer 13 formed on the insulating layer 11, and a second insulating layer 13. It has a formed wiring pattern, a third insulating layer 15 formed to cover the second insulating layer 13 and the wiring pattern, and a contact hole formed in the third insulating layer 15.
The second insulating layer 13 and the wiring pattern 14 become the wiring layer of the present embodiment.
[0076]
As shown in FIG. 16D, since the simulation value of the line width (the width of the wiring pattern 5) is smaller than the measurement result (the width of the wiring pattern 4), the mask correction amount is more than necessary. That is, the width of the OPC correction photomask 6 is wider than the target width, and as a result, the actually formed wiring pattern 14 also becomes thicker than the designed value, and a thicker wiring can be formed.
However, when the line width of the wiring increases, the upper and lower contact holes always fall into the wiring, so that the connection between the wiring pattern and the upper and lower contact holes can be secured, which is desirable.
[0077]
However, care must be taken that the wiring resistance increases.
Next, a change in wiring resistance is confirmed from the difference between the target line width (design value) of point 1 and point 4 and the simulation line width.
The target line widths of point 1 and point 4 are 400 nm and 600 nm, respectively, and as shown in FIG. 15, the fitting residuals of point 1 and point 4 are -6 nm and -7.8 nm, respectively.
For example, the longitudinal direction of the wiring pattern 14 (the direction perpendicular to the plane of FIG. 17) is 1 μm. 1 μm²Rm (Ω / μm²), The wiring resistance at point 1 and point 4 is 0.4−0.006 * 2 = 0.388 Rm (Ω / μm²) And 0.6−0.008 * 2 = 0.584 Rm (Ω / μm)²).
[0078]
On the other hand, the specified wiring resistance of the wiring pattern having the line widths of 400 nm and 600 nm is 0.4 Rm (Ω / μm²) And 0.6Rm (Ω / μm)²), The ratio of the wiring resistance at point 1 and point 4 to the specified wiring resistance is 0.388 / 0.4 = 0.97 and 0.584 / 0.6 = 0.97.
That is, since the wiring pattern 14 becomes thicker, its wiring resistance is reduced by 3%. Such a decrease in the wiring resistance is an allowable value according to the design rule, and therefore does not cause any problem.
Therefore, when the fitting residual is in the negative direction of the allowable range at the time of model extraction and verification, the actual wiring becomes thicker, but there is no problem because the connection with the contact holes in the upper and lower layers can be secured. Therefore, it is not necessary to repeat pattern correction and simulation in order to reduce this residual, and it is determined that the fitting accuracy is sufficiently high.
[0079]
Next, in the test pattern 2, when each point where the fitting residual exceeds the allowable value is actually subjected to OPC, the pattern considers the correlation with other layers.
As shown in FIGS. 14 and 15, in the test pattern 2, a fitting residual is generated in a direction in which the line width of the simulation result becomes narrower than that of the measurement result at all of the points 5, 6, 7, and 8. .
Specifically, the allowable value of the fitting residual of the on-line pattern is within ± 5 nm, whereas the fitting residual of point 5 is −5.3 nm, point 6 is −9.5 nm, and point 7 is −16. 2 nm, point 8 is -12.5 nm.
Since the opening 2a in the test pattern 2 is a space between the wirings in the wiring layer, when the space between the wirings changes, the width of the wiring pattern on both sides of the space also changes. As described above, since the wiring pattern is always connected to the contact holes in the upper and lower layers, this point must be taken into account when simulating the space between wirings. For example, when the space between the wirings is large, the width of the wiring is reduced, which is not preferable from the viewpoint of the connection between the wiring and the contact hole.
[0080]
When the space between the wirings becomes larger and the width of the wiring becomes smaller than the design value, the allowable range of the space between the wirings and the variation of the wiring pattern line width is determined from the matching accuracy with the contact.
FIG. 18 shows the effect on the contacts of the variation in the space between wirings in the simulation of the wiring layer.
FIG. 18A shows a wiring structure in which an inter-wiring space 21c whose line width is a measurement result (design value) is formed between the wiring patterns 21a and 21b, and two broken lines indicate the inter-wiring space 21c. Indicates the width.
FIG. 18B shows the inter-wiring space 22c whose width is a simulation value, and as shown, the space 22c is smaller in width than the space 21c. Therefore, the width of the wiring patterns 22a and 22b is calculated to be large.
FIG. 18C shows the OPC correction photomask 23. More specifically, a target wiring space is simulated using a model that outputs the inter-wiring space 22c. According to the fitting model, the OPC correction photomask 23 is obtained by adding the width of the wiring patterns 21a and 21b. In the OPC correction photomask 23, the space 23c is larger than the design width (the width of the space 21c), and the width of the wiring patterns 23a and 23b on both sides of the space 23c has a negative mask correction amount. Are thinner than the wiring patterns 21a and 21b shown in FIG.
FIG. 18D shows, using the OPC correction photomask 23, the wiring patterns 24a and 24b formed on the semiconductor substrate, the space 24c between the wirings, and the contact holes 16a formed in the upper layer of the wiring patterns 24a and 24b. 16b and contact holes 12a and 12b formed in the lower layer of the wiring patterns 24a and 24b.
[0081]
As shown in FIGS. 18A to 18D, the simulation value (the width of the space 22c) of the line width of the space between the wirings is smaller than the measurement result or the design value (the width of the space 21c). Calculation is made thicker (wiring patterns 22a and 22b). Therefore, the mask correction amount is set to a value smaller than the required correction amount. That is, the wiring pattern 23a is thinner than the target value, and as a result, the actually formed wiring patterns 24a and 24b are thinner than the design value.
However, since the wiring patterns 24a and 24b may be connected to the contact holes 16a and 12a and 16b and 12b in the upper and lower layers, misalignment between the wiring patterns 24a and 24b and these contact holes is confirmed.
[0082]
Regarding the misalignment between the wiring pattern and the contact hole, the wiring width (FIG. 18D, 24a and 24b) and the contact hole 16a, 16b (or 12a, 12b) after the simulation in which OPC is performed on the design value. Since there is no problem if the interval satisfies the overlay on the design rule, satisfying the following equations 1 and 2 is a condition for a good connection between the wiring pattern and the contact hole.
[0083]
FIG. 19 is an enlarged view of the wiring pattern 24a or the wiring pattern 24b shown in FIG. In order to simplify the drawing, in FIG. 19, the contact holes 12a or 12b are not shown, the oblique lines are omitted, and the reference numerals of the wiring patterns and the contact holes are 24 and 16.
As shown in FIG. 19, the diameter of the contact hole 16 is indicated by D, the maximum value is indicated by Dmax, and the minimum value is indicated by Dmin. The line width of the wiring pattern 24 is L, the maximum value is Lmax, and the minimum value is Lmin.
The distance from the contact hole 16 to the edge of the wiring pattern 24 is indicated by S1 and S2, and a small value of S1 and S2 is Smin. The overlay between the wiring layer 24 and the contact hole 16 determined by the design rule is δL.
[0084]
In order to secure the connection between the wiring layer and the contact hole, the following condition must be satisfied.
δL <Smin (1)
D + 2 · δL <L (2)
[0085]
According to Equation 1, the overlay must be ensured also on the short side (S1 or S2) from the contact hole 16 to the edge of the wiring pattern 24.
According to Equation 2, the sum of the diameter of the contact hole 16 and twice the overlay must not exceed the width of the wiring pattern 24.
[0086]
Next, specific numerical examples will be given.
In the test pattern 2, the widths of the spaces between the wirings at points 5 to 8 where the residual exceeds the allowable value are 150 nm, 200 nm, 500 nm and 1000 nm, respectively, and the respective fitting residuals are as shown in FIG. , -5.3 nm, -9.5 nm, -16.2 nm, and -12.5 nm, and the correction amounts after OPC were 3 nm, 5 nm, 10 nm, and 10 nm, respectively.
The diameter of the contact hole 16 is fixed to 200 nm, that is, Dmax = Dmin = D = 200 nm. The overlay δL between the wiring layer and the contact hole is 20 nm regardless of the width of the wiring pattern.
The test pattern 2b is a square of 10 μm square, and the wiring width here is represented by (10 μm−line width of 2a after OPC) / 2.
Under such conditions, it is checked whether Expressions 1 and 2 are satisfied.
[0087]
Since the wiring portion (shaded area) of the pattern 2 is about 5 μm, S1 and S2 at points 5 to 8 all satisfy Expression 1.
Since the diameters of the contact holes 16 are all 200 nm, D + 2 · δL = 200 + 2 × 20 = 240 nm when the left side of Equation 2 is calculated for points 5 to 8.
Next, if the width of the wiring pattern at point 5 is L5,

Similarly, L6 = 4895 nm, L7 = 4740 nm, and L8 = 4490 nm.
That is, all of the points 5 to 8 satisfy Expression 2. Therefore, it has been found that there is no problem in misalignment between the wiring pattern 24 and the contact hole 16.
[0088]
Thus, at the time of model extraction and verification, even if the fitting residual of the space between wirings exceeds the allowable range, it is acceptable as long as it does not affect the device characteristics. Actually, as described above, when the misalignment between the wiring pattern and the contact hole after the OPC is confirmed, it can be seen that the connection between the wiring pattern and the contact hole can be sufficiently secured, and no problem occurs. Therefore, it can be said that the fitting accuracy is sufficiently high.
Therefore, sufficient accuracy is obtained as a model for all test patterns and length measurement points, and the model is accurate.
As a result, it is not necessary to repeat the pattern modification and simulation to reduce the measured residual. As a result, the time required for model extraction and verification can be reduced.
[0089]
Using the above model, light intensity simulation is performed using mask pattern data for forming a wiring layer composed of test patterns 1, 2, and 3, and the shape, size, and distribution of each pattern in the wiring layer are calculated. I do. A correction amount is calculated from a difference between the pattern obtained by the simulation and the design pattern, and an OPC correction mask pattern is obtained.
[0090]
The process of extracting the model for obtaining the OPC correction mask pattern for forming the wiring layer using the test pattern described above is summarized in the flowchart of FIG. In FIG. 20, the description of the same contents as in FIG. 13 will be appropriately omitted.
FIG. 20 is a flowchart illustrating an example of processing in model extraction and verification in model-based OPC in the second embodiment.
[0091]
Step S31:
A first test pattern 1, a second test pattern 2, and a third test pattern 3 are formed.
Step S32:
The pattern width and the space distance between the patterns in each test pattern are measured.
Step S33:
To extract the model, create various files used for the model.
Step S34:
Using the extracted model, the pattern line width in the first, second, and third test patterns 3 is calculated using the test pattern data.
[0092]
Step S35:
The measurement result is compared with the simulation value to determine whether or not the fitting residual is within an allowable error range.
Specifically, the pattern was divided into a line pattern and a line end pattern, and the allowable error range was set to -a≤S≤ + a for each of them. Here, S represents a fitting residual, and a is a constant.
If the residual is within the allowable error range, the process proceeds to step 39, where the model verification is completed and the model is completed.
If the residual is not within the allowable error range, the process proceeds to step S36.
[0093]
Step S36:
For the points where the residual exceeds the (-a, + a) range, the characteristics of the relevant pattern are checked. If the residual moves in the negative direction and the positive direction beyond the (-a, + a) range, it is sent to the device. Analyze the effects of
For example, in the case of a wiring pattern, when the width of the wiring pattern becomes thinner or thicker, the effect on the connection between the wiring pattern and the upper and lower contact holes is analyzed.
As a result, the upper limit and the lower limit that can secure the connection between the two are found, and a new residual allowable range −b ≦ S ≦ + c is determined. Here, b and c are constants.
[0094]
Step S37:
For each point where the residual exceeds the (-a, + a) range, it is checked whether the residual falls within the residual tolerance -b≤S≤ + c.
Step S38:
If the residual is within -b≤S≤ + c, the process proceeds to step 39, where the model verification is completed, and the model is completed.
If the residual does not fall within the range of -b≤S≤ + c, the process returns to step S33, where various setting items for performing the simulation are corrected, and the simulation is performed again. Steps S33 to S38 are repeated until the residual enters −b ≦ S ≦ + c.
[0095]
Thus, model extraction and verification are completed.
By simulating a target pattern on a semiconductor substrate using the above model and calculating the correction amount of each side of the mask pattern, an OPC correction mask pattern can be obtained.
[0096]
According to the above-described embodiment, even when the fitting residual exceeds the specified allowable range, the fitting accuracy is not made insufficient, and when the OPC is actually performed, the excess of the residual becomes a pattern. The characteristics of the device, for example, the influence on the connection state between the wiring layer and the contact hole are determined, and the allowable range of the fitting residual is reevaluated. As a result, it is not necessary to repeat processing such as model correction in order to reduce the excess residual, and reasonable model evaluation can be easily achieved, and the time required for model extraction and verification can be reduced.
[0097]
Third embodiment
In the present embodiment, a model is extracted and verified using a test pattern by the method described in the first and second embodiments, and an OPC correction mask pattern is obtained by model-based OPC. An example of manufacturing a semiconductor device using the OPC correction mask pattern will be described.
In the present embodiment, first, model extraction and verification are performed. The method of model extraction and verification is the same as the method described in the first and second embodiments.
That is, the allowable range of the fitting residual is evaluated from the influence of the characteristics of the pattern to be formed on the semiconductor device and the variation of the pattern line width on the semiconductor device characteristics, and a reasonable model evaluation is easily achieved in a short time.
For example, in the case of the wiring pattern and the space between the wirings, the allowable range of the error of the wiring pattern and the space between the wirings is determined from the connection relationship between the wiring pattern and the contact holes in the upper and lower layers.
An OPC correction mask pattern is created based on the model thus obtained, and a semiconductor device is manufactured.
[0098]
FIG. 21 is a partial cross-sectional view showing a process for manufacturing the semiconductor device shown in FIG.
FIG. 21A shows, for example, a photomask 31 on which an opening pattern 32 is formed and an optical system 33 in the exposure apparatus.
The photomask 31 is a photomask that has been subjected to OPC by the model-based OPC using the model obtained as described above.
Laser light 40 from a light source (not shown) passes through a photomask 31 and irradiates an underlying semiconductor substrate via an optical system 33.
[0099]
FIG. 21B shows the insulating layer 11 made of, for example, an oxide film. Although not shown, a photoresist film is applied on the insulating layer 11, light from the exposure apparatus shown in FIG. 21A irradiates the photoresist film, exposure is performed, and the opening pattern 32 on the photomask 31 is formed on the insulating layer 11. Then, a contact hole 12 is formed. Thereafter, the photoresist is removed.
In the contact hole 12, for example, a metal such as W is deposited.
Next, as shown in FIG. 21C, a second insulating layer 13 made of, for example, an oxide film is formed on the insulating layer 11, and an opening for forming a wiring layer in the second insulating layer 13 is formed. 14b is formed by exposure. Although the photomask used at this time is different from that used in the step of FIG. 21B, it is referred to as a photomask 31 for convenience.
[0100]
Next, as shown in FIG. 21D, for example, a metal such as W is deposited in the opening 14b to form the wiring layer 14.
Then, a third insulating layer 15 is formed to cover the second insulating layer 13 and the wiring layer 14. Then, exposure is performed in the same manner as in FIG. 21B, the opening pattern 32 on the photomask 31 is transferred to the insulating layer 15, and the contact hole 16 is formed.
As in FIG. 21C, the photomask used at this time is different from that used in the steps of FIGS. 21B and 21C, but is referred to as a photomask 31 for convenience.
[0101]
The mask correction amount of the photomask 31, which is an OPC correction photomask, is obtained by evaluating the allowable range of the fitting residual due to the influence of the characteristics of the pattern to be formed in the semiconductor device and the fluctuation of the pattern line width on the semiconductor device characteristics. Was. For example, in the case of a wiring pattern, the allowable range of errors in the wiring pattern and the space between the wirings is determined from the connection relationship between the wiring pattern and the contact holes in the upper and lower layers. Therefore, the connection between the wiring pattern 14 and the contact holes 12 and 16 in the upper and lower layers is sufficiently ensured.
[0102]
According to the present embodiment, the time required for obtaining the mask correction amount can be reduced by the model-based OPC, and the connection between the formed wiring pattern and the contact holes in the upper and lower layers can be secured.
[0103]
As described above, the present invention has been described based on the preferred embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.
For example, in the above embodiment, the allowable range of the residual is evaluated based on the connection relationship between the pattern and another layer, but other device characteristics may be used.
In the above-described embodiment, an example in which the fitting residual is negative has been described. However, even when the residual is positive, the device characteristics can be similarly analyzed and the allowable range of the residual can be evaluated.
[0104]
【The invention's effect】
According to the photomask design method, photomask, and semiconductor device of the present invention described above, the allowable range of the simulation error is determined by the characteristics of the pattern in the device and the influence of the error of the pattern on the device characteristics. Since it is only necessary that each pattern satisfies the simulation accuracy actually required, there is no need to perform unnatural operations such as modifying the model more than necessary simply to reduce simulation errors. Model evaluation can be easily achieved, and the time required for model extraction and verification can be reduced.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating an outline of a process related to a model-based OPC in a first embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a model fitting process in model-based OPC in the first embodiment of the present invention.
FIG. 3 is a diagram schematically showing a process of performing a simulation on an actual circuit using model-based OPC in the first embodiment of the present invention.
FIG. 4 is a diagram schematically showing a shape after transferring and processing layout data of an actual circuit to which model-based OPC has been applied in the first embodiment of the present invention.
FIG. 5 is a flowchart showing an outline of a process relating to model extraction and verification in model-based OPC in the first embodiment of the present invention.
FIG. 6 shows a first example of a test pattern used in the first embodiment of the present invention.
FIG. 7 shows a second example of the test pattern used in the first embodiment of the present invention.
FIG. 8 shows a third example of the test pattern used in the first embodiment of the present invention.
FIG. 9 is a diagram illustrating a definition of a fitting residual used in the embodiment of the present invention.
FIG. 10 is a diagram illustrating the definition of the fitting residual used in the embodiment of the present invention, following FIG. 9;
FIG. 11 is a diagram comparing a line width measured using a test pattern and a simulation result in the first embodiment of the present invention.
FIG. 12 is a diagram showing a residual between a simulation result and a measurement result of a line width in a test pattern in the first embodiment of the present invention.
FIG. 13 is a flowchart illustrating a specific example of processing in model extraction and verification in model-based OPC in the first embodiment of the present invention.
FIG. 14 is a diagram comparing a line width measured using a test pattern and a simulation result in the second embodiment of the present invention.
FIG. 15 is a diagram showing a residual between a simulation result and a measurement result of a line width in a test pattern in the second embodiment of the present invention.
FIG. 16 is a diagram showing a relationship and an influence between a change in a line width of a wiring pattern and a contact in a simulation of a wiring layer in the second embodiment of the present invention.
FIG. 17 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 18 is a diagram showing, in a simulation of a wiring layer, a relationship between contacts and an influence of a change in a space between wirings in a second embodiment of the present invention.
FIG. 19 is a diagram showing misalignment between a wiring pattern and a contact hole in the second embodiment of the present invention.
FIG. 20 is a flowchart illustrating a specific example of processing in model extraction and verification in model-based OPC according to the second embodiment of this invention.
FIG. 21 is a partial cross-sectional view showing a process for manufacturing the semiconductor device according to the third embodiment of the present invention.
[Explanation of symbols]
1, 2, 3 ... test pattern, 1a ... pattern, 1b ... measurement location, 1c ... actual pattern, 1d ... simulation pattern, 2a ... opening, 2b ... pattern, 2c ... measurement location, 3a, 3b ... pattern, 3c ... Measurement locations, 3d: pattern line width, 4: design wiring pattern, 5: simulation pattern, 6: OPC correction mask, 11: insulating layer, 12, 12a, 12b: contact hole, 13: insulating layer, 14: wiring layer, Reference numeral 15: insulating layer, 16, 16a, 16b: contact hole, 21a, 21b: design wiring pattern, 21c: space between design wirings, 22a, 22b: simulation wiring pattern, 22c: space between simulation wirings, 23: OPC correction mask 23a, 23b: corrected wiring pattern, 23c: corrected inter-wiring space, 24 , 24b formed wiring pattern, 24c formed wiring space, 31 photomask, 32 opening pattern, 33 optical system, 101 test pattern layout data, 102 test pattern photomask, 103 ... Wafer, 104: Test pattern, 105: Process model, 106: Layout data of actual circuit, 107: Simulation pattern, 108: OPC correction pattern, 109: Target pattern

Claims (15)

Forming a plurality of test patterns that can constitute a target pattern to be formed, and measuring the dimensions of the test patterns;
Using the measurement results of the test pattern dimensions, extracting a model for calculating the dimensions of the test pattern,
A step of adjusting parameters in the model until a difference between a calculation result of the test pattern dimension by the model and a measurement result of the test pattern dimension is within a predetermined error range;
Obtaining a correction to a photomask for forming the target pattern by the adjusted model,
A photomask designing method in which the error range is determined by characteristics of the target pattern in a semiconductor device. The error range is from a predetermined minimum value to a maximum value,
2. The photomask designing method according to claim 1, wherein the minimum value and the maximum value are independently determined according to characteristics of the target pattern in a semiconductor device. The target pattern includes a linear pattern to be a wiring pattern in the semiconductor device,
3. The photomask designing method according to claim 2, wherein a minimum value and a maximum value of the error range are determined according to a connection state between the wiring pattern and a contact hole connected to the wiring pattern. The target pattern includes a groove-shaped line pattern to be a groove between wiring patterns in a semiconductor device,
3. The photomask designing method according to claim 2, wherein a minimum value and a maximum value of the error range are determined according to a connection state between the wiring pattern on both sides of the groove-shaped line pattern and a contact hole connected to the wiring pattern. The photomask designing method according to claim 1, wherein an optical proximity effect correction (OPC) for a photomask for forming the target pattern is obtained by the model. A photomask that has been subjected to correction for forming a target pattern,
The amount of correction, the difference between the measurement result of the dimensions of the plurality of test patterns formed in advance and the calculation result of the dimensions of the test pattern by the model is within the error range determined by the characteristics of the target pattern in the semiconductor device. Photomask required to become. The error range is from a predetermined minimum value to a maximum value,
7. The photomask according to claim 6, wherein the minimum value and the maximum value are independently determined by characteristics of the target pattern in a semiconductor device. The target pattern includes a linear pattern to be a wiring pattern in the semiconductor device,
8. The photomask according to claim 7, wherein a minimum value and a maximum value of the error range are determined according to a connection state between the wiring pattern and a contact hole connected to the wiring pattern. The target pattern includes a groove-shaped line pattern to be a groove between wiring patterns in a semiconductor device,
8. The photomask according to claim 7, wherein a minimum value and a maximum value of the error range are determined according to a connection state between the wiring pattern on both sides of the grooved line pattern and a contact hole connected to the wiring pattern. Includes an OPC correction mask pattern that has been subjected to optical proximity effect correction,
The photomask according to claim 6, wherein the correction amount of the light approach effect correction is obtained by the model. A semiconductor device including a target pattern formed using a corrected photomask,
The amount of correction is a difference between a measurement result of dimensions of a plurality of test patterns formed in advance and a calculation result of dimensions of the test pattern by a model within an error range determined by characteristics of the target pattern in a semiconductor device. Semiconductor device required to be. The error range is from a predetermined minimum value to a maximum value,
12. The semiconductor device according to claim 11, wherein the minimum value and the maximum value are independently determined by characteristics of the target pattern in the semiconductor device. The target pattern includes a wiring pattern,
13. The semiconductor device according to claim 12, wherein a minimum value and a maximum value of the error range are determined according to a connection state of the wiring pattern and a contact hole connected to the wiring pattern. The target pattern includes a wiring pattern groove,
13. The semiconductor device according to claim 12, wherein a minimum value and a maximum value of the error range are determined according to a connection state of the wiring pattern on both sides of the groove between the wiring patterns and a contact hole connected to the wiring pattern. The semiconductor device according to claim 11, wherein the photomask includes an OPC correction mask pattern on which an optical proximity effect correction has been performed.

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