JP2004157160A - Method for forming process model, method for designing mask pattern, mask and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a process model to eliminate errors caused by variance in the mask manufacturing process, to provide a method for designing a mask pattern including the above method, and to provide a mask and a method for manufacturing a semiconductor device. <P>SOLUTION: The method for forming a process model includes processes of forming a designed test pattern on a test mask, reproducing the test pattern based on the measurement of the test pattern on the test mask, and fitting the designed data of the reproduced test pattern and the measurement result of the pattern transferred in the process of exposing the test mask. The method for designing a mask pattern includes a process of correcting the pattern by using the above method. The mask has a mask pattern designed by the above method. The method for manufacturing a semiconductor device includes a lithographic process using the above mask. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mask used for lithography, a method for designing a mask pattern formed on the mask, a method for creating a process model used in a simulation process in mask pattern design, and manufacturing of a semiconductor device including lithography using a mask. About the method.
[0002]
[Prior art]
At present, in a manufacturing process of a semiconductor device, an optical lithography technique is mainly used to form a pattern for a semiconductor element on a semiconductor substrate. A photomask used for optical lithography is an original plate for exposure on which a pattern composed of a transparent region and a light shielding region is formed. A photomask whose reduction ratio is not 1: 1 is particularly called a reticle.
[0003]
In optical lithography, a layout pattern (mask pattern) of a photomask is transferred onto a wafer coated with a photosensitive resin called a resist by, for example, a reduction projection exposure apparatus. By developing the resist exposed through the photomask, a predetermined resist pattern is obtained.
[0004]
In the conventional photolithography technology, the development of an exposure apparatus, particularly by increasing the numerical aperture (NA) of a projection lens system, has been attempted to cope with miniaturization of a semiconductor element. As is known as the Rayleigh equation, the following equation (1) is established between the limit resolution R (the size of the limit fine layout pattern that can be resolved) and the NA. As the NA increases, the limit resolution decreases, and a high resolution can be obtained.
R = K₁  × λ / NA (1)
(K₁  Is a constant that depends on the process such as resist performance)
[0005]
Although the resolving power is improved by increasing the NA of the exposure apparatus, the depth of focus (the range in which the deviation of the focal position is allowed) is reduced, and it has become difficult to further miniaturize from the viewpoint of the depth of focus. The depth of focus DOF and NA have the relationship of the following equation (2). As the NA is increased, the depth of focus becomes narrower, and a slight shift of the focal position cannot be tolerated.
DOF = K₂  × λ / NA²    ... (2)
(K₂  Is a process-dependent constant)
[0006]
Therefore, various super-resolution techniques have been studied. In general, the super-resolution technique is a technique for improving the light intensity distribution on the image plane by controlling the transmittance and the phase on the pupil plane of the illumination optical system, the photomask, and the projection lens system. As a super-resolution technique for improving the resolution characteristics by optimizing the illumination optical system, there is a modified illumination method.
[0007]
Further, as a super-resolution technique by improving the photomask side, use of a phase shift mask can be cited. For example, a halftone phase shift mask has attracted attention because its manufacture and mask pattern design are easier than other phase shift masks. In a halftone type phase shift mask, the light shielding film of a normal binary mask is replaced with a translucent film made of chromium oxynitride or the like having a transmittance of about 4 to 10%, and the transmitted light of the translucent film and the surrounding transparent region are removed. A phase difference of 180 degrees is generated in the transmitted light.
[0008]
In a halftone type phase shift mask, light intensity decreases due to interference between lights having a phase difference of 180 degrees at a boundary between a transparent region and a translucent region, and the light intensity distribution becomes steep. However, since the light intensity decreases near the boundary between the transparent region and the translucent region, a correction (mask bias) for increasing the size of the transparent region is necessary in order to obtain a desired resist pattern size. Become.
[0009]
In the pattern formation near the resolution limit, the influence of the optical proximity effect (Optical Proximity Effect) becomes remarkable. The optical proximity effect is a phenomenon in which a pattern is affected by a peripheral pattern and changes in shape and dimensions. Therefore, an optical proximity correction (OPC: Optical Proximity Correction) method in consideration of the optical proximity effect is being actively studied in addition to the above-described super-resolution technology.
[0010]
In the OPC method, a desired resist pattern is formed by deforming a mask pattern in advance. Examples of the OPC method include a method of simply changing the size of the mask pattern (mask bias) and a method of changing the size of a part of the mask pattern (jog), and the mask bias and the jog are distinguished.
[0011]
As another example of the OPC method, there is a method of arranging a fine pattern smaller than the resolution limit at a corner of the layout pattern (such as a hat and a self). The mask correction amount in the OPC is determined depending on its own pattern size, shape, and peripheral layout pattern. A method of obtaining the mask correction amount from the result of simulation using an arithmetic unit (computer or simulator) based on the actual measurement result of a sample created by actually transferring a test pattern is called model-based OPC.
[0012]
In the simulation of the manufacturing process of a semiconductor device (process simulation), a lithography process, an ion implantation process, an impurity diffusion process, and other processes are simulated by an arithmetic unit without actually manufacturing the semiconductor device, and the shape and impurities of each part are measured. Is to predict the concentration distribution and the like.
[0013]
According to such a process simulation, when a mask pattern formed on a photomask is exposed on a resist on a wafer, and the wafer is etched using the resist pattern obtained by development as a mask, the mask is formed on the wafer. Patterns can be predicted from design data.
[0014]
In the model-based OPC, the design data input to the arithmetic unit is applied to a wafer (or a conductive layer or an insulating layer formed on the wafer). Hereinafter, for simplification, a sample wafer, a conductive layer or The pattern formed on the insulating layer is simply referred to as a wafer is simulated. Simulation is performed on a plurality of design data in which the mask correction amount has been changed, and the mask correction amount when the simulation result and the original design data are closest to each other is determined as the optimum correction amount.
[0015]
The design data input to the arithmetic unit is usually GDSII data (design data represented in a standard expression format of mask pattern data proposed by Karma Corporation in the United States). The determined mask correction amount is added to the design data using an arithmetic unit. A process model used for simulation of the conventional model-based OPC is created as follows. A conventional process model creation method will be described with reference to a flowchart of FIG.
[0016]
Step 1 (ST1)
The layout data (GDSII data) of the test pattern is created. The test pattern is a collection of simplified patterns that can represent layout patterns of various shapes and sizes existing in a design circuit of a semiconductor device. In creating a test pattern, a design rule that specifies a pattern permitted in design is considered. A test mask is manufactured using the created test pattern.
[0017]
Step 2 (ST2)
Perform sample preparation by the current process. First, a resist is applied on a wafer for producing a sample, and the resist is exposed through a test mask. The resist is developed to form a resist pattern to which the test pattern has been transferred. Next, the wafer is etched using the resist pattern as a mask, the test pattern is transferred to the wafer, and then the resist is removed. Hereinafter, the wafer on which the test pattern is transferred is referred to as a sample.
[0018]
Step 3 (ST3)
In step 2, the length of the test pattern transferred to the sample is measured. For the length measurement, for example, a scanning electron microscope (SEM) is used.
[0019]
Step 4 (ST4)
Create a condition file to be input to the simulator. The items of the condition file include, for example, layout data (GDSII data) of the test pattern, coordinates and dimensions of the test pattern measured on the sample, and settings of the exposure apparatus.
[0020]
Step 5 (ST5)
Create a process model. Specifically, the various input files created in step 4 are input to the simulator, and a process model that is a function for calculating the size of the test pattern (pattern formed by etching) transferred to the sample is output. . The input file created in step 4 incorporates the GDSII data created in step 1 and the length measurement results on the sample obtained in step 3.
[0021]
Step 6 (ST6)
Regarding the process model output in step 5, it is checked whether the difference between the actual measurement result in step 3 and the simulation result by the created process model (hereinafter referred to as fitting residue) is within a specified value. Here, the specified value is a specification (target value) of the model fitting accuracy set in advance in consideration of manufacturing variations due to a process, the accuracy of a lithography simulator as an arithmetic unit, and the like.
[0022]
If the remaining fittings deviate from the specified values, the process returns to step 4 and corrects the input file of the simulator as appropriate. If the specified value is satisfied, the model fitting ends.
[0023]
By performing a simulation using the model function (process model) created as described above, the actual transfer result of the mask pattern for manufacturing a semiconductor device can be accurately calculated. When the created process model and original layout data (GDSII data) are input to the simulator, layout data to which an OPC pattern is added is obtained.
[0024]
[Problems to be solved by the invention]
In the model-based OPC described above, the mask correction amount is determined on the assumption that the simulation result by the process model is the actual measurement result of the layout pattern. That is, the pattern after OPC includes the remaining fitting. Therefore, it is important how to reduce the fitting residue (perform accurate model fitting). At present, by adjusting the setting conditions at the time of the simulation, the accuracy of the fitting between the actual measurement result and the process model is being improved.
[0025]
In recent years, high integration and high speed operation are required for semiconductor devices, and pattern line widths are becoming finer. For this reason, even a small error of, for example, about several nm has a large effect on device characteristics. In addition, since an integrated circuit is complicated, for example, a memory portion and a logic portion having different layout pattern densities are simultaneously manufactured, the process technology has reached the limit of manufacturing masks and samples. For example, even a process error of a mask that causes an error of several nanometers on a wafer has affected the model fitting.
[0026]
In step 6 of the conventional process model creation method shown in FIG. 11, the goal is to match the actual measurement result and the simulation result, and the fitting residue represented by the following equation (3) is used as an index of the model fitting accuracy.
Fitting residue = simulation result-actual measurement result (3)
[0027]
However, modeling of phenomena occurring in the actual process of sample formation is not perfect, and furthermore, there is a limit to model fitting accuracy due to factors such as definition of measurement points and measurement accuracy. Therefore, it is difficult to completely match the actual measurement result with the simulation result, and there is a problem how to separate uncertain elements and apply high-precision OPC.
[0028]
The actual measurement result of the layout pattern formed by etching the wafer includes a mask manufacturing error generated during the mask manufacturing process. On the other hand, in the process simulation, the original design data (GDSII data) is input assuming that the mask is ideally manufactured. That is, in the process simulation, the actual manufacturing error of the mask is not considered.
[0029]
In the conventional model fitting, a simulation result that does not include a mask manufacturing error is combined with an actual transfer result (actual measurement result) that includes a mask manufacturing error. Worsens.
[0030]
As described above, in the model-based OPC, when simulating a layout pattern formed on a wafer, design data (GDSII data) of a layout pattern that is ultimately desired to be obtained on the wafer is input. When OPC is performed by a process model created using the measurement results of a sample including a mask manufacturing error, the final dimensional control accuracy deteriorates.
[0031]
Even if the simulation condition setting, that is, the condition file input to the simulator is optimized to improve the model fitting accuracy, a desired model fitting accuracy cannot be obtained in the case of a process model including a mask manufacturing error. Therefore, in the model-based OPC, an appropriate mask correction amount cannot be obtained, and a desired fine pattern cannot be formed with a desired dimensional accuracy.
[0032]
The present invention has been made in view of the above problems, and therefore, the present invention provides a process model creation method capable of improving model fitting accuracy by eliminating errors caused by variations in a mask manufacturing process. The purpose is to do.
Another object of the present invention is to provide a mask pattern designing method capable of performing a simulation using a process model from which a mask manufacturing error has been eliminated and controlling the transfer result of the mask pattern with high accuracy.
[0033]
Another object of the present invention is to provide a mask including a mask pattern corrected by a high-precision simulation and capable of transferring a desired layout pattern with high precision.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of transferring a mask pattern corrected by a highly accurate simulation and forming a desired fine pattern with high accuracy.
[0034]
[Means for Solving the Problems]
In order to achieve the above object, a process model creation method according to the present invention provides a simulation process model for predicting a pattern to be transferred by a predetermined process including exposure by using mask pattern design data as input data. A method of creating test pattern data which is design data of a test pattern in which a part of the mask pattern is selected and / or changed; and a step of creating a test mask on which the test pattern is formed. Measuring the length of the test pattern formed on the test mask; regenerating the test pattern data so as to match the length measurement result of the test pattern on the test mask; Transferring the test pattern on the test mask by a process Forming a sample, measuring the length of the test pattern transferred to the sample, performing the simulation using the re-created test pattern data as input data, and performing a test transferred by the predetermined process. A step of estimating a pattern, a length measurement result of the test pattern in the sample, and a result of the simulation for estimating a test pattern to be transferred using the re-created test pattern data as input data having a predetermined error. Performing a fitting so as to fall within the range to create a process model.
[0035]
Thereby, in creating a process model used for the process simulation, it is possible to eliminate an error due to a variation in a mask manufacturing process and improve the model fitting accuracy.
[0036]
In order to achieve the above object, a mask pattern designing method according to the present invention is a method for designing a mask pattern formed on a mask, the method using design data of a test pattern in which a part of the mask pattern is selected and / or changed. Creating certain test pattern data, creating a test mask on which the test pattern is formed, measuring the length of the test pattern formed on the test mask, and using the test pattern on the test mask Re-creating the test pattern data so as to match the length measurement result, transferring the test pattern on the test mask by a predetermined process including exposure, and fabricating a sample; and Measuring the length of the test pattern transferred to the test pattern, and recreating the test pattern data. Performing a first simulation using the data as input data, predicting a test pattern to be transferred by the predetermined process, measuring the length of the test pattern in the sample, and recreating the test pattern data. A process of creating a process model by performing fitting so that a result of the first simulation for predicting a test pattern to be transferred is within a predetermined error range; and inputting design data of the mask pattern as input data. As data, performing a second simulation using the process model, predicting a pattern in which the mask pattern is transferred by the predetermined process, and correcting the mask pattern under a plurality of conditions having different correction amounts, Enter the corrected mask pattern design data Performing the second simulation using the process model as a data, predicting a pattern in which the corrected mask pattern is transferred by the predetermined process, and transferring the corrected mask pattern from the result of the second simulation. A step of determining an optimum correction amount such that a pattern to be obtained is closest to the design data of the mask pattern; and a step of correcting the mask pattern with the optimum correction amount.
[0037]
This makes it possible to eliminate mask manufacturing errors from a process model used in a simulation for correcting a mask pattern such as OPC. Therefore, the transfer result of the mask pattern can be predicted with high accuracy by simulation, and the mask correction amount for obtaining a desired transfer result can be determined more accurately.
[0038]
In order to achieve the above object, a mask of the present invention is characterized in that a mask pattern designed by the above-described mask pattern designing method of the present invention is formed. This makes it possible to transfer a desired layout pattern with high precision in the lithography process.
[0039]
In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention includes the lithography step using the mask of the present invention. Thereby, for example, a desired fine pattern can be formed on a semiconductor device with high accuracy.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a process model creation method, a mask pattern design method, a mask, and a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In the present embodiment, a process model is created based on the length measurement results of a test pattern formed on a test mask, which is a test photomask, and the length measurement results of a test pattern transferred and formed on a sample wafer. .
[0041]
Conventionally, OPC is performed so that a desired layout pattern can be finally obtained on a device by using a process model created using an actual measurement result of a test pattern formed on a sample and design data of the test pattern. Was. On the other hand, in the present embodiment, a process created in consideration of a test mask manufacturing error using the actual measurement result of the test pattern formed on the sample and the length measurement result of the test pattern formed on the test mask. According to the model, OPC is performed on a photomask for actual device manufacture.
[0042]
In the present embodiment, an example in which a correction pattern is added by OPC to a mask pattern for forming a gate layer of a transistor will be described. The layout pattern of the gate layer mainly includes a line-shaped rectangle. Therefore, a process model is created using a line and space (L / S) pattern in which a plurality of rectangles are arranged in parallel as shown in FIG. In the line-and-space pattern, the line width W and / or the line end position E in the line longitudinal direction are to be simulated. In FIG. 1, the sum of the line width W and the line interval S is defined as a pitch P.
[0043]
FIG. 2 shows a flowchart of the process model creation method of the present embodiment. Hereinafter, each step of FIG. 2 will be described.
Step 1 (ST1)
The layout data (GDSII data) of the test pattern is created. The test pattern is a collection of simplified patterns that can represent layout patterns of various shapes and sizes existing in a design circuit of a semiconductor device. In creating a test pattern, a design rule that specifies a pattern permitted in design is considered. A test mask is manufactured using the created test pattern.
[0044]
Step 2 (ST2)
In step 1, the length of the test pattern formed on the test mask is measured. For example, SEM is used for the length measurement. The length measurement location of the pattern on the test mask matches the length measurement location of the test pattern processed on the sample wafer.
[0045]
Step 3 (ST3)
Using the length measurement result of the test pattern on the test mask obtained in step 2, layout data (GDSII data) of the test pattern to be input to the simulator is recreated.
[0046]
Step 4 (ST4)
Perform sample preparation by the current process. A sample refers to a wafer to which a test pattern has been transferred. First, a resist is applied on a wafer for producing a sample, and the resist is exposed through a test mask. The resist is developed to form a resist pattern to which the test pattern has been transferred. Next, the wafer is etched using the resist pattern as a mask, the test pattern is transferred to the wafer, and then the resist is removed.
[0047]
Step 5 (ST5)
In step 4, the length of the test pattern transferred to the sample is measured. For example, SEM is used for the length measurement.
[0048]
Step 6 (ST6)
Create a condition file to be input to the simulator. The items of the condition file include, for example, layout data (GDSII data) of the test pattern and coordinates and dimensions of the test pattern measured on the sample. The setting of the exposure apparatus such as NA, coherence factor σ, exposure wavelength λ, and zonal ratio ε are also included in the condition file.
[0049]
Step 7 (ST7)
Create a process model. Specifically, various input files created in step 6 are input to the simulator, and a process model, which is a function for calculating the dimensions of the test pattern (pattern formed on the sample by etching) transferred to the sample, is created. Output. The input file created in step 6 incorporates the GDSII data recreated in step 3 and the length measurement results on the sample obtained in step 5. In the present embodiment, this step is a first simulation.
[0050]
Step 8 (ST8)
Regarding the process model output in step 7, it is checked whether the difference (residual fitting) between the actual measurement result in step 5 and the simulation result by the created process model is within a specified value. Here, the specified value is a specification (target value) of the model fitting accuracy set in advance in consideration of manufacturing variations due to a process, the accuracy of a lithography simulator as an arithmetic unit, and the like.
[0051]
The specified value is set for each pattern type. For example, the fitting residue of the pattern edge position shift amount (EPE; Edge Placement Error) when the gate length is 250 nm is within ± 5 nm per side in the direction of the line width W (gate length direction) of the L / S pattern in FIG. Set.
[0052]
For the line end, another test pattern as shown in FIG. 3, for example, is used. The distance between the line ends indicated by the arrows in FIG. 3 is defined as a length measurement point. For example, the fitting residue between the line ends when the gate length is 250 nm is set within ± 50 nm. For the line-to-line end, a test pattern as shown in FIG. 4 is used, for example. A fitting residue is set with the line-to-line end indicated by an arrow in FIG.
[0053]
At present, various tools are available on the market that can execute simulations such as OPC using GDSII data such as layout patterns. Various input files including the re-created GDSII data and the measurement results of the samples are input to the simulator, which is such a model creation tool, and model fitting is performed for each pattern type.
[0054]
If the remaining fitting deviates from the specified value, the process returns to step 6 and corrects the input file of the simulator as appropriate. If the specified value is satisfied, the model fitting ends.
[0055]
By performing a simulation using the model function (process model) created as described above, the actual transfer result of the mask pattern for manufacturing a semiconductor device can be accurately calculated. When the created process model and original layout data (GDSII data) are input to the simulator, layout data to which an OPC pattern is added is obtained.
[0056]
In the present embodiment, a simulation using the process model created by the first simulation is referred to as a second simulation. Therefore, the above-described prediction of the actual transfer result of the mask pattern for manufacturing a semiconductor device and the OPC process include the second simulation. A commercially available simulator can be used for the second simulation.
[0057]
In the OPC process, a second simulation is performed using design data obtained by correcting the layout pattern as input data. The correction amount of the layout pattern is variously changed by the input data, and the correction amount when a desired transfer result (a pattern closest to the original design data) is obtained from the transfer results calculated by the second simulation. calculate. This is set as the optimum correction amount, and the OPC is optimized by correcting the layout pattern with the optimum correction amount.
[0058]
FIGS. 5 and 6 are schematic diagrams showing the mask pattern designing method of the present embodiment. FIG. 5 shows a process model creation step, and FIG. 6 shows an OPC step.
In the process model creation step shown in FIG. 5, the test pattern 2 formed on the test mask 1 in (a) is transferred to the sample wafer 3 in (c) by the transfer process in (b).
[0059]
On the other hand, the design data recreated from the length measurement result of the test mask 1 in (d) and the various setting files 4 are input to the first simulator 5 in (e). The first simulator 5 predicts the transfer result of (f). By combining the actual measurement result of the sample (c) and the simulation result of (f), a process model 6 including a mask manufacturing error is output (first simulation).
[0060]
In the OPC process shown in FIG. 6, the design data of (a) the mask pattern 7 for actual semiconductor device manufacturing is input to the first simulator 5. The first simulator 5 predicts the transfer result 8 of (b) using the process model 6 created in a series of steps shown in FIG. 5 (second simulation). By inputting the transfer result 8 of (b) to the second simulator 9 using the process model 6, the OPC is optimized, and the corrected mask pattern 10 of (c) is output.
[0061]
Next, a specific example of the content of processing performed inside the tool when a process model is created will be described. FIG. 7 is an enlarged view of a portion surrounded by a circle in FIG. 7A shows a pattern in the design data, B shows a measurement result of the test mask, and C shows a measurement result of the sample.
[0062]
It is assumed that the measurement result B on the mask is converted to the size on the wafer. For example, in the case of a reduction projection exposure apparatus, multiplying the measurement result of the test mask by the reduction ratio converts it to the size on the wafer. As shown in FIG. 7, the edges of the pattern A of the design data, the mask length measurement result B, and the sample length measurement result C often do not match.
[0063]
FIG. 8 is a further enlarged view of the part circled in FIG. In FIG. 8, the edge of a design pattern (A in FIG. 7) that is a shape desired to be obtained after etching on a wafer is denoted by x1. Also, the edge of the pattern (B in FIG. 7) obtained by converting the length measurement result on the mask into the size on the wafer is x2, and the edge of the pattern (C in FIG. 7) actually measured on the sample is x3.
[0064]
In FIG. 8, I (x3-x1) indicates the EPE in the conventional process model creation method, and II (x3-x2) indicates the EPE in the process model creation method of the present embodiment. Ideally, x1 and x2 match, but x1 and x2 often do not match due to process-specific variations during mask fabrication. The deviation between x1 and x2 causes distortion of the process model, which may be a factor of deteriorating model fitting accuracy.
[0065]
According to the conventional process model creation method, the edge x3 of the layout pattern actually measured in the sample is expressed as a function f of the edge x1 in the layout pattern of the design data. That is, there is a relationship represented by the following equation (4).
f (x1) = x3 (4)
[0066]
The process model f (x1) in the equation (4) includes an error in the mask manufacturing process. That is, even in an actual device manufacturing mask other than the test mask, the above model is established only when the error of x2 in the test mask is reproduced. Therefore, for example, even if the mask is manufactured so that the edge becomes x1 as the original design data, there is a contradiction that the correction accuracy in the OPC deteriorates.
[0067]
On the other hand, in the process model creation method of the present embodiment, the edge x3 of the pattern actually measured on the sample is represented as a function g of the edge x2 of the pattern actually measured on the mask. That is, there is a relationship represented by the following equation (5).
g (x2) = x3 (5)
This eliminates the effects of errors that occur in the mask manufacturing process.
[0068]
The model fitting accuracy in the present embodiment described above is shown. FIG. 9 shows a process formed by a conventional method with the gate length set to 250 nm and the EPE set to ± 5 nm in the direction of the line width W (gate length direction) of the L / S pattern in FIG. Shows the fitting accuracy of the model. On the other hand, FIG. 10 shows the fitting accuracy of the process model created according to the present embodiment.
[0069]
In FIGS. 9 and 10, a indicates the measurement result of the sample. B indicates a simulation result (a simulation result of the process, that is, a result of the first simulation). c indicates the fitting residue represented by the equation (3). The actual measurement result a and the simulation result b of the sample are represented by the left vertical axis (line width W (nm) in FIG. 1), and the fitting residue is represented by the right vertical axis.
[0070]
As shown in FIG. 9, according to the conventional method, the remaining fitting does not fall within ± 5 nm depending on the pitch. On the other hand, in FIG. 10, the fitting residue is within ± 5 nm regardless of the pitch. As can be seen by comparing FIGS. 9 and 10, according to the process model creation method of the present embodiment, the fitting residue can be reduced.
[0071]
According to the mask pattern correction method of the present embodiment, a simulation (second simulation) using the process model created by the above method is performed, and the layout pattern formed on the wafer is closest to the original design data. The mask correction amount is determined so as to be as follows. Therefore, a correction pattern is created by high-precision OPC.
[0072]
A mask pattern designed by the above-described mask pattern designing method of the present embodiment is formed on the mask of the present embodiment. This makes it possible to transfer a desired layout pattern with high precision in the lithography process.
Further, the method for manufacturing a semiconductor device of the present embodiment includes a photolithography step using the mask of the present embodiment. This makes it possible to form a desired fine pattern on a semiconductor device with high accuracy.
[0073]
Embodiments of the process model creation method, the mask pattern design method, the mask, and the semiconductor device manufacturing method of the present invention are not limited to the above description. For example, a process model created by the process model creation method of the present invention is used not only for a model-based OPC based on a simulation but also for a combination of a rule-based OPC that generates a correction pattern based on a rule and a model-based OPC. Is also possible.
[0074]
Also, the test pattern for correction between line ends shown in FIG. 3, the test pattern for correction between line and line ends shown in FIG. 4, or other test patterns are the same as those in the case of the above L / S pattern. A process model can be created in a similar procedure.
[0075]
Further, the mask of the present invention is not limited to a photomask such as a phase shift mask and a binary mask, and may be a mask for charged particle beam lithography such as electron beam lithography or ion beam lithography, or a mask for X-ray lithography. Good. Further, the process model creation method and the mask pattern design method of the present invention may be applied to the design of a mask pattern other than a photomask to perform pattern correction other than the OPC. In addition, various changes can be made without departing from the spirit of the present invention.
[0076]
【The invention's effect】
According to the process model creation method of the present invention, it is possible to eliminate errors caused by variations in a mask manufacturing process and to improve model fitting accuracy. According to the mask pattern designing method of the present invention, a simulation is performed using a process model in which a manufacturing error of a mask has been eliminated, and the transfer result of a mask pattern can be controlled with high accuracy.
[0077]
According to the mask of the present invention, a desired layout pattern can be transferred with high accuracy because the mask pattern is corrected by high-precision simulation. According to the method of manufacturing a semiconductor device of the present invention, a desired fine pattern can be formed with high accuracy by transferring a mask pattern corrected by high-precision simulation.
[Brief description of the drawings]
FIG. 1 is a diagram showing an L / S pattern according to an embodiment of a process model creation method of the present invention.
FIG. 2 is a flowchart showing a process model creation method according to the present invention.
FIG. 3 is a diagram showing an example of a test pattern to which the process model creation method of the present invention can be applied.
FIG. 4 is a diagram showing another example of a test pattern to which the process model creation method of the present invention can be applied.
FIG. 5 is a schematic view showing a process model creating step of the mask pattern designing method of the present invention.
FIG. 6 is a schematic view showing an OPC step of the mask pattern designing method of the present invention.
FIG. 7 is an enlarged view of a part of FIG. 1;
FIG. 8 is an enlarged view of a part of FIG. 7;
FIG. 9 is a comparative example of the model fitting accuracy of the process model creating method according to the embodiment of the present invention, and is a diagram showing the model fitting accuracy of the conventional process model creating method.
FIG. 10 is a diagram showing model fitting accuracy of the process model creation method according to the embodiment of the present invention.
FIG. 11 is a flowchart showing a conventional process model creation method.
[Explanation of symbols]
W: line width, E: line end, P: pitch, 1 ... test mask, 2 ... test pattern, 3 ... wafer, 4 ... file, 5 ... first simulator, 6 ... process model, 7 ... device manufacturing Mask pattern, 8: transfer result of mask pattern 7, 9: second simulator, 10: corrected mask pattern, A: pattern using design data, B: measurement result using mask, C: sample As a result of length measurement, I: EPE by the conventional method, II: EPE by the method of the present invention.

Claims (8)

A method for creating a simulation process model for predicting a pattern to be transferred by a predetermined process including exposure, wherein the mask pattern design data is input data,
Creating test pattern data that is design data of a test pattern in which a part of the mask pattern is selected and / or changed;
Producing a test mask on which the test pattern is formed,
Measuring the length of the test pattern formed on the test mask,
Re-creating the test pattern data so as to match the measurement result of the test pattern in the test mask,
Transferring the test pattern on the test mask by the predetermined process to produce a sample;
Measuring the length of the test pattern transferred to the sample,
Performing the simulation using the re-created test pattern data as input data, and predicting a test pattern to be transferred by the predetermined process;
Fitting is performed so that the length measurement result of the test pattern in the sample and the result of the simulation for predicting a test pattern to be transferred using the recreated test pattern data as input data are within a predetermined error range. And creating a process model by performing the following. The predetermined process, a step of exposing a resist through the mask on which the mask pattern is formed or the test mask on which the test pattern is formed,
Developing the resist;
Processing the underlayer of the resist by etching using the resist as a mask,
2. The method according to claim 1, further comprising the step of removing the resist. A method for designing a mask pattern formed on a mask,
Creating test pattern data that is design data of a test pattern in which a part of the mask pattern is selected and / or changed;
Producing a test mask on which the test pattern is formed,
Measuring the length of the test pattern formed on the test mask,
Re-creating the test pattern data so as to match the measurement result of the test pattern in the test mask,
Transferring the test pattern on the test mask by a predetermined process including exposure, to produce a sample,
Measuring the length of the test pattern transferred to the sample,
Performing a first simulation using the re-created test pattern data as input data, and predicting a test pattern to be transferred by the predetermined process;
The length measurement result of the test pattern in the sample and the result of the first simulation for predicting the transferred test pattern using the re-created test pattern data as input data are within a predetermined error range. To create a process model by performing fitting as follows,
Using the design data of the mask pattern as input data, performing a second simulation using the process model, and predicting a pattern to which the mask pattern is transferred by the predetermined process;
The second simulation using the process model is performed using the design data of the corrected mask pattern as input data to correct the mask pattern under a plurality of conditions where the correction amounts are different from each other, and the corrected mask pattern is Estimating a pattern to be transferred by the predetermined process;
Determining an optimal correction amount such that the transferred pattern is closest to the design data of the mask pattern from the result of the second simulation;
Correcting the mask pattern with the optimum correction amount. The predetermined process, a step of exposing a resist through the mask on which the mask pattern is formed or the test mask on which the test pattern is formed,
Developing the resist;
Processing the underlayer of the resist by etching using the resist as a mask,
4. The method according to claim 3, further comprising the step of removing the resist. A mask in which a light or charged particle beam transmission part is formed in a predetermined mask pattern,
A step of creating test pattern data that is design data of a test pattern obtained by selecting and / or changing a part of the mask pattern;
Producing a test mask on which the test pattern is formed,
Measuring the length of the test pattern formed on the test mask,
Re-creating the test pattern data so as to match the measurement result of the test pattern in the test mask,
Transferring the test pattern on the test mask by a predetermined process including exposure, to produce a sample,
Measuring the length of the test pattern transferred to the sample,
Performing a first simulation using the re-created test pattern data as input data, and predicting a test pattern to be transferred by the predetermined process;
The length measurement result of the test pattern in the sample and the result of the first simulation for predicting the transferred test pattern using the re-created test pattern data as input data are within a predetermined error range. To create a process model by performing fitting as follows,
Using the design data of the mask pattern as input data, performing a second simulation using the process model, and predicting a pattern to which the mask pattern is transferred by the predetermined process;
The second simulation using the process model is performed using the design data of the corrected mask pattern as input data to correct the mask pattern under a plurality of conditions where the correction amounts are different from each other, and the corrected mask pattern is Estimating a pattern to be transferred by the predetermined process;
Determining an optimal correction amount such that the transferred pattern is closest to the design data of the mask pattern from the result of the second simulation;
Correcting the mask pattern with the optimum correction amount. The mask according to claim 5, wherein the mask is a photomask that transmits light through the transmission part. 7. The mask according to claim 6, wherein the correction of the mask pattern includes an optical proximity effect correction. A method for manufacturing a semiconductor device, comprising a step of exposing a resist through a mask in which a transmission part of light or a charged particle beam is formed in a predetermined mask pattern,
A step of creating test pattern data that is design data of a test pattern obtained by selecting and / or changing a part of the mask pattern;
Producing a test mask on which the test pattern is formed,
Measuring the length of the test pattern formed on the test mask,
Re-creating the test pattern data so as to match the measurement result of the test pattern in the test mask,
Transferring the test pattern on the test mask by a predetermined process including exposure, to produce a sample,
Measuring the length of the test pattern transferred to the sample,
Performing a first simulation using the re-created test pattern data as input data, and predicting a test pattern to be transferred by the predetermined process;
The length measurement result of the test pattern in the sample and the result of the first simulation for predicting the transferred test pattern using the re-created test pattern data as input data are within a predetermined error range. To create a process model by performing fitting as follows,
Using the design data of the mask pattern as input data, performing a second simulation using the process model, and predicting a pattern to which the mask pattern is transferred by the predetermined process;
The second simulation using the process model is performed using the design data of the corrected mask pattern as input data to correct the mask pattern under a plurality of conditions where the correction amounts are different from each other, and the corrected mask pattern is Estimating a pattern to be transferred by the predetermined process;
Determining an optimal correction amount such that the transferred pattern is closest to the design data of the mask pattern from the result of the second simulation;
Correcting the mask pattern with the optimum correction amount.

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