JPH0777221B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The pinch-off resistance of the FET is improved by utilizing the electric charge induced in GaAs by the stress generated by the difference in thermal expansion coefficient between GaAs and the silicon nitride film (Si ₃ N ₄ film). Improve.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a GaAs FET having an improved pinch-off breakdown voltage.

[Conventional technology]

A conventional method of manufacturing a compound semiconductor device, for example, a GaAs FET will be described with reference to FIG. 2. First, an insulating film is formed on the surface of a GaAs wafer 11 including a GaAs active layer 12 and a GaAs buffer layer 13.
An oxide film (first SiO ₂ film) 14 is grown as shown in FIG. 2 (a).

Next, as shown in FIG. 2 (b), a resist 15 is applied on the first SiO ₂ film 14 and patterned to form a resist.
The first SiO ₂ film 14 is overetched by a wet chemical process using 15 as a mask to leave the first SiO ₂ film 14 having a width slightly smaller than the width of the resist 15. 2 (b) and below, the GaAs active layer 12 and the GaAs buffer layer 13 are omitted and only the GaAs wafer 11 is shown.

Then, as shown in FIG. 2 (c), an ohmic electrode material [eg, gold-germanium (AuGe)] is vapor-deposited on the entire surface,
The resist 15 and the ohmic electrode material on the resist 15 are removed by the lift-off method to leave the ohmic electrodes, that is, the source electrode 16 and the drain electrode 17. As described with reference to FIG. 2 (b), since the etching of the first SiO ₂ film is over-etched, A and A are shown between the remaining first SiO ₂ film 14 and the source and drain electrodes. A gap portion indicated by'is generated, and the active layer of the GaAs wafer 11 is exposed at this portion.

Next, in order to fill the above-mentioned gap and insulate the exposed surface of the GaAs wafer, a second layer is formed on the entire surface as shown in FIG. 2 (d).
The SiO ₂ film 18 is deposited.

Next, as shown in FIG. 2 (e), a resist 19 is applied on the entire surface and patterned to open a gate electrode window 20.

Then, as shown in FIG. 2F, the second SiO ₂ film 18 and the first SiO ₂ film 14 are dry-etched using the resist 19 as a mask. After that, overetching is performed by wet etching, and the surface of the GaAs wafer 11 is slightly etched.

Next, as shown in FIG. 2 (g), a gate electrode material such as
Al is vapor-deposited, the resist 19 and Al on the resist 19 are removed by a lift-off method, and the gate electrode 21 is left. In the GaAs FET manufactured in this manner, the source electrode 16 is grounded, and the negative voltage is applied to the gate electrode 21 and the positive voltage is applied to the drain electrode 17.

[Problems to be solved by the invention]

When the pinch-off withstand voltage (drain bias value when the device burns out when the drain bias is increased in the gate pinch-off state) of the FET having the above structure is measured, the gate length is about 1 μm and the gate width is about 100 μm. It is about 30V. This value is still insufficient when considering large-amplitude operation of the FET, and improvement in pinch-off breakdown voltage is required.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing an FET in which the pinch breakdown voltage is improved.

[Means for solving problems]

The above problems include the step of forming a first insulating film made of silicon oxide on the GaAs active layer, the step of forming a resist film having openings in the source and drain electrode formation regions on the first insulating film, Etching using the resist film as a mask to side-etch the first insulating film on the source and drain electrode formation regions and part of the first insulating film under the resist film to expose the GaAs active layer; A step of forming source and drain electrodes on the exposed GaAs active layer separated from the first insulating film using the eave-shaped register film as a mask by the side etching, and the source electrode and the drain. The first insulating film between the electrodes is selectively etched to form an eave-shaped gate forming window, and an etchant is injected from the window, In the method of manufacturing a semiconductor device, comprising: forming a recess in the GaAs active layer; and selectively forming a gate electrode on the recess using the gate forming window as a mask, the source and drain electrodes A step of forming a second insulating film made of silicon nitride on the surface of the GaAs active layer exposed in the space between the first insulating film and the first insulating film, and using the second insulating film as the outermost layer in the space. This is solved by providing a method for manufacturing a semiconductor device, which is characterized by being included.

[Action]

It is understood that one of the factors that determines the pinch-off breakdown voltage is electrolytic concentration in the gap portion A, with reference to FIG. Therefore, it was judged that the relaxation of this electrolytic concentration would lead to an improvement in the pinch-off breakdown voltage, and a silicon nitride film was used instead of the conventional second SiO ₂ film.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 2 (g) again, when a drain bias is applied, electrolysis occurs between the end of the drain electrode 17 and the gate electrode 21 in the direction indicated by the arrow I in the figure.

Here, the relationship between the first SiO ₂ film 14 and the second SiO ₂ film 18 is an enlarged view of the gap portion A in FIG. 2 (g).
The second SiO 2 filled in the gap is described with reference to
_A compressive force acts on the ₂ film in the direction indicated by the arrow I, and this compressive force generates + polarized charge on the surface of the GaAs active layer immediately below the 2nd SiO ₂ film, and this polarized charge is shown in FIG. ), Electrolysis is generated in the direction schematically indicated by the arrow I ', and as a result, the arrow I'
As indicated by I and I ′, the concentration of electrolysis at the drain electrode end increases and the pinch-off breakdown voltage decreases.

In the present invention, the portion A is filled with silicon nitride instead of the conventional second SiO ₂ film, and at the contact portion between silicon nitride and GaAs, the stress of silicon nitride in the opposite direction to SiO ₂ causes Negative polarization charge, marked with a mark, is induced in GaAs and the resulting electrolysis is directed from GaAs to the drain electrode edge. On the other hand, the electric field due to the drain bias is
As described above, since it is directed from the drain electrode end toward the GaAs side, it is understood that the electric field generated by the polarization charge alleviates the electric field concentration at the drain electrode end.

Therefore, in the method of the present invention, the process described with reference to FIG. 2 is carried out, but instead of the deposition of the second SiO ₂ film 18 described with reference to FIG. Deposit. The growth of silicon nitride is carried out by conventional techniques using SiH ₄
And NH ₃ are reacted as shown in the following formula.

The growth temperature of 3SiH ₄ + 4NH ₃ → Si ₃ H ₄ + 12H ₂ is about 300 ° C. In one embodiment of the present invention,
1 The SiO ₂ film 14 has grown to a film thickness of 1000 Å to some extent.

The following steps are similar to the conventional example, and the difference from the conventional example is
2 The only difference is that a silicon nitride film 22 is grown instead of the SiO ₂ film 18.

When the inventor measured the pinch-off breakdown voltage in the embodiment shown in FIG. 1, a value of about 35 V was obtained, which was 5 V higher than the conventional example. According to the present invention, the FET has a higher breakdown voltage. And large-amplitude operation became possible, and it became possible to take out a large amount of power from the FET.

〔The invention's effect〕

As described above, according to the present invention, the contact between the silicon nitride film and the GaAs layer causes the stress of the silicon nitride film to cause the GaAs
The effect that the polarization charge induced inside relaxes the electric field concentration and enables the large-amplitude operation of the FET is obtained.

[Brief description of drawings]

1 is a sectional view of an embodiment of the present invention, and FIGS. 2A to 2H are sectional views of a conventional example. In FIGS. 1 and 2, 11 is a GaAs wafer, 12 is a GaAs active layer, 13 is a GaAs buffer layer, 14 is a first SiO ₂ film, 15 is a resist, 16 is a source electrode, 17 is a drain electrode, and 18 is The second SiO ₂ film, 19 is a resist, 20 is a gate electrode window, 21 is a gate electrode, and 22 is a silicon nitride film.

Claims (1)

[Claims] 1. A first GaAs active layer comprising silicon oxide.
Forming an insulating film; forming a resist film having openings in the source and drain electrode forming regions on the first insulating film; and etching using the resist film as a mask to form the source and drain electrode forming regions. Of the first insulating film and a part of the first insulating film below the resist film to expose the GaAs active layer, and using the resist film formed into an eave shape by the side etching as a mask. A step of forming source and drain electrodes on the exposed GaAs active layer so as to be separated from the first insulating film, and selectively etching the first insulating film between the source electrode and the drain electrode. , Forming an eave-shaped gate forming window, and injecting an etchant through the window,
A method of manufacturing a semiconductor device, comprising: forming a recess in a GaAs active layer; and selectively forming a gate electrode on the recess using the gate formation window as a mask, wherein the source and drain electrodes are A second insulating film made of silicon nitride is formed on the surface of the GaAs active layer exposed in the space between the first insulating film and the space, and in the space,
A method of manufacturing a semiconductor device, comprising the step of using the second insulating film as an outermost layer.