JPH0772508A - Thin film transistor panel - Google Patents

Abstract

PURPOSE:To prevent pit erosion in a terminal part of an upper layer line due to a defect of a protection insulating film by dividing the terminal part of at least the upper layer line between a lower layer line and the upper layer line into plural areas which succeed partially to one another. CONSTITUTION:The terminal part 32a of the data line 32 wired on a gate insulating film 12 and an inter-layer insulating film 23 formed on a substrate is equally divided into two areas A1 and A2 by a slit 33 which is provided in the center of the terminal part and extends in the terminal length direction, and the divided areas Al and A2 are connected to each other outside the end part of the slit 33. Thus, the terminal part 32a of the data line 32 is divided into the two areas A1 and A2 which succeed partially to each other, so the widths W1 and W2 of the divided areas A1 and A2 of the terminal part 32a are small and, therefore, even when the protection insulating film 24 is formed by heat formation which gives excellent film quality, a projection such hillock and a whisker is not generated at the terminal part 32a at the time of the film formation.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a thin film transistor panel.

[0002]

2. Description of the Related Art A thin film transistor (TFT) is formed on a substrate.
A thin film transistor panel (hereinafter referred to as a TFT panel) in which an address line and a data line for supplying a gate signal and a data signal to the thin film transistor are formed is used, for example, in an active matrix liquid crystal display element.

FIG. 12 is an equivalent circuit plan view of a conventional TFT panel used for an active matrix liquid crystal display element. This TFT panel is formed by a plurality of transparent insulating substrates 1 made of glass or the like. Thin film transistors (hereinafter, referred to as TFTs) 10 are formed in an array in the row direction (horizontal direction) and the column direction (vertical direction), and the TF of each row is formed.
An address line 21 for supplying a gate signal to T10 and a data line 22 for supplying a data signal to the TFT 10 in each column are formed, and a pixel electrode 20 is formed corresponding to each TFT 10.

FIG. 13 shows one TFT of the above TFT panel.
FIG. 3 is a cross-sectional view of a portion of the TFT 10, in which the TFT 10 includes a gate electrode portion 11 formed on a substrate 1 and SiN formed thereon
A gate insulating film 12 made of (silicon nitride), and i made of a-Si (amorphous silicon) formed on the gate insulating film 12 so as to face the gate electrode 11.
The i-type semiconductor film 13 and a source electrode 15 and a drain electrode 16 formed on the i-type semiconductor film 13 with an n-type semiconductor film 14 made of a-Si doped with impurities interposed therebetween. Reference numeral 17 is a blocking film made of Si 2 N provided on the channel region of the i-type semiconductor film 13.

This TFT 10 is called an inverted stagger structure, and the TFT 10 has a reverse stagger structure.
In the T panel, the address line 21 is wired on the substrate 1, and the gate electrode 11 of the TFT 10 is integrally formed on the address line 21. The address line 21 and the gate electrode 11 are formed as thin as possible in order to reduce the step between the gate line 11 and the surface of the substrate 1, and the surface of the address line 21 and the gate electrode 11 is formed on the gate insulating film 12. In order to make up for the withstand voltage of the above, anodization is performed except for the terminal portion 21a. In FIG.
a is an oxide film formed by the anodic oxidation.

The gate insulating film 12 of the TFT 10 is also used.
Are formed over substantially the entire surface of the substrate 1, and the address lines 21 are covered with the gate insulating film 12. The pixel electrode (transparent electrode) 20 is the TFT 1
It is formed on the gate insulating film (transparent film) 12 at the side of 0, and the pixel electrode 20 is connected to the source electrode 15 of the TFT 10 at one edge portion thereof.

Further, the TFT 10 is covered with an interlayer insulating film 23 made of Si 3 N 4. The interlayer insulating film 23 is formed from the TFT forming portion to the data line wiring portion, the data line 22 is laid on the interlayer insulating film 23, and the TFT 10 is formed in the contact hole 23a provided in the interlayer insulating film 23. Drain electrode 1
Connected to 6.

The data line 22 is connected to Si N
Is covered with a protective insulating film 24, and its terminal portion 22a is exposed by forming an opening in the protective insulating film 24.

FIG. 14 is a plan view of a data line terminal portion in a conventional TFT panel, and FIG. 15 is a sectional view taken along the line XV-XV in FIG. In order to prevent corrosion from the peripheral portion of the line terminal portion 22a, the terminal portion 22a is formed in such a size as to be exposed except for the peripheral portion.

In other words, considering the case where the entire terminal portion 22a is exposed, the surface of the terminal portion 22a is covered by connecting a drive circuit to the terminal portion 22a, so that the surface of the terminal portion 22a from the front side is covered. Corrosion does not occur,
Since the peripheral edge portion of the terminal portion 22a is exposed, moisture in the air causes the terminal portion 22a to corrode from the peripheral edge portion over a long period of time, and due to the progress of this corrosion, connection with the drive circuit is finally achieved. Generate a defect.

Therefore, in this TFT panel, the terminal portion exposure opening 24a provided in the protective insulating film 24 is formed to have the above-described size, and the peripheral edge portion of the terminal portion 22a is protected.
4 to prevent corrosion from the peripheral portion of the terminal portion 22a.

In this TFT panel, as shown in FIGS. 14 and 15, the interlayer insulating film 23 is not formed in the formation portion of the data line terminal portion 22a, and the terminal portion 22a of the data line 22 is gated. It is formed on the insulating film 12.

The protective insulating film 24 is generally formed in a grid pattern in which openings are formed in portions corresponding to the respective pixel electrodes 20 over substantially the entire surface of the substrate 1, and not only the data lines 22 are formed. It also covers the formation part of the TFT 10 and the address line 21.

The terminal portion 21 of the address line 21
Although not shown, a is exposed by forming an opening in the gate insulating film 12 and the protective insulating film 24. Either or both of the terminal portion exposing openings provided in the gate insulating film 12 and the protective insulating film 24 are provided in order to prevent corrosion from the peripheral portion of the terminal portion 21a.
It is formed in such a size that a is exposed except for the peripheral portion thereof. Therefore, the terminal portion 21a of the address line 21 is formed.
Also, the peripheral portion thereof is covered with at least one of the gate insulating film 12 and the protective insulating film 24.

By the way, in the above TFT panel,
In order to reduce the line resistance of the address line 21 and the data line 22, these lines 21 and 22 are connected to a low resistance Al (aluminum) -based metal such as Al to Ti.
It is formed of an Al-based alloy containing a minute amount (several weight%) of a refractory metal such as (titanium) or Ta (tantalum).

Of the address line 21 and the data line 22, the lower layer line, that is, the address line 21 wired on the substrate 1 is the substrate 1 as described above.
Although it is thinly formed in order to reduce the step difference with the surface, the upper line, that is, the data line 22 provided on the interlayer insulating film 23 is formed to be thick to some extent in order to further reduce the line resistance.

[0017]

However, the above-mentioned conventional T
The FT panel has the terminal portion 22a of the data line 22 when the protective insulating film 24 is formed at the end of the manufacturing process.
There is a problem in that protrusions P such as hillocks and whiskers are generated on the surface of the as shown in FIG.

This is because the surface of an Al-based metal film is roughened when heated to several hundreds of degrees Celsius, and the formation of the protective insulating film 24 generally does not change the characteristics of the semiconductor film.
The plasma CVD apparatus is used at a substrate temperature of 220 to 250 ° C. When the protective insulating film 24 is formed,
The protrusion P is generated on the surface of the terminal portion 22a of the data line 22 made of the l-based metal film.

The occurrence of the projection P is due to a relaxation phenomenon of internal stress generated in the metal film by heating, that is, a phenomenon in which the internal stress generated in the metal film concentrates on a weak portion of the metal film and the surface of this portion rises. It is thought that this protrusion P
Is mainly generated near the edge of the metal film.

The larger the film thickness and width of the metal film, the larger the internal stress generated in the metal film by heating. Therefore, the protrusion P does not occur in the line portion of the data line 22 having a very small width. However, since the width W of the terminal portion 22a is as wide as 100 to 120 μm, the protrusion P is generated on the terminal portion 22a.

When the protrusion P is formed on the terminal portion 22a, the formed protective insulating film 24 is pierced by the protrusion P as shown in FIG. 15, and a defect is generated in this portion.
In a long period of time, the terminal portion 22a is corroded from the defective portion of the protective insulating film 24, and due to the progress of this pitting corrosion, a connection failure with the drive circuit is finally generated.

The gate insulating film 12, the blocking insulating film 17, and the interlayer insulating film 23 are the protective insulating film 24.
Similarly, the film is formed by the plasma CVD apparatus at the above-mentioned substrate temperature (220 to 250 ° C.), and therefore,
The address line 21 wired on the substrate 1 is heated each time the insulating films 12, 17, 23 and the protective insulating film 24 are formed, and the film thickness of the address line 21 is different from that of the surface of the substrate 1. It is made as thin as possible in order to reduce the step difference. In the conventional TFT panel, the terminal portion 21a of the address line 21 has the same thickness as the line portion. Does not occur.

Therefore, in the conventional TFT panel, the above-mentioned pitting corrosion does not occur in the terminal portion 21a of the address line 21, but the pitting corrosion of the terminal portion 22a of the data line 22 progresses and the connection with the drive circuit is defective. When this occurs, the TFT panel does not operate normally with respect to the applied data signal, and the life of the liquid crystal display element ends.

Although the TFT panel has the reverse stagger structure of the TFT 10, the pitting corrosion of the terminal portion due to the generation of the above-mentioned protrusion also occurs in the TFT panel having the other structure.

That is, the structure of the TFT includes a stagger structure, a coplanar structure, a reverse coplanar structure, etc. in addition to the reverse stagger structure. In the TFT panel having the stagger structure or the coplanar structure as the TFT, a data signal is supplied to the TFT panel. The data line to be supplied is wired on the substrate, and the address line for supplying the gate signal is wired on the insulating film formed on the substrate. Further, in the TFT panel in which the TFT has an inverse coplanar structure, the address lines are wired on the substrate and the data lines are wired on the insulating film formed on the substrate, as in the above TFT panel.

Conventionally, in these TFT panels as well, the lower layer line wired on the substrate is made as thin as possible in order to reduce the step difference from the substrate surface, and the terminal portion is also made to have the same thickness. Although the above-mentioned protrusion does not occur in the terminal portion of the lower layer line, the upper layer line is formed to be thick to some extent, so that a protrusion occurs in the terminal portion of the upper layer line when the protective insulating film is formed, and this protrusion causes the protective insulating film Defects occur and pitting corrosion occurs in the terminal portion of the upper layer line.

For this reason, conventionally, it has been considered that the protective insulating film is formed by the plasma CVD apparatus with almost no heating so that no protrusion is generated at the terminal portion of the upper layer line when the protective insulating film is formed. However, the insulating film thus formed has a problem that the film quality is rough and the reliability as a protective insulating film is poor.

An object of the present invention is to provide a TFT in which no protrusion is generated in the terminal portion of the upper layer line even when the protective insulating film is formed by heating for obtaining good film quality.
To provide a panel.

[0029]

According to the present invention, a thin film transistor is formed on an insulating substrate, a lower layer line is provided on the substrate to supply a gate signal or a data signal to the thin film transistor, and the lower line is formed on the substrate. And an upper layer line for supplying a data signal or a gate signal to the thin film transistor, which is wired on the insulating film,
In a thin film transistor panel in which the upper layer line is covered with a protective insulating film and an opening is formed in the protective insulating film to expose the terminal portion of the upper layer line except its peripheral portion, at least the upper layer of the lower layer line and the upper layer line. The terminal of the line is divided into a plurality of regions that are locally continuous with each other.

In order to obtain a protective insulating film having a good film quality, it is desirable to form this protective insulating film at 220 to 250 ° C. Further, in order to reduce the line resistance of the upper layer line, this upper layer line is required. And the film thickness of the terminal part are 2
It is desirable to set the thickness to 00 to 350 nm, but in that case, the width of each divided region of the terminal portion may be set to 50 to 40 μm or less.

Further, in the example of the terminal portion of the upper layer line, the terminal portion is divided by a slit provided in the center thereof along the terminal length direction, and the respective divided regions are continuous with each other outside the end portion of the slit, Alternatively, it is divided into a wide region at the center and a narrow region at the periphery by a slit having a discontinuous portion at least partially provided in a frame shape along the peripheral edge of the terminal portion, and each divided region is a non-continuous portion of the slit. They may be continuous with each other in the continuous portion.

[0032]

According to the TFT panel of the present invention, since the terminal portion of the upper layer line is locally divided into a plurality of regions which are continuous with each other, the width of each divided region of the terminal portion is small and therefore the protection is provided. Even if the insulating film is formed by heating the film to obtain a good film quality, no protrusion is generated at the terminal portion of the upper layer line during the film formation.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a TFT panel used for an active matrix liquid crystal display device will be described below with reference to the drawings.

1 to 9 show a first embodiment of the present invention, FIG. 1 is a plan view of a data line terminal portion of a TFT panel, and FIG. 2 is a sectional view taken along the line II--II of FIG. , FIG. 3 is FIG.
FIG. 3 is a sectional view taken along line III-III of FIG. In addition, FIG. 4 shows TF
A plan view of the address line terminal portion of the T panel, FIG.
6 is a sectional view taken along line V-V in FIG. 6, and FIG. 6 is a sectional view taken along line VI-VI in FIG. The TFT panel of this embodiment has a T
The FT has an inverted staggered structure, and since this TFT is the same as that shown in FIG. 13, its description is omitted.

First, the data line terminal portion shown in FIGS. 1 to 3 will be described. 1 to 3, parts corresponding to those of the conventional TFT panel shown in FIGS. 14 and 15 are designated by the same reference numerals, and overlapping description will be omitted.

In the TFT panel of this embodiment, the terminal portion 32a of the data line 32 wired on the gate insulating film 12 and the interlayer insulating film 23 formed on the substrate 1 is provided in the center in the terminal length direction. Along the slit 33, it is equally divided into two areas A1 and A2, and these divided areas A1 and A2 are divided.
2 has a shape in which they are continuous with each other outside the end of the slit 33.

In this embodiment, the slit 33 is used.
One end of which is opened to the outer end edge of the terminal portion 32a (the edge portion on the opposite side to the edge portion on the side connected to the line portion) to form a length slightly shorter than the length of the terminal portion 32a, The divided areas A1 and A2 are locally continuous at the edge of the terminal portion 32a on the side of the line portion.

Further, the data line 32 has a T on Al.
Al containing several wt% of high melting point metal such as i or Ta
It is made of an Al-based metal film such as a system alloy, the line portion is formed to have an extremely small width (about 20 to 40 .mu.m), and the terminal portion 32a is a wide portion having a total width W0 of 100 to 120 .mu.m.

The data line 32 has a protective insulating film 2 made of SiN or the like, as in the conventional TFT panel.
4 and is covered with the data line 32 terminal portion 32a.
Are exposed by providing an opening 24a in the protective insulating film 24. The opening 24a is formed in the terminal portion 3
The terminal portion 32a is formed to have a size such that the peripheral portion thereof is exposed except for the peripheral portion thereof.
It is covered with and is protected from corrosion from the periphery.

In this TFT panel, since the terminal portion 32a of the data line 32 is locally divided into two areas A1 and A2 which are continuous with each other, the divided areas A1 and A2 of the terminal portion 32a are divided. The widths W1 and W2 are small. Therefore, even if the protective insulating film 24 is formed by heating to obtain good film quality, protrusions such as hillocks and whiskers are generated on the terminal portion 32a during the film formation. There is no.

The divided areas A1 and A2 of the terminal portion 32a
The widths W1 and W2 may be selected as follows according to the film thickness of the terminal portion 32a and the film formation temperature (substrate temperature) of the protective insulating film 24.

That is, FIGS. 7 to 9 show the results of examining the generation of the above-mentioned protrusions by heating a line formed of a metal film made of an Al-based alloy containing Al or Ti in an amount of about 5% by weight. Shows.

In FIG. 7, the line width of the metal film is 50 μm.
And the relationship between the heating temperature and the number of generated protrusions when the film thickness is 350 nm. In this case, 220
No protrusions are generated at a heating temperature of ℃ or below, and the heating temperature is 22
When the temperature exceeds 0 ° C, protrusions are generated, and the number of these protrusions increases with increasing heating temperature.

FIG. 8 shows the relationship between the film thickness of the metal film and the number of generated protrusions when the heating temperature is 250 ° C. and the line width of the metal film is 50 μm. In this case, the film thickness is Two
When the thickness is less than 00 nm, no protrusions are generated, and when the thickness exceeds 200 nm, protrusions are generated, and the number of these protrusions increases as the film thickness increases.

FIG. 9 shows the relationship between the line width of the metal film and the number of generated protrusions when the heating temperature is 250 ° C. and the film thickness of the metal film is 350 nm. In this case, the line width is If the thickness is 40 μm or less, no protrusion is generated and the line width is 40
If it exceeds μm, protrusions are generated, and the number of these protrusions increases as the line width increases.

On the other hand, when the protective insulating film 24 made of SiN or the like is formed by the plasma CVD apparatus, in order to obtain an insulating film with good film quality, this protective insulating film 24 is provided with 220-2.
It is desirable to form the film at 50 ° C. Further, in order to reduce the line resistance of the data line 32, the film thickness of the data line 32 and its terminal portion 32 a is set to 200 to 350.
It is desirable to increase the thickness to some nm.

This condition is satisfied, and moreover, the protective insulating film 24
In order to prevent the protrusions from being formed on the terminal portion 32a during the film formation, the widths W1 and W2 of the divided areas A1 and A2 of the terminal portion 32a may be set to 50 to 40 .mu.m or less.

That is, for example, when the film thickness of the data line 32 and its terminal portion 32a is 350 nm and the protective insulating film 24 is formed at 220 ° C., the relationship between the heating temperature and the number of protrusions shown in FIG. 7 is obtained. If the line width is 50 μm or less, no protrusion is generated. In this case, the widths W1 and W2 of the divided areas A1 and A2 of the terminal portion 32a are set to 50 μm.
It may be set to m or less.

The thickness of the data line 32 and its terminal portion 32a is set to 200 nm, and the protective insulating film 24 is set to 2 nm.
The same applies to the case of forming a film at 50 ° C., and in this case as well, FIG.
As shown in the relationship between the film thickness and the number of protrusions, the line width is 50
If the thickness is less than or equal to μm, no protrusions will be generated.
The widths W1 and W2 of the divided areas A1 and A2 of 2a are 50 μm.
You can do the following:

The thickness of the data line 32 and its terminal portion 32a is 350 nm, and the protective insulating film 24 is 25
When the film is formed at 0 ° C., as shown in the relationship between the line width and the number of protrusions shown in FIG. 9, no protrusion occurs if the line width is 40 μm or less. The widths W1 and W2 of the regions A1 and A2 may be set to 40 μm or less.

The thickness of the data line 32 and its terminal portion 32a is 200 nm, and the protective insulating film 24 is 22.
When forming a film at 0 ° C., each divided area A1 of the terminal portion 32a
, A2 have widths W1 and W2 slightly larger than 50 μm, the protrusions hardly occur. However, in this case as well, if the widths W1 and W2 of the divided regions A1 and A2 are 50 μm or less, the protrusions can be more completely generated. It can be lost.

Further, according to this TFT panel, even if the protective insulating film 24 is formed by heating film formation that can obtain good film quality, the terminal portion 32 of the data line 32 is formed at the time of film formation.
Since no protrusions are generated in a, unlike the conventional TFT panel, the protrusions are pierced by the formed protective insulating film protrusions to cause defects, and holes are formed from defective portions of the protective insulating film within a long period of time. There is no possibility that the terminal portion of the data line will be corroded by the corrosion and a connection failure with the drive circuit will not occur.

Next, the address line terminal portion shown in FIGS. 4 to 6 will be described. In this embodiment, the terminal portion 31A of the address line 31 wired on the substrate 1 has a small connection resistance with the drive circuit. In order to achieve this, on the lower layer terminal film 31a formed integrally with the address line 31, the upper layer terminal film 31b made of the same metal film as the data line 32 is formed.
Has a two-layer film structure.

The upper terminal film 31b has an opening 1 for exposing the lower terminal film 31a except the peripheral portion of the gate insulating film 12 formed to cover the address line 31.
2a is formed, and then a metal film (200
The Al-based metal film having a thickness of up to 350 nm is formed by a sputtering apparatus or the like, and the metal film is patterned by photolithography. The upper terminal film 31b is a gate insulating film. Since it is formed in the opening 12a provided in 12, the outer shape thereof is the same as that of the lower terminal film 3 described above.
It is slightly smaller than the outer shape of 1a.

The address line 31 is made of Al containing Al by several wt% of a high melting point metal such as Ti or Ta.
It is made of an Al-based metal film such as an l-based alloy, and its line portion is formed to have an extremely small width (about 20 to 40 μm).
The entire width of the lower terminal film 31a is 100 to 120 μm.
It is considered to be the wide part. The address line 31
Is 150 nm in order to reduce the step difference from the surface of the substrate 1.
It is formed to a thin film thickness, and an anodic oxide film a is formed on the surface of the line portion.

The address line terminal portion 31A composed of the lower layer terminal film 31a and the upper layer terminal film 31b laminated on the lower layer terminal film 31a has the same terminal length as the terminal portion 32a of the data line 32. The slits 34 along the direction equally divide the two regions B1 and B2, each of which has a width of 50 to 40 .mu.m or less.

The slit 34 is formed at the same time when the data line metal film is patterned, and the slit 34 has the same shape on both the lower layer terminal film 31a and the upper layer terminal film 31b. Has been formed.

Further, the terminal portion 3 of the address line 31.
1A is exposed by providing an opening 24b in the protective insulating film 24. The opening 24b is formed in the terminal portion 3
The terminal portion 31A is formed to have a size such that the peripheral portion of the terminal portion 1A is exposed except for the peripheral portion thereof.
It is covered with to prevent corrosion from the periphery.

In this TFT panel, the terminal portion 31A of the address line 31 has a two-layer film structure of a lower terminal film 31a and an upper terminal film 31b made of an Al-based metal film, but the protective insulating film 24 is formed. Even if the heat-deposition is performed so that a good film quality is obtained, the terminal portion 32 is formed at the time of the film formation.
Protrusions such as hillocks and whiskers do not occur on a.

That is, the lower layer terminal film 31a of the terminal portion 31A is a thin film having a film thickness of about 150 nm formed integrally with the address line 31, and if the Al-based metal film has this film thickness. , The protective insulating film 24 is 220 to 25
Even if the film is formed by heating at 0 ° C., no protrusion is generated. In this embodiment, the lower layer terminal film 31a is also divided into the two regions B1 and B2 by the slit 34. However, even if the lower layer terminal film 31a is not divided into a plurality of regions, a protrusion is generated. There is no.

Further, the lower terminal film 31a is formed at the film forming temperature (the film forming temperature) when the gate insulating film 12, the blocking insulating film 17 shown in FIG. 13, and the interlayer insulating film 23 are formed in the manufacturing process of the TFT panel. 220 to 250 ° C.), the lower terminal film 31a is also formed when these insulating films are formed.
There is no protrusion on the.

On the other hand, the upper layer terminal film 31 of the terminal portion 31A.
b is the same film thickness as the data line 32 (200 to 350 n
Although it is an Al-based metal film having a thickness of m), this upper terminal film 3
Since 1b is divided into two areas B1 and B2 by the slit 34, the width of each of the divided areas A1 and A2 is small (50 to 40 .mu.m or less), and therefore the same as the terminal portion 32a of the data line 32 described above. And the protective insulating film 2
No protrusion is generated during the film formation of No. 4.

In the above embodiment, the address line 3
The terminal portion 31A of No. 1 has a two-layered film structure in which the upper layer terminal film 31b is laminated on the lower layer terminal film 31a. The terminal portion 31A is a lower layer formed integrally with the address line 31 and having a film thickness of about 150 nm. A single layer film composed of only the terminal film 31a may be used. In that case, no protrusion is formed on the terminal portion 31a of the address line 31 even if the terminal portion 31a of the address line 31 is not divided. Therefore, at least the terminal portion of the data line 32 is formed. 32a may be divided.

Further, in the above embodiment, the data line 32
The terminal portion 32a is divided into two regions A1 and A2 by slits 33 and 34 provided in the center thereof along the terminal length direction, but the divided shape of the terminal portion 32a may be arbitrary. It suffices that the terminal portion is divided into a plurality of regions that are locally continuous with each other. In this case as well, it is desirable that the protective insulating film 24 is formed by heating at 220 to 250 ° C. and the upper data line 32 has a film thickness of 200 to 350 nm. Is 50
It may be set to -40 μm or less.

10 and 11 show a second embodiment of the present invention. FIG. 10 is a plan view of a data line terminal portion of a TFT panel, and FIG. 11 is a sectional view taken along line XI-XI of FIG. Is. In addition, in FIG. 10 and FIG.
Components corresponding to those shown in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the terminal portion 32a of the data line 32 has a slit 35 having four discontinuous portions 36 provided in a frame shape along the peripheral edge of the terminal portion 32a. It is divided into a region C2, and the divided regions C1 and C2 are continuous with each other in each discontinuous portion 36 of the slit 35, and the width W3 of the wide region C1 at the center is 50 to 40 .mu.m or less. Narrow area C
The widths W4 and W5 of 2 are each set to about 10 to 15 μm.

In this embodiment, the slit 35 provided in a frame shape along the peripheral edge of the terminal portion 32a has the discontinuous portions 36 at four positions.
Need only have a discontinuous portion at least in part.

In addition, the TFT panel of the above-mentioned embodiment is TF
Although T has an inverted stagger structure, the present invention
The FT can also be applied to a TFT panel having a stagger structure, a coplanar structure, an inverse coplanar structure, etc., and even in that case, a lower layer line for wiring on the substrate (a data line in a TFT panel having a stagger structure or a coplanar structure) , The address line in the TFT panel having the reverse coplanar structure of the TFT) and the upper layer line (the TFT panel having the stagger structure or the coplanar structure in which the TFT has the stagger structure or the reverse coplanar structure) which is wired on the insulating film formed on the substrate. In the structured TFT panel, at least the terminal portion of the upper layer line formed to have a certain thickness may be divided into a plurality of regions that are locally continuous with each other.

[0069]

In the TFT panel of the present invention, the terminal portion of at least the upper layer line of the lower layer line and the upper layer line is divided into a plurality of regions which are locally continuous with each other, and therefore the protective insulating film Even if the film is formed by heating to obtain a good film quality, no protrusions are generated in the terminal portion of the upper layer line during the film formation. It is possible to prevent pitting corrosion from occurring in the terminal portion of the.

[Brief description of drawings]

FIG. 1 is a plan view of a data line terminal portion of a TFT panel showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a plan view of an address line terminal portion of a TFT panel.

5 is a cross-sectional view taken along the line VV of FIG.

6 is a sectional view taken along line VI-VI of FIG.

FIG. 7 is a diagram showing the relationship between the heating temperature and the number of generated protrusions when the line width of the metal film is 50 μm and the film thickness is 350 nm.

FIG. 8 is a diagram showing the relationship between the thickness of a metal film and the number of generated protrusions when the heating temperature is 250 ° C. and the line width of the metal film is 50 μm.

FIG. 9: The heating temperature is 250 ° C., and the thickness of the metal film is 35.
The figure which shows the relationship between the line width of a metal film at the time of 0 nm, and the number of generated protrusions.

FIG. 10 is a plan view of a data line terminal portion of a TFT panel showing a second embodiment of the present invention.

11 is a cross-sectional view taken along the line XI-XI of FIG.

FIG. 13 is an equivalent circuit plan view of a conventional TFT panel.

FIG. 14 is a plan view of a data line terminal portion in a conventional TFT panel.

15 is a sectional view taken along line XV-XV in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 12 ... Gate insulating film 23 ... Interlayer insulating film 24 ... Protective insulating film 24a, 24b ... Opening 31 ... Address line a ... Anodized film 31A ... Terminal part 31a ... Lower layer terminal film 31b ... Upper layer terminal film 32 ... Data line 32a ... Terminal part 33, 34, 35 ... Slit 36 ... Discontinuous part A1, A2, B1, B2, C1, C2 ... Divided area

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[Procedure amendment]

[Submission date] March 25, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a plan view of a data line terminal portion of a TFT panel showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a sectional view taken along the line III-III in FIG.

FIG. 4 is a plan view of an address line terminal portion of a TFT panel.

5 is a cross-sectional view taken along the line VV of FIG.

6 is a sectional view taken along line VI-VI in FIG.

FIG. 7 is a diagram showing the relationship between the heating temperature and the number of generated protrusions when the line width of the metal film is 50 μm and the film thickness is 350 nm.

FIG. 8 is a diagram showing the relationship between the thickness of a metal film and the number of generated protrusions when the heating temperature is 250 ° C. and the line width of the metal film is 50 μm.

FIG. 9: The heating temperature is 250 ° C., and the thickness of the metal film is 35.
The figure which shows the relationship between the line width of a metal film at the time of 0 nm, and the number of generated protrusions.

FIG. 10 is a plan view of a data line terminal portion of a TFT panel showing a second embodiment of the present invention.

11 is a cross-sectional view taken along the line XI-XI of FIG.

FIG. 12 is an equivalent circuit plan view of a conventional TFT panel.

FIG. 13 is a sectional view of one TFT portion of a conventional TFT panel.

FIG. 14 is a plan view of a data line terminal portion in a conventional TFT panel.

15 is a sectional view taken along line XV-XV in FIG.

[Explanation of Codes] 1 ... Substrate 12 ... Gate insulating film 23 ... Interlayer insulating film 24 ... Protective insulating film 24a, 24b ... Opening 31 ... Address line a ... Anodized film 31A ... Terminal portion 31a ... Lower layer terminal film 31b ... Upper layer terminal Membrane 32 ... Data line 32a ... Terminal part 33, 34, 35 ... Slit 36 ... Discontinuous part A1, A2, B1, B2, C1, C2 ... Divided area

Claims (4)

[Claims] 1. A thin film transistor on an insulating substrate,
A lower layer line wired on the substrate to supply a gate signal or a data signal to the thin film transistor, and an upper layer line wired on the insulating film formed on the substrate to supply a data signal or a gate signal to the thin film transistor. In addition to the above, the upper layer line is covered with a protective insulating film, in this protective insulating film, in the thin film transistor panel in which an opening for exposing the terminal portion of the upper layer line except its peripheral portion is formed, the lower layer line and the upper layer line A thin film transistor panel, wherein at least the terminal portion of the upper layer line is divided into a plurality of regions locally continuous with each other. 2. The protective insulating film is an insulating film formed by heating at 220 to 250 ° C., and the film thickness of the terminal portion of the upper layer line is 20.
0 ~ 350nm, the width of each divided area of this terminal is 50 ~
The thin film transistor panel according to claim 1, wherein the thickness is 40 μm or less. 3. The terminal portion of the upper layer line is divided by a slit provided in the center thereof along the terminal length direction, and the divided regions are continuous with each other outside the end portion of the slit. The thin film transistor panel according to claim 1 or 2. 4. The terminal portion of the upper layer line is divided into a wide area at the center and a narrow area at the peripheral edge by a slit having a discontinuous portion at least partially provided in a frame shape along the peripheral edge thereof. The thin film transistor panel according to claim 1, wherein the respective divided regions are continuous with each other in the discontinuous portion of the slit.