JPH1152425A - Tft array substrate and its production, and tft liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a TFT(thin-film transistor) array substrate which is strong to a high-temp. heat treatment, is low in resistance in wiring parts, may be produced with smaller number of stages for remedy with the heat treatment and has a good adhesion between the substrates and the thin films on these substrates and high reliability. SOLUTION: A high m.p. metal is used for at least one of the source wiring 1 or common wiring 2 or gate wiring 3 of the TFT array substrate having the substrate, the source wiring 1, common wiring 2 and gate wiring 3 and TFTs 4 formed in a matrix form on the substrate surface. At least one of the source wiring 1, common wiring 2 and gate wiring 3 formed by using the high m.p. metal is annealed at the m.p. of the high m.p. metal or below.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT in which a refractory metal is used for wiring and the refractory metal wiring is laser-annealed at a temperature lower than the melting point.
The present invention relates to an array substrate, a method for manufacturing the same, and a TFT liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, wiring of a TFT array substrate is required to have a low resistance for large capacity and high definition.
Generally, Al (aluminum) is used. However, on the other hand, Al is vulnerable to the thermal process, and therefore requires many processes as a measure for heat treatment. For example, Al undergoes a hillock (abnormal growth of a thin film), migration, and the like when subjected to a heat process at about 300 ° C. or higher. Therefore, a step of anodizing the surface of the Al metal and a subsequent step of patterning the surface oxide film are required, and the number of steps is greatly increased.

On the other hand, it can withstand high temperature heat treatment,
As a low-resistance material, there is a high melting point metal such as Mo (molybdenum) and W (tungsten). Usually, a refractory metal thin film using these materials is formed by a sputtering method. However, the refractory metal thin film formed by the sputtering method has a crystal defect caused by a distortion of a state change from a gas phase to a solid phase, and thus is much higher than the material's original specific resistance. Therefore, if a high-melting-point metal is used as a wiring material for a TFT array substrate that requires low resistance, this point poses a problem.

Generally, a high melting point metal thin film having such crystal defects can be reduced in resistance by performing an annealing treatment. For example, Japanese Patent Application Laid-Open No. Hei 5-21387 describes an annealing method in which a high melting point metal thin film is thermally melted by a laser and then recrystallized. However, when such an annealing method is used for a refractory metal thin film on a TFT array substrate, a temperature much higher than the strain point of the substrate is required. The adhesive force is weakened, and the substrate is adversely affected.

[0005]

As described above, TFTs
In general, Al is used for the wiring of the array substrate. However, Al is vulnerable to the thermal process, and requires many additional steps as a measure against it. On the other hand, there is a high melting point metal as a wiring material that is resistant to heat treatment and has low resistance. However, in general, these high-melting metals easily form crystal defects when forming a thin film, and thus have a higher resistivity than the original resistivity. Further, such a process of improving crystal defects and reducing the resistance is not easy because the substrate is likely to be adversely affected. Therefore, the use of a high melting point metal for a TFT array substrate that requires low resistance has some problems.

The present invention has been made in order to solve the above-mentioned problems in such a situation. A first object of the present invention is to provide a wiring portion which is resistant to high-temperature heat treatment and has low resistance at the same time. There is good adhesion between the substrate and the thin film on the substrate,
An object of the present invention is to obtain a TFT array substrate having high electrical reliability. The second object is to reduce the resistance of the refractory metal wiring so as not to impair the adhesion between the substrate and the thin film on the substrate, and at the same time, it is possible to perform such a resistance reduction process with a small number of steps. It is still another object of the present invention to provide a method of manufacturing a TFT array substrate capable of reducing the number of heat treatment steps in the manufacturing process of the TFT array substrate itself and a device incorporating the same. Further, a third object is to provide a TFT liquid crystal display device using a highly reliable TFT array substrate, which is resistant to high-temperature heat treatment, has low resistance in the wiring portion, has good adhesion between the substrate and the thin film on the substrate, and has high reliability. Is what you get.

[0007]

In a TFT array substrate according to the present invention, a substrate, a source wiring, a common wiring, a gate wiring, and a TFT (thin film transmission) formed in a matrix on the surface of the substrate are provided.
tor), a refractory metal is used for at least one of the source wiring or the common wiring or the gate wiring, and the source wiring or the refractory metal using the refractory metal is used. At least one of the common wiring and the gate wiring is annealed by a laser at a temperature equal to or lower than the melting point of the high melting point metal.

The high melting point metal of the TFT array substrate according to the present invention is Mo (molybdenum) or Ta (tantalum).
Or W (tungsten).

The high melting point metal of the TFT array substrate according to the present invention is Cr (chromium).

Further, the high melting point metal of the TFT array substrate according to the present invention has been annealed by a YAG laser.

[0011] The manufacturing method according to the present invention is directed to a method of manufacturing a TFT array substrate comprising a substrate, a source wiring, a common wiring, a gate wiring, and a TFT formed in a matrix on the surface of the substrate. A high melting point metal is used for at least one of the wiring or the common wiring or the gate wiring, and at least one of the source wiring or the common wiring or the gate wiring using the high melting point metal is used for the high melting point. It is manufactured with a step of annealing at a temperature lower than the melting point of the metal.

Further, in the method of manufacturing a TFT array substrate according to the present invention, the TFT array substrate is annealed by using a YAG laser and manufactured.

Furthermore, a TFT liquid crystal display device according to the present invention is characterized in that the TFT array substrate of the present invention is used.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 6 show a first embodiment of the present invention.
It is for explaining. Here, FIG. 1 is a schematic configuration diagram of a TFT array substrate. In the figure, reference numeral 1 denotes a group of source wirings formed on a glass substrate, and S ₁ , S ₂ .
It is composed of _M source wirings. 2 is composed of a plurality of common wiring of a common wiring group arranged formed perpendicular to the source wiring group _{1, C 1, C 2 ...} C N. 3 is constituted of a plurality of gate lines of a gate wiring group arranged formed perpendicular to the source wiring group 1 and so as to alternate with the common wiring group _{2, G 1, G 2 ...} G N. Reference numeral 4 denotes a TFT formed in each section surrounded by the source wiring group 1, the common wiring group 2, and the gate wiring group 3, reference numeral 5 denotes a storage capacitor for holding a signal voltage input through the TFT 4, Reference numeral 6 denotes a source terminal provided in the source wiring group 1, and reference numeral 7 denotes a plurality of common wirings C ₁ , C ₂ .
One common wiring for common provided to make each potential of _N common, 8 is a common wiring contact hole formed for connecting the common wiring group 2 and the common wiring 7 for common, and 9 is a common wiring contact hole. Terminal provided on the common wiring for use, 10 is a gate terminal connected to the gate wiring group 3 through the lead wiring 11, and 12 is a gate wiring group contact hole formed for connecting the lead wiring 11 and the gate wiring group 3. , 13 is a short ring which is a wiring provided for substrate inspection, and 14 is an inspection resistor also provided for substrate inspection. Reference numeral 100 denotes a liquid crystal to be injected between the TFT array substrate and the counter substrate for easy understanding, and no liquid crystal is formed on the TFT array substrate itself.

FIG. 2 is an upper plan view around one pixel of the TFT, in other words, an upper plan view around one section surrounded by the source wiring group 1, the common wiring group 2, and the gate wiring group 3. FIG. 3 is a cross-sectional configuration diagram along AA ′ in FIG. In the figure, 15 is a glass substrate, 16
Is a gate insulating film, 17 is intrinsic i-type hydrogenated amorphous silicon, 18 is n-type hydrogenated amorphous silicon, 19 is a drain electrode, 20 is a storage capacitor electrode,
21 is a protective film, 22 is a flattening film, 23 is a drain contact hole, 24 is a storage capacitor electrode contact hole, 2
Reference numeral 5 denotes an ITO (indium tin oxide) thin film serving as a pixel electrode. The gate wiring group 3, the gate insulating film 16, the i-type hydrogenated amorphous silicon 17 and the n-type hydrogenated amorphous silicon 18, the source wiring group 1, and the drain electrode 19 constitutes the TFT 4 shown in FIG. FIG. 4 is a cross-sectional configuration diagram around the gate terminal 10 shown in FIG. FIG. 5 is a cross-sectional configuration diagram around the source terminal 6 shown in FIG. FIG. 6 is a schematic diagram of a manufacturing process for explaining the method of manufacturing the TFT array substrate according to the first embodiment of the present invention, taking the portion shown in FIG. 3 as an example.

Hereinafter, a TFT array substrate and a method of manufacturing the same according to the first embodiment of the present invention will be described mainly with reference to FIG. First, the gate wiring group 3 is placed on the glass substrate 15.
Then, Mo, which is the material of the common wiring group 2, is formed by a sputtering method. After that, photolithography, wet etching,
The pattern processing is performed by removing the resist to form a gate wiring group 3 and a common wiring group 2 as shown in FIG. Thereafter, as shown in FIG.
Then, only the common wiring group 2 is annealed at a temperature equal to or lower than the melting point of Mo using the second harmonic of the YAG laser to reduce the resistance without melting. Thereafter, a silicon nitride film containing hydrogen, i-type hydrogenated amorphous silicon 17 and n-type hydrogenated amorphous silicon 18 which are the gate insulating film 16 are successively formed by the plasma CVD method. Then, unnecessary portions of the i-type hydrogenated amorphous silicon 17 and the n-type hydrogenated amorphous silicon 18 are removed by photolithography, dry etching, and resist removal to form as shown in FIG. 6C.

Next, the gate insulating film 16 is patterned by photolithography, dry etching and resist removal.
A gate wiring contact hole 12 as shown in FIG. 4 is formed. Although not shown, a common wiring contact hole 8 is formed in the same manner. Returning to FIG.
is formed by a sputtering method, and further through photolithography, wet etching, and resist removal steps, the source wiring group 1 is formed.
And a drain electrode 19 and a storage capacitor electrode 20 are formed. At this time, a lead wire 11 to the gate terminal 10 as shown in FIG. 4 is also formed. Thereafter, only the source wiring group 1 is annealed by the second harmonic of the YAG laser below the melting point to lower the resistance without melting. Further, source wiring group 1
Then, part of the n-type hydrogenated amorphous silicon 18 is removed using the drain electrode 19 as a mask. Then, a silicon nitride film containing hydrogen is formed as the protection film 21. Further, a photosensitive organic resin film is applied as a flattening film 22.

After photolithography and dry etching, as shown in FIG.
1 is partially removed to form the gate terminal 10. Similarly, as shown in FIG. 5, a part of the protective film 21 on the source wiring group 1 is partially removed, and the source terminal 6 is formed. Similarly, as shown in FIG. 6, part of the protective film 21 on the drain electrode 19 is partially removed to form a drain contact hole 23. Then, in a similar manner, a part of the protective film 21 on the storage capacitor electrode 20 is partially removed, and a storage capacitor electrode contact hole 24 is formed, as shown in FIG. 6D. Finally, an ITO (indium tin oxide) thin film 25 is formed as a pixel electrode by a sputtering method, and is formed as shown in FIG.

In the TFT array substrate manufactured in this manner, the wiring portion is resistant to high-temperature heat treatment by using a high melting point metal for the wiring portion. Therefore, in the manufacturing process of the TFT array substrate itself and the device incorporating the same, it is possible to reduce the number of steps for heat treatment and reduce the cost. On the other hand, since the laser annealing at a temperature lower than the melting point is used for the resistance lowering treatment of the high melting point metal, the increase in the number of steps due to the lowering of the resistance of the high melting point metal wiring is reduced. Further, since the resistance of the wiring portion is reduced as described above, it is possible to cope with a large-capacity, high-definition device requiring low resistance.
In addition, when the laser annealing is performed, the high melting point metal is annealed at a temperature below the melting point without melting, so that the adhesion between the substrate and the thin film on the substrate is good, and there is almost no damage or distortion to the base. , Electrical reliability is high. Furthermore, since only the refractory metal wiring portion is selectively annealed here, no pre-treatment such as forming a protective film on other portions is necessary when performing laser annealing, which further speeds up the manufacturing process. And cost reduction are possible. If necessary, a heat-resistant barrier may be formed by forming a silicon oxide film, a silicon nitride film, or the like on the substrate.

In the above description, M is used as the high melting point metal.
Although o is used, another refractory metal such as Cr, Ta, or W may be used. Of course, there is no problem with these laminated films and alloy thin films as long as they are high melting point metals. However, the above Mo,
As compared with other high melting point metals, Ta and W have a relatively large effect of lowering the resistance by the laser annealing method having a melting point or lower as in the present invention, and particularly have an effect that the wiring width can be reduced in design. large. When Cr is used, wet etching can be easily performed.

In addition, although an example has been described in which the high-melting point metal thin film is laser-annealed after pattern processing, the pattern processing may be performed after forming the thin film and then laser-annealing only the necessary portions. Of course, if the productivity is not reduced, the entire surface of the substrate may be laser-annealed.

Further, the case of an amorphous silicon TFT has been described, but a polysilicon TFT may be used.

Although the case where the silicon nitride film containing hydrogen and the organic resin film are used for the protective film has been described, a silicon oxide film may be used. Further, an organic resin film may be stacked. Of course, a coating and firing type inorganic transparent thin film may be used.

Although the case where the storage capacitor is formed between the pixel electrode and the common line has been described, the same applies to the case where the storage capacitor is formed between the pixel electrode and the preceding gate line.
The same applies to an IPS type LCD.

It is also possible to anneal with a YAG primary laser, a third harmonic laser, a fourth harmonic laser, or an excimer laser instead of the second harmonic laser of YAG. Note that the YAG laser is a solid-state laser, and although it has lower energy than an excimer laser which is a gas laser, it is a stable and easy-to-maintain device. In this regard, YAG laser is advantageous in terms of production maintenance cost and yield,
As in the present invention, the advantage that a low energy YAG laser can be used is great.

Further, the inspection method of the TFT array substrate may be different as shown in FIG. 7, that is, the guard resistor transistor 26 may be provided at the terminal as shown in FIG.

Further, another TFT structure may be used.

Furthermore, the same can be applied to the manufacture of semiconductors.

Embodiment 2 Next, a TFT liquid crystal display device using the TFT array substrate according to the first embodiment will be described with reference to FIG. FIG. 8 is an assembled sectional view of the TFT liquid crystal display device according to the second embodiment of the present invention. In the figure, A is the TF of the first embodiment.
The T array substrate, B is the counter electrode substrate, and C is the liquid crystal layer. In the counter electrode substrate B, 102 is a glass substrate 15
A color filter formed thereon by a pigment dispersion method or a dyeing method, a counter electrode 103 formed thereon of ITO,
Reference numeral 104 denotes an alignment film made of polyimide or the like formed thereon. Also, in the TFT array substrate A,
Similarly, an alignment film 104 is formed. In the TFT liquid crystal display device, the TFT array substrate A and the counter electrode substrate B thus formed are assembled at a small interval as shown in FIG. 8, and the liquid crystal 100 is injected into the TFT array substrate A and the short ring 13 and the inspection. It can be obtained by cutting and removing unnecessary parts such as the use resistor 14. As described above, by using a TFT array substrate that is resistant to high-temperature heat treatment, has low resistance in the wiring portion, has good adhesion between the substrate and the thin film on the substrate, and has high reliability as in the first embodiment. , Low cost, large capacity, high definition, highly reliable TF
A T liquid crystal display device can be obtained.

[0030]

Since the present invention is configured as described above, it has the following effects.

A TFT array substrate according to the present invention is a TFT array substrate comprising a substrate, a source line, a common line, a gate line, and a TFT formed in a matrix on the surface of the substrate. A high melting point metal is used for at least one of the wiring or the gate wiring, and at least one of the source wiring or the common wiring or the gate wiring where the high melting point metal is used is used for the laser or the high melting point metal. Since the wire is annealed at a temperature lower than the melting point of the metal, the wiring portion is resistant to high-temperature heat treatment and has low resistance at the same time. be able to.

In the TFT array substrate according to the present invention, Mo, Ta, and W have a greater effect of lowering the resistance by the laser annealing method having a melting point lower than that of the present invention as compared with other refractory metals. The wiring width can be reduced in design.

In the TFT array substrate according to the present invention, Cr can perform wet etching relatively easily as compared with other refractory metals.

Further, in the TFT array substrate according to the present invention, the YAG laser is a solid-state laser, which is more stable and more maintainable than the excimer laser which is a gas laser. A TFT array substrate can be realized.

In a method of manufacturing a TFT array substrate according to the present invention, a method of manufacturing a TFT array substrate including a substrate, a source wiring, a common wiring, a gate wiring, and a TFT formed in a matrix on the surface of the substrate. In the method, a refractory metal is used for at least one of the source wire or the common wire or the gate wire, and at least one of the source wire or the common wire or the gate wire using the refractory metal is laser-coated. The annealing at a temperature equal to or lower than the melting point of the high melting point metal, so that the high melting point metal wiring can be reduced in resistance so as not to impair the adhesion between the substrate and the thin film on the substrate, Can be manufactured with a small increase in the number of steps.

In the method for manufacturing a TFT array substrate according to the present invention, the YAG laser is a solid-state laser, which is a more stable and maintainable device than an excimer laser which is a gas laser. It can be manufactured advantageously in terms of cost and yield.

By using such a TFT array substrate of the present invention, a low-cost, large-capacity, high-definition, highly-reliable TFT liquid crystal display device can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a TFT array substrate according to a first embodiment of the present invention.

FIG. 2 is an upper plan view around a TFT pixel on a TFT array substrate according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional configuration view taken along line A-A 'in FIG.

FIG. 4 is a sectional configuration diagram around a gate terminal on the TFT array substrate according to the first embodiment of the present invention;

FIG. 5 is a sectional configuration diagram around a source terminal on the TFT array substrate according to the first embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a manufacturing process of the TFT array substrate according to the first embodiment of the present invention.

FIG. 7 is another example similar to the TFT array substrate according to the first embodiment of the present invention.

FIG. 8 is an assembled sectional view of a TFT liquid crystal display device according to a second embodiment of the present invention.

[Explanation of symbols]

1 source line group S ₁ ... S _M source lines 2 common wiring group C ₁ ... C _N common wirings 3 gate wiring group G ₁ ... G _N gate wiring 4 TFT 5 storage capacitor 6 common line for source terminal 7 common 8 common wiring contact Hall 9 Common terminal 1
Reference Signs List 0 Gate terminal 11 Lead wiring 12 Gate wiring contact hole 13 Short ring 14 Inspection resistor 15 Glass substrate 16 Gate insulating film 17 i-type hydrogenated amorphous silicon 18 n-type hydrogenated amorphous silicon 19 Drain electrode 20 Storage capacitor electrode 21 Protective film 22 Flattening film 23 Drain contact hole 24 Storage capacitor electrode contact hole 25 ITO (indium tin oxide) thin film 26 Guard resistance transistor 100 Liquid crystal 101 Polarizer 102 Color filter 103 Counter electrode 104 Alignment film 105 Pixel and TFT A TFT array substrate B Opposite Electrode substrate C Liquid crystal layer

Claims (7)

[Claims] 1. A TFT array substrate comprising a substrate, a source wiring, a common wiring, a gate wiring, and a TFT formed in a matrix on the substrate surface, wherein at least one of the source wiring, the common wiring, and the gate wiring is provided. While one high melting point metal is used, at least one of the source wiring or the common wiring or the gate wiring where the high melting point metal is used is annealed by a laser at a temperature equal to or lower than the melting point of the high melting point metal. A TFT array substrate. 2. The TFT array substrate according to claim 1, wherein the refractory metal is Mo, Ta, or W. 3. The TFT array substrate according to claim 1, wherein the high melting point metal is Cr. 4. The TFT array substrate according to claim 1, wherein the laser is a YAG laser. 5. A method of manufacturing a TFT array substrate comprising a substrate, a source wiring, a common wiring, a gate wiring, and a TFT formed in a matrix on the surface of the substrate, wherein the source wiring, the common wiring, or the gate is provided. While using high melting point metal for at least one of the wiring,
A step of annealing at least one of the source wiring, the common wiring, and the gate wiring using the high melting point metal with a laser at a temperature equal to or lower than the melting point of the high melting point metal. . 6. The method according to claim 5, wherein the laser is a YAG laser. 7. A TF using the TFT array substrate according to any one of claims 1 to 4.
T liquid crystal display device.