JPH0766281A - Forming method of element isolating region - Google Patents

Forming method of element isolating region

Info

Publication number
JPH0766281A
JPH0766281A JP21438393A JP21438393A JPH0766281A JP H0766281 A JPH0766281 A JP H0766281A JP 21438393 A JP21438393 A JP 21438393A JP 21438393 A JP21438393 A JP 21438393A JP H0766281 A JPH0766281 A JP H0766281A
Authority
JP
Japan
Prior art keywords
oxide film
film
trench
locos
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21438393A
Other languages
Japanese (ja)
Inventor
Kenichi Azuma
賢一 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP21438393A priority Critical patent/JPH0766281A/en
Publication of JPH0766281A publication Critical patent/JPH0766281A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable a fine element isolating region to be formed by a method wherein a trench and an element isolating region are formed at the same time. CONSTITUTION:A thermal oxide film 2 and an anti-oxidizing film 3 (SiN film) are formed on a silicon semiconductor substrate 1, and the films 3 and 2 located on a part which serves as an element isolating region are so removed as to make the surface of the substrate 1 exposed. Then, the silicon semiconductor substrate 1 is thermally oxidized to form a LOCOS oxide film 4, and the LOCOS oxide film 4 is anisotropically etched using the anti-oxidizing film 3 as a mask. Then, the Si substrate 1 is anisotropically etched to form a trench 5. Next, a non-doped CVD-SiO2 6 is deposited on all the surface, all the surface is etched back until the anti-oxidizing film 3 is exposed, then the anti-oxidizing film 3 is removed, the oxide film 2 is removed by an HF treatment, and thus an NMOS element isolating region is formed by LOCOS and trench.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は素子分離領域の形成方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation region.

【0002】[0002]

【従来の技術】大容量のLSIを開発するには、限られ
たチップ面積内で、いかに集積度の高い集積回路を開発
するかによる。このような集積度の向上は、集積回路を
構成する素子の微細化によりなされる。更に、素子の微
細化はトランジスタの微細化を伴い、素子分離領域の微
細化も必要とされる。
2. Description of the Related Art Development of a large-capacity LSI depends on how to develop a highly integrated circuit within a limited chip area. Such an improvement in the degree of integration is made by miniaturizing the elements constituting the integrated circuit. Further, miniaturization of elements is accompanied by miniaturization of transistors, and miniaturization of element isolation regions is also required.

【0003】通常、素子分離領域の形成には、選択酸化
(LOCOS、ロコス)法と呼ばれる方法が用いられ
る。この方法はシリコン基板にSiN膜を形成した後、
フォトリソグラフィ工程にてパターンニングして素子分
離領域のSiN膜を除去し、露出したシリコン基板表面
を選択的に酸化することによりシリコン絶縁膜からなる
素子分離領域を形成する方法である。
In general, a method called a selective oxidation (LOCOS) method is used for forming the element isolation region. In this method, after forming a SiN film on a silicon substrate,
This is a method of forming a device isolation region made of a silicon insulating film by patterning in a photolithography process to remove the SiN film in the device isolation region and selectively oxidizing the exposed silicon substrate surface.

【0004】[0004]

【発明が解決しようとする課題】素子分離領域の縮小に
より以下の事が問題となってきている。選択酸化時にS
iN膜のストレスにより、狭い素子分離領域ではフィー
ルド酸化膜が十分に成長せず、フィールド酸化膜の薄膜
化が起こる(図1)。フォトリソグラフィ、エッチング
工程で0.2μm以下の開口ができても、図1からも明
らかなように素子分離領域のLOCOS酸化膜の膜厚は
60%以下になり、十分な分離能力が得られなくなって
きている。またLOCOS酸化膜下の不純物濃度を上げ
ることによって分離特性を向上させることもできるが、
不純物濃度を上げすぎると接合耐圧が低くなる問題があ
る。他に、選択酸化時にSiN膜に覆われた領域にまで
Si基板が酸化され、バーズビークと呼ばれるシリコン
酸化膜が広がり、素子領域が狭くなる問題もある。
Due to the reduction of the element isolation region, the following matters have become problems. S during selective oxidation
Due to the stress of the iN film, the field oxide film does not grow sufficiently in the narrow element isolation region, and the field oxide film is thinned (FIG. 1). Even if an opening of 0.2 μm or less is formed in the photolithography or etching process, as is apparent from FIG. 1, the film thickness of the LOCOS oxide film in the element isolation region becomes 60% or less, and sufficient isolation capability cannot be obtained. Is coming. Also, the separation characteristics can be improved by increasing the impurity concentration under the LOCOS oxide film.
If the impurity concentration is too high, there is a problem that the junction breakdown voltage becomes low. Another problem is that the Si substrate is oxidized to the region covered with the SiN film during the selective oxidation, the silicon oxide film called bird's beak spreads, and the element region is narrowed.

【0005】バーズビークを抑える技術としてSiN膜
の横にサイドウォールを形成する技術(特開平4-127433
号)が有る。しかし、サイドウォールを形成する技術に
おいてはパターンの微細化に伴い選択酸化時の開口幅が
サイドウォール幅だけ小さくなり、上記で示した素子分
離領域のLOCOS酸化膜の膜厚の薄膜化が起こりやす
い。このようなLOCOS法の問題点を解決する素子分
離法として、トレンチ分離法(特開平2-198153号)があ
る。この方法は、異方性エッチングによりSi基板に溝
(トレンチ)を形成し、酸化膜などで埋め込みエッチバ
ックをおこなう方法である。酸化を行わないのでパター
ニング通りに素子領域を決定でき、狭い分離領域でも膜
厚が確保できる。
As a technique for suppressing bird's beak, a technique for forming a sidewall beside a SiN film (Japanese Patent Laid-Open No. 4-127433)
No.). However, in the technique of forming the sidewall, the opening width at the time of selective oxidation is reduced by the sidewall width as the pattern is miniaturized, and thus the LOCOS oxide film in the element isolation region is likely to be thinned. . A trench isolation method (Japanese Patent Laid-Open No. 2-198153) is known as an element isolation method that solves the problems of the LOCOS method. In this method, a trench is formed in the Si substrate by anisotropic etching, and an oxide film or the like is embedded to perform etch back. Since no oxidation is performed, the element region can be determined according to patterning, and the film thickness can be secured even in a narrow isolation region.

【0006】しかし、溝の埋め込み時に全面エッチバッ
クを行うため、トレンチ以外の広い分離領域の埋め込み
が困難となる。これを解決する方法に、広い分離領域を
LOCOS法で、狭い分離領域をトレンチで形成する方
法もあるがフォト工程が2回必要となる。更に、自己整
合的にLOCOS酸化膜とトレンチ形成する方法(米国
特許5096848,特開平3-24554号)もあるが工程が複雑で
ある。
However, since the entire surface is etched back when the trench is filled, it is difficult to fill a wide isolation region other than the trench. As a method of solving this, there is a method of forming a wide isolation region by a LOCOS method and a narrow isolation region by a trench, but the photo process is required twice. There is also a method of forming a LOCOS oxide film and a trench in a self-aligned manner (US Pat. No. 5096848, Japanese Patent Laid-Open No. 3-24554), but the process is complicated.

【0007】[0007]

【課題を解決するための手段】かくして本発明によれ
ば、シリコン基板上に酸化膜、酸化防止膜をこの順で形
成し、次に素子分離領域形成予定部分及びトレンチ形成
予定部分の酸化膜及び酸化防止膜を基板が露出するまで
除去し、該基板を熱酸化することにより、前記形成予定
部分にロコス酸化膜を形成し、次に前記トレンチ形成予
定部分の基板が露出するまで選択的にロコス酸化膜を異
方性エッチングにより除去し、更にトレンチ形成予定部
分のシリコン基板を選択的に異方性エッチングして凹部
を形成し、次に全面に酸化シリコンを堆積させた後、エ
ッチバック処理に付して酸化防止膜を露出させた後、該
酸化防止膜及び前記酸化膜を除去することによりトレン
チと素子分子領域を同時に形成することを特徴とする素
子分離領域の形成方法が提供される。
Thus, according to the present invention, an oxide film and an anti-oxidation film are formed in this order on a silicon substrate, and then an oxide film in a portion where a device isolation region is to be formed and a portion where a trench is to be formed are formed. The oxidation preventing film is removed until the substrate is exposed, and the substrate is thermally oxidized to form a locos oxide film at the portion where the formation is to be formed, and then selectively the locos is formed until the substrate where the trench is to be formed is exposed. The oxide film is removed by anisotropic etching, and the silicon substrate in the part where the trench is to be formed is selectively anisotropically etched to form a recess, and then silicon oxide is deposited on the entire surface, followed by an etchback process. A method for forming an element isolation region, characterized in that a trench and an element molecule region are simultaneously formed by removing the antioxidant film and the oxide film after exposing There is provided.

【0008】以下、本発明の形成方法に従って説明す
る。まず、シリコン基板上に酸化膜、酸化防止膜を形成
する。酸化膜の形成方法には、熱酸化法、CVD法、ス
パッタ法等の公知の方法を使用することができ、その膜
厚は25〜150Åが好ましい。また酸化防止膜は、例
えば、SiN等が挙げられ、その形成方法はPCVD
法,LPCVD法等の方法が挙げられ、膜厚は500〜
2500Åが好ましい。
A description will be given below according to the forming method of the present invention. First, an oxide film and an antioxidant film are formed on a silicon substrate. As a method for forming the oxide film, a known method such as a thermal oxidation method, a CVD method or a sputtering method can be used, and the film thickness thereof is preferably 25 to 150Å. The antioxidant film may be, for example, SiN or the like, and the formation method thereof is PCVD.
Method, LPCVD method, etc., and the film thickness is 500-
2500Å is preferred.

【0009】次に、1回のフォトリソグラフィ工程によ
り形成したレジストパターンをマスクとして、素子分離
領域及びトレンチとなる予定部分の酸化膜及び酸化防止
膜をエッチングにより除去する。ここで、素子分離領域
を酸化した後の表面を平坦にする必要があれば、シリコ
ン基板を更に100〜1000Åエッチングしてもよ
い。エッチング方法には公知の方法が使用でき、例え
ば、ウェットエッチング,イオンエッチング,プラズマ
エッチング等が挙げられる。
Next, using the resist pattern formed by one photolithography process as a mask, the oxide film and the oxidation prevention film in the portions to be the element isolation regions and trenches are removed by etching. Here, if it is necessary to flatten the surface after oxidizing the element isolation region, the silicon substrate may be further etched by 100 to 1000 Å. A known method can be used as the etching method, and examples thereof include wet etching, ion etching, and plasma etching.

【0010】次にレジストパターンを除去し、900℃
以上、好ましくは1000℃以上で熱酸化を行うことに
よりシリコン基板を酸化し、素子分離領域及びトレンチ
部にLOCOS酸化膜を膜厚1000〜5000Åで形
成する。この酸化の際に、酸化剤が酸化膜下へも拡散す
るので、上記素子分離領域及びトレンチ部の端部にいわ
ゆるバーズビークと称される酸化膜の横方向への張り出
しが生ずる。この張り出しのために、LOCOS酸化膜
は、端部に向かってその膜厚が徐々に減少する構造とな
る。ここで、このLOCOS法によるLOCOS酸化膜
に代えてポリバッファLOCOS法,サイドウォールL
OCOS法等による膜も使用することができる。
Next, the resist pattern is removed, and the temperature is 900 ° C.
As described above, preferably, the silicon substrate is oxidized by performing thermal oxidation at 1000 ° C. or higher, and a LOCOS oxide film is formed in a film thickness of 1000 to 5000 Å in the element isolation region and the trench portion. At the time of this oxidation, the oxidant also diffuses under the oxide film, so that the so-called bird's beak so-called lateral protrusion of the oxide film occurs at the ends of the element isolation region and the trench portion. Due to this overhang, the LOCOS oxide film has a structure in which the film thickness gradually decreases toward the end. Here, instead of the LOCOS oxide film formed by the LOCOS method, a polybuffer LOCOS method and a sidewall L are used.
A film formed by the OCOS method or the like can also be used.

【0011】次に上記LOCOS酸化膜を異方性エッチ
ングによりエッチングする。異方性エッチングには、プ
ラズマエッチング法、反応性イオンエッチング(RI
E)法等の公知の方法を使用することができる。エッチ
ングガスには、CF4+H2等ガスのようにシリコンのエ
ッチング速度よりLOCOS酸化膜のエッチング速度の
方が大きいガスを使用することが好ましい。このような
エッチングによって、LOCOS酸化膜がエッチングさ
れるが、このLOCOS酸化膜は素子分離領域より、ト
レンチ部の方が薄いので、トレンチ部のシリコン基板の
方がより早く露出する。
Next, the LOCOS oxide film is etched by anisotropic etching. For anisotropic etching, plasma etching, reactive ion etching (RI
A known method such as the method E) can be used. As the etching gas, it is preferable to use a gas such as CF 4 + H 2 which has a higher etching rate for the LOCOS oxide film than that for silicon. By such etching, the LOCOS oxide film is etched. Since the LOCOS oxide film is thinner in the trench portion than in the element isolation region, the silicon substrate in the trench portion is exposed earlier.

【0012】このようにトレンチ部のシリコン基板が露
出した時点でエッチングガスを変えることにより、シリ
コン基板を選択的に異方性エッチングし、トレンチを開
口することができる。この際使用できるエッチングガス
には、塩素系(Cl2 等)又は臭素系(HBr等)のガ
ス等が挙げられ、またトレンチの深さは1000〜30
00Åが好ましい。
By changing the etching gas when the silicon substrate in the trench portion is exposed in this way, the silicon substrate can be selectively anisotropically etched to open the trench. Examples of the etching gas that can be used at this time include chlorine-based (Cl 2 or the like) or bromine-based (HBr or the like) gas, and the depth of the trench is 1000 to 30.
00Å is preferred.

【0013】このトレンチには、サイドウォール反転防
止のために不純物を濃度1×1013〜1×1014ion
s/cm2注入エネルギー50〜150kevでトレン
チの側壁へ注入することが好ましい。また、上記エッチ
ング時のダメージの回復及びSi/SiO2界面を制御
するため、膜厚100〜1000Åの熱酸化膜を形成し
ても良い。
In order to prevent sidewall inversion, an impurity concentration of 1 × 10 13 to 1 × 10 14 ion is applied to the trench.
It is preferable to implant into the sidewall of the trench with s / cm 2 implantation energy of 50 to 150 kev. Further, a thermal oxide film having a film thickness of 100 to 1000 Å may be formed in order to recover the damage at the time of etching and control the Si / SiO 2 interface.

【0014】次にCVD法により、酸化シリコン膜を全
面に形成する。この酸化シリコン膜の膜厚は、最小トレ
ンチ幅の1/2以上であり1000〜5000Åが好ま
しい。この酸化シリコン膜形成後、フッ酸溶液又はRI
Eによる等速エッチバック等を使用して全面エッチバッ
クを行い、酸化防止膜を露出させる。尚、上記酸化シリ
コン膜の代わりに、ポリシリコン膜、アモルファスシリ
コン膜を形成して、エッチバック後、酸化処理を施すこ
とによる酸化シリコン膜を使用してもよい。
Next, a silicon oxide film is formed on the entire surface by the CVD method. The thickness of this silicon oxide film is at least ½ of the minimum trench width, and is preferably 1000 to 5000Å. After forming this silicon oxide film, hydrofluoric acid solution or RI
The entire surface is etched back by using a constant velocity etch back with E or the like to expose the antioxidant film. Instead of the above silicon oxide film, a polysilicon film or an amorphous silicon film may be formed, and a silicon oxide film obtained by performing an oxidation process after etching back may be used.

【0015】次に酸化防止膜及び酸化膜を溶剤処理して
除去すれば、LOCOS酸化膜とトレンチを併用した素
子分離を形成することができる。ここで使用される溶剤
には酸化防止膜がSiNの場合はリン酸,一方酸化膜に
はHF等が挙げられる。本発明の形成方法は、素子分離
を必要とする半導体装置であれば適用でき、例えばNM
OS,PMOS,CMOS等の各種のデバイスに適用す
ることができる。
Next, if the antioxidant film and the oxide film are removed by solvent treatment, element isolation using a LOCOS oxide film and a trench together can be formed. The solvent used here includes phosphoric acid when the antioxidant film is SiN, and HF or the like for the oxide film. The formation method of the present invention can be applied to any semiconductor device that requires element isolation.
It can be applied to various devices such as OS, PMOS and CMOS.

【0016】[0016]

【作用】LOCOS酸化膜の薄膜化を利用しているので
自己整合的にLOCOS酸化膜による素子分離領域とト
レンチによる素子分離領域を同時に形成することがで
き、かつフォトリソグラフィー工程が1度で済む。
Since the thinning of the LOCOS oxide film is utilized, the element isolation region formed by the LOCOS oxide film and the element isolation region formed by the trench can be simultaneously formed in a self-aligned manner, and the photolithography process can be performed only once.

【0017】[0017]

【実施例】実施例1 シリコン半導体基体上1に熱酸化膜2を100Å、酸化
防止膜3(SiN膜)1200Åを形成し、次に1回の
フォトリソグラフィ工程により形成したリソグラフパタ
ーンをマスクとして、素子分離領域となる部分の酸化防
止膜3、酸化膜2を基板1が露出するまで除去し、次に
基板1をLOCOS酸化後の表面を平担にするため80
0Å更にエッチングした。
EXAMPLES Example 1 A thermal oxide film 2 of 100 Å and an antioxidant film 3 (SiN film) of 1200 Å were formed on a silicon semiconductor substrate 1, and then a lithographic pattern formed by a single photolithography process was used as a mask. The anti-oxidation film 3 and the oxide film 2 which are to be element isolation regions are removed until the substrate 1 is exposed, and then the substrate 1 is flattened to have a flat surface after LOCOS oxidation.
0Å Further etching.

【0018】次に、レジストパターンを除去した後、9
00℃以上の熱酸化により3500Åのシリコン半導体
基板を酸化し、LOCOS酸化膜4を形成した(図2
(b))。次に酸化防止膜3をマスクにLOCOS酸化
膜4を異方性エッチングした(LOCOS酸化膜時の広
い分離領域の50〜60%程度)。エッチングガスはフ
ロロカーボン系ガス(CM N ;m=1〜4、n=2〜
8、例えばCHF3 ,CH2 2 ,CH3 F等)とH2
又はO2 の混合ガスを使用した。図1に示すようにLO
COS膜厚は狭い開口幅で薄くなっているので、開口幅
0.2μm以下のパターンでは基板1が露出する。
Next, after removing the resist pattern, 9
The LOCOS oxide film 4 was formed by oxidizing the 3500Å silicon semiconductor substrate by thermal oxidation at 00 ° C or higher (Fig. 2).
(B)). Next, the LOCOS oxide film 4 was anisotropically etched using the anti-oxidation film 3 as a mask (about 50 to 60% of the wide isolation region at the time of LOCOS oxide film). The etching gas is a fluorocarbon-based gas (C M F N ; m = 1 to 4, n = 2 to
8, eg CHF 3 , CH 2 F 2 , CH 3 F, etc.) and H 2
Alternatively, a mixed gas of O 2 was used. As shown in FIG.
Since the COS film thickness is thin with a narrow opening width, the substrate 1 is exposed in a pattern with an opening width of 0.2 μm or less.

【0019】次に、Si基板1を3000Å程度異方性
エッチングし、トレンチ5を形成した(図2(c))。
エッチングガスは塩素系(Cl2 等)又は臭素系(HB
r等)のガス等を使用した。次にサイドウォール反転防
止用注入のためにホウ素イオンを30keV,3×10
12ions/cm2でトレンチ側壁へ注入した。次に、
エッチング時のダメージ回復とSi/SiO2界面の制
御のため、熱酸化膜を900℃以上、1000Åで形成
した。
Next, the Si substrate 1 was anisotropically etched to about 3000 Å to form a trench 5 (FIG. 2 (c)).
The etching gas is chlorine (Cl 2 etc.) or bromine (HB
r etc.) was used. Next, boron ions are added at 30 keV, 3 × 10 5 for implantation to prevent sidewall inversion.
It was injected into the sidewall of the trench at 12 ions / cm 2 . next,
A thermal oxide film was formed at 900 ° C. or more and 1000 Å in order to recover damage during etching and control the Si / SiO 2 interface.

【0020】次にノンドープCVD−SiO26(最小
トレンチ幅の1/2以上の膜厚)を全面に堆積(図2
(d))し、全面エッチバックした。酸化防止膜3が露
出したらエッチバックをとめ(図2(e))、この後、
溶剤処理(酸化防止膜がSiNの場合リン酸)により酸
化防止膜3を除去し、HF処理で酸化膜2を除去すれ
ば、LOCOSとトレンチを併用したNMOSの素子分
離が形成できた(図2(f))。
Next, non-doped CVD-SiO 2 6 (a film thickness of 1/2 or more of the minimum trench width) is deposited on the entire surface (FIG. 2).
(D)), and the entire surface was etched back. When the antioxidant film 3 is exposed, etching back is stopped (FIG. 2 (e)), and then,
If the antioxidant film 3 is removed by solvent treatment (phosphoric acid when the antioxidant film is SiN) and the oxide film 2 is removed by HF treatment, it is possible to form an NMOS element isolation using both LOCOS and a trench (FIG. 2). (F)).

【0021】[0021]

【発明の効果】LOCOS酸化膜の膜厚の薄膜化を利用
しているので、自己整合的にLOCOSによる分離領域
とトレンチによる分離領域とを形成でき、素子領域をき
めるフォトリソグラフィー工程が1度で良い。そのた
め、工程数が削減できるので、コストが低減できる。
Since the thinning of the LOCOS oxide film is utilized, the isolation region by the LOCOS and the isolation region by the trench can be formed in a self-aligning manner, and the photolithography process for determining the element region can be performed only once. good. Therefore, the number of steps can be reduced, and the cost can be reduced.

【0022】LOCOS酸化膜形成にポリバッファLO
COS法を用いた場合、狭い開口幅ではLOCOSの基
板側への酸化が少ないため、分離耐圧が低下するが、本
方法を適用すれば分離耐圧が低下することはない。LO
COS形成にサイドウォールLOCOS法を用いた場
合、Si開口幅が狭くなりLOCOSの薄膜化が起こり
易くなるが本方法を適用すればLOCOSの薄膜化によ
り分離特性が劣化することはない。
Poly buffer LO is used for forming the LOCOS oxide film.
When the COS method is used, since the LOCOS is less oxidized to the substrate side with a narrow opening width, the isolation withstand voltage is reduced, but the application of this method does not reduce the isolation withstand voltage. LO
When the sidewall LOCOS method is used for COS formation, the Si opening width is narrowed and the LOCOS is easily thinned. However, when this method is applied, the thinning of the LOCOS does not deteriorate the separation characteristics.

【0023】トレンチ分離法では、素子分離領域の広い
開口幅と狭い開口幅でトレンチ深さが等しいため、一度
に埋め込むのが困難である。しかしながら、本方法では
広い開口幅では、LOCOSがトレンチ底部に残るた
め、狭い開口部より、広い開口部の深さが浅くなり、従
来に比べて埋め込みが容易である。
In the trench isolation method, it is difficult to fill the trenches at once because the trench depth is the same in the wide and narrow openings of the element isolation region. However, in this method, since the LOCOS remains at the bottom of the trench with a wide opening width, the depth of the wide opening becomes shallower than that of the narrow opening, and the filling is easier than in the conventional case.

【図面の簡単な説明】[Brief description of drawings]

【図1】LOCOS酸化膜の膜厚とシリコン基板の開口
との関係を示す図である。
FIG. 1 is a diagram showing a relationship between a film thickness of a LOCOS oxide film and an opening of a silicon substrate.

【図2】本発明の形成方法の概略断面図である。FIG. 2 is a schematic cross-sectional view of the forming method of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 酸化防止膜 4 LOCOS酸化膜 5 トレンチ 6 酸化シリコン膜 1 Silicon Substrate 2 Oxide Film 3 Antioxidation Film 4 LOCOS Oxide Film 5 Trench 6 Silicon Oxide Film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 9274−4M H01L 21/94 A ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location 9274-4M H01L 21/94 A

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板上に酸化膜、酸化防止膜を
この順で形成し、次に素子分離領域形成予定部分及びト
レンチ形成予定部分の酸化膜及び酸化防止膜を基板が露
出するまで除去し、該基板を熱酸化することにより、前
記形成予定部分にロコス酸化膜を形成し、次に前記トレ
ンチ形成予定部分の基板が露出するまで選択的にロコス
酸化膜を異方性エッチングにより除去し、更にトレンチ
形成予定部分のシリコン基板を選択的に異方性エッチン
グして凹部を形成し、次に全面に酸化シリコンを堆積さ
せた後、エッチバック処理に付して酸化防止膜を露出さ
せた後、該酸化防止膜及び前記酸化膜を除去することに
よりトレンチと素子分子領域を同時に形成することを特
徴とする素子分離領域の形成方法。
1. An oxide film and an oxidation preventive film are formed in this order on a silicon substrate, and then the oxide film and the oxidation preventive film in the element isolation region formation planned portion and the trench formation planned portion are removed until the substrate is exposed. By thermally oxidizing the substrate, a locos oxide film is formed in the portion where the formation is to be formed, and then the locos oxide film is selectively removed by anisotropic etching until the substrate in the portion where the trench is to be formed is exposed. Further, the silicon substrate in the portion where the trench is to be formed is selectively anisotropically etched to form a concave portion, then silicon oxide is deposited on the entire surface, and then subjected to an etchback process to expose the antioxidant film. A method for forming an element isolation region, characterized in that the trench and the element molecule region are simultaneously formed by removing the antioxidant film and the oxide film.
JP21438393A 1993-08-30 1993-08-30 Forming method of element isolating region Pending JPH0766281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21438393A JPH0766281A (en) 1993-08-30 1993-08-30 Forming method of element isolating region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21438393A JPH0766281A (en) 1993-08-30 1993-08-30 Forming method of element isolating region

Publications (1)

Publication Number Publication Date
JPH0766281A true JPH0766281A (en) 1995-03-10

Family

ID=16654883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21438393A Pending JPH0766281A (en) 1993-08-30 1993-08-30 Forming method of element isolating region

Country Status (1)

Country Link
JP (1) JPH0766281A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016046513A (en) * 2014-08-22 2016-04-04 中美▲せき▼晶製品股▲ふん▼有限公司 Method of manufacturing wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016046513A (en) * 2014-08-22 2016-04-04 中美▲せき▼晶製品股▲ふん▼有限公司 Method of manufacturing wafer
CN106206250A (en) * 2014-08-22 2016-12-07 昆山中辰矽晶有限公司 wafer manufacturing method

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