JPH0763052B2 - Semiconductor crystal growth method - Google Patents

Semiconductor crystal growth method

Info

Publication number
JPH0763052B2
JPH0763052B2 JP57229441A JP22944182A JPH0763052B2 JP H0763052 B2 JPH0763052 B2 JP H0763052B2 JP 57229441 A JP57229441 A JP 57229441A JP 22944182 A JP22944182 A JP 22944182A JP H0763052 B2 JPH0763052 B2 JP H0763052B2
Authority
JP
Japan
Prior art keywords
crystal
growth
crystal growth
semiconductor single
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57229441A
Other languages
Japanese (ja)
Other versions
JPS59123221A (en
Inventor
昭男 吉川
勝 数村
一成 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57229441A priority Critical patent/JPH0763052B2/en
Publication of JPS59123221A publication Critical patent/JPS59123221A/en
Publication of JPH0763052B2 publication Critical patent/JPH0763052B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02387Group 13/15 materials
    • H01L21/02395Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02623Liquid deposition
    • H01L21/02625Liquid deposition using melted materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体結晶成長方法に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a semiconductor crystal growth method.

従来例の構成とその問題点 通常行なわれている半導体結晶成長方法の代表的なもの
として、液相エピタキシャル成長、気相エピタキシャル
成長がある。液相エピタキシャル成長においてはスライ
ドボード式がよく採用される。
Configuration of Conventional Example and Problems Thereof Liquid crystal epitaxial growth and vapor phase epitaxial growth are typical representatives of semiconductor crystal growth methods that are usually performed. The slide board method is often adopted in liquid phase epitaxial growth.

半導体結晶成長方法での問題点としては次の項目が挙げ
られる。
The problems with the semiconductor crystal growth method include the following items.

結晶成長係への望まれない不純物及びミクロン程度
の大きさのゴミの混入が避けにくく、又混入したものを
除去することが難しい。
It is difficult to avoid undesired impurities and dust particles of about micron size from entering the crystal growth member, and it is difficult to remove the mixed impurities.

特に液相エピタキシャル成長の場合、1μm以下の
膜厚を有する成長層の再現性の良い成長が難しい。
Particularly in the case of liquid phase epitaxial growth, it is difficult to grow a growth layer having a film thickness of 1 μm or less with good reproducibility.

メルトバックの問題がある。 There is a meltback problem.

以上の問題を解決する方法として、第1図に示されるよ
うな基板ホルダー1上の半導体単結晶成長板2と結晶成
長溶液3の間に結晶板4を置く方法が試みられている。
5は結晶成長溶液溜めとなるスライドボートである。矢
印は溶液スライド方向である。前途の問題点での不純
物やゴミを結晶板4に付着させて取り、しかも結晶板4
に結晶成長溶液3を覆い被せてエピタキシャル成長させ
ることにより過飽和度を調節し、問題点と共に問題点
をも解決しようとするものであるが、問題点〜を
十分解決したとは言えない。
As a method of solving the above problems, a method of placing a crystal plate 4 between a semiconductor single crystal growth plate 2 on a substrate holder 1 and a crystal growth solution 3 as shown in FIG. 1 has been attempted.
A slide boat 5 serves as a crystal growth solution reservoir. The arrow indicates the solution slide direction. Impurities and dust from the problems in the previous section are adhered to and removed from the crystal plate 4.
It is intended to adjust the degree of supersaturation by covering the crystal growth solution 3 with the crystal growth solution 3 and perform epitaxial growth to solve the problems as well as the problems, but it cannot be said that the problems (1) to (3) are sufficiently solved.

発明の目的 本発明は上記従来の問題点〜を全て解決することを
目的とするものである。
OBJECT OF THE INVENTION The present invention aims to solve all of the above-mentioned conventional problems.

発明の構成 上記目的を達成するため、本発明の半導体結晶成長方法
は、スライドボート式液相エピタキシャル成長法又は気
相エピタキシャル成長法において、半導体単結晶板の横
に、表面に段差や溝等の深さ0.5μm以上、ビッチ1μ
m以上の凹凸部を逆メサ状に有する結晶板を配置し、結
晶成長溶液又は結晶成長ガスを前記結晶板上を通過させ
た後前記半導体単結晶基板に達せしめるものである。
In order to achieve the above object, the semiconductor crystal growth method of the present invention is a slide boat type liquid phase epitaxial growth method or vapor phase epitaxial growth method, in the side of the semiconductor single crystal plate, the depth of steps and grooves on the surface. 0.5μm or more, bitch 1μ
A crystal plate having irregularities of m or more in an inverted mesa shape is arranged, and a crystal growth solution or a crystal growth gas is passed over the crystal plate and then allowed to reach the semiconductor single crystal substrate.

実施例の説明 以下、本発明の実施例について、図面に基づいて説明す
る。第2図にスライドボート方式による液相エピタキシ
ャル成長の実施例を示す。図において11は基板ホルダー
で、この基板ホルダー11上には半導体単結晶基板12と結
晶成長溶液13とそれらの間に結晶板14を設けてある。15
は前記結晶成長溶液溜めとなるスライドボートである。
前記半導体単結晶基板12及び結晶板14はGaAs基板で構成
している。ところで前記結晶板14の表面には深さ1.5μ
m,200μmピッチの段差14aを逆メサ形状に設てある。成
長温度は850℃で以下0.5℃/分の冷却速度で冷却して約
5℃の過飽和度をつけ、スライドボート5を第2図
(a)の矢印方向にスライドさせることにより結晶板14
上に結晶成長溶液13を10秒間被せ、その後更にスライド
させることにより、結晶成長溶液13を、半導体単結晶基
板12上に被せ、この要領で順次異なる結晶成長溶液をス
ライドさせて多層成長を行なった。結晶成長後、成長表
面を観察し、多層エピタキシャル層各層の膜厚を測定し
た。
Description of Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows an example of liquid phase epitaxial growth by the slide boat method. In the figure, 11 is a substrate holder, on which a semiconductor single crystal substrate 12, a crystal growth solution 13 and a crystal plate 14 are provided between them. 15
Is a slide boat that serves as the crystal growth solution reservoir.
The semiconductor single crystal substrate 12 and the crystal plate 14 are GaAs substrates. By the way, the surface of the crystal plate 14 has a depth of 1.5 μm.
Steps 14a with m and 200 μm pitch are provided in an inverted mesa shape. The growth temperature is 850 ° C. and is cooled at a cooling rate of 0.5 ° C./min or less to obtain a supersaturation degree of about 5 ° C., and the slide boat 5 is slid in the direction of the arrow in FIG.
The crystal growth solution 13 is coated on the top for 10 seconds and then further slid, so that the crystal growth solution 13 is coated on the semiconductor single crystal substrate 12, and in this manner, different crystal growth solutions are sequentially slid to perform multi-layer growth. . After crystal growth, the growth surface was observed and the film thickness of each layer of the multilayer epitaxial layer was measured.

第4図に代表的な結晶成長後の表面状態を示す。又次表
はそれらの表面状態を定量化したもので、全表面に占め
る鏡面成長の割合いを百分率で示した。又次表において
は各5ロットづつ調べた結果を示す。
FIG. 4 shows a typical surface condition after crystal growth. The following table is a quantification of their surface states, and the percentage of mirror growth on the entire surface is shown as a percentage. In addition, the following table shows the results of examining each of the 5 lots.

第4図(a)は平坦な結晶板を前置した場合、第4図
(b)は第4図(a)の結晶板の代りに段差を設けた結
晶板を置いた場合である。第4図において斜線部分がく
もり部分、白い部分が鏡面を示す。鏡面成長の割合いは
半導体単結晶基板に関しては、(a)に比べ(b)の方
が良いことがわかる。これに対して結晶板に関しては
(a)の方が良いが、(a)(b)共余り差はない。又
結晶板の段差の深さは0.5μm以上、ピッチ1μm以上
で小さいほど効果が大で、順メサと逆メサでは逆メサの
方が段差の効果が大きいということが他の実験より得ら
れている。以上より結晶板14に凹凸部を設けることによ
って半導体単結晶基板12上への成長の際の汚れを効果的
に取り除き得ることがわかった。又フォトルミネッセン
ス測定等により、第4図(b)の場合の半導体単結晶基
板12上の成長膜の方が強い発光を示すことも観測され、
望まれない不純物のゲッタリング効果も持つことが明ら
かとなった。又この成長では膜厚0.5μmの層を成長し
たが、そのときの膜厚のばらつきは第4図(a)の方法
で±0.2μm、第4図(b)の方法で±0.1μmと再現性
が向上した。更に半導体単結晶基板12上にも段差を設
け、結晶板14上への段差構造の有無に対するメルトバッ
クの影響を調べた。段差構造のある結晶板4を用いると
約3割メルトバック量が減り、それにつれてメルトバッ
ク後の形状の再現性及びその上へのエピタキシャル成長
層の形状の再現性が向上することが観察された。尚前記
結晶板14及び半導体単結晶基板12はGaAs基板で構成して
いるが、GaP,InP等の他の化合物半導体、Si,Ge等の半導
体を用いることも可能である。
FIG. 4 (a) shows the case where a flat crystal plate is placed in front, and FIG. 4 (b) shows the case where a stepped crystal plate is placed instead of the crystal plate shown in FIG. 4 (a). In FIG. 4, the shaded portion indicates the cloudy portion and the white portion indicates the mirror surface. It can be seen that the ratio of mirror growth is better in (b) than in (a) for the semiconductor single crystal substrate. On the other hand, regarding the crystal plate, (a) is better, but there is no difference between (a) and (b). Other experiments have shown that the smaller the step depth of the crystal plate is 0.5 μm or more and the pitch is 1 μm or more, the smaller the effect is. The reverse mesa has a greater effect on the step between the forward mesa and the reverse mesa. There is. From the above, it was found that by providing the crystal plate 14 with the concavo-convex portion, stains during growth on the semiconductor single crystal substrate 12 can be effectively removed. It was also observed by photoluminescence measurement that the growth film on the semiconductor single crystal substrate 12 in the case of FIG.
It has been revealed that it also has a gettering effect for unwanted impurities. In this growth, a layer having a film thickness of 0.5 μm was grown, and the variation in film thickness at that time was reproduced as ± 0.2 μm by the method of FIG. 4 (a) and ± 0.1 μm by the method of FIG. 4 (b). The property has improved. Further, a step was also provided on the semiconductor single crystal substrate 12, and the influence of meltback on the presence or absence of the step structure on the crystal plate 14 was examined. It was observed that when the crystal plate 4 having a step structure is used, the meltback amount is reduced by about 30%, and the shape reproducibility after the meltback and the shape reproducibility of the epitaxial growth layer thereon are improved accordingly. The crystal plate 14 and the semiconductor single crystal substrate 12 are GaAs substrates, but other compound semiconductors such as GaP and InP, and semiconductors such as Si and Ge can be used.

第3図に本発明の第2実施例としての気相エピタキシャ
ル成長法を示しており、図において21はサセプタ(基板
ホルダー)、22及び23はこのサセプタ21上に設けられた
半導体単結晶基板及び結晶板、24はこれを入れる石英反
応管、25はこの石英反応管24の一端に設けた結晶成長用
ガス流入口である。前記結晶板23はその表面に段差等の
凹凸部を有して結晶成長用ガス流入口23から流入するガ
スの流れ方向上手側に位置し、半導体単結晶板22は下手
側に位置する。のようにして構成して、前記結晶成長用
ガスが前記結晶板23上を通過した後、半導体単結晶板22
に達するようにしても前記第1実施例と同様の結果が得
られる。
FIG. 3 shows a vapor phase epitaxial growth method as a second embodiment of the present invention. In the figure, 21 is a susceptor (substrate holder), 22 and 23 are semiconductor single crystal substrates and crystals provided on the susceptor 21. A plate, 24 is a quartz reaction tube in which this is put, and 25 is a crystal growth gas inlet provided at one end of this quartz reaction tube 24. The crystal plate 23 has uneven portions such as steps on its surface and is located on the upstream side in the flow direction of the gas flowing in from the crystal growth gas inlet 23, and the semiconductor single crystal plate 22 is located on the lower side. As described above, after the crystal growth gas has passed over the crystal plate 23, the semiconductor single crystal plate 22
Even if it reaches, the same result as in the first embodiment can be obtained.

すなわち、結晶板23には、その表面に深さ2μm、4μ
m、ピッチの段差を逆メサ状に形成し、成長温度700
℃、全ガス流量2/分の結晶成長条件で気相成長を行
なった。その結果を第5図(a)に示す。半導体単結晶
基板22のほぼ全面にわたって良好な鏡面成長がなされて
いることがわかる。また、表面に凹凸のない平坦な結晶
板23を半導体単結晶基板22から見て、ガスの流れ方向の
上流側に置いた例について第5図(b)に示す。この場
合、半導体単結晶基板22の鏡面成長の割合は、第5図
(a)に比べて、減少している。
That is, the crystal plate 23 has a depth of 2 μm or 4 μm on its surface.
m, pitch steps are formed in an inverted mesa shape, and the growth temperature is 700
Vapor phase growth was performed under the conditions of a crystal growth condition of 0 ° C. and a total gas flow rate of 2 / min. The results are shown in Fig. 5 (a). It can be seen that good mirror surface growth is achieved over almost the entire surface of the semiconductor single crystal substrate 22. Further, FIG. 5B shows an example in which a flat crystal plate 23 having no surface irregularities is placed on the upstream side in the gas flow direction as viewed from the semiconductor single crystal substrate 22. In this case, the rate of mirror surface growth of the semiconductor single crystal substrate 22 is smaller than that in FIG. 5 (a).

また、結晶板23を置かない場合は、さらに鏡面成長がな
される割合、第5図(c)に示すように減少する。次表
において、第5図(a)〜(c)の各条件で各5ロット
づつ調べた結果を示す。
Further, when the crystal plate 23 is not placed, the rate of further mirror growth is reduced as shown in FIG. 5 (c). In the following table, the results of examining 5 lots each under the conditions of FIGS. 5 (a) to 5 (c) are shown.

前記より明らかなように、気体中の結晶成長材料に含ま
れる汚れや不純物が結晶板23で取り除かれ、その効果は
結晶板23表面に凹凸等の溝を設けることで、特に顕著で
ある。また、メサ形状は、順メサよりも逆メサの方が、
汚れを取り除く効果が大きいことがわかった。
As is clear from the above, the stains and impurities contained in the crystal growth material in the gas are removed by the crystal plate 23, and the effect is particularly remarkable by providing grooves such as irregularities on the surface of the crystal plate 23. In addition, the mesa shape of the reverse mesa is
It turned out that the effect of removing dirt was great.

発明の効果 本発明の半導体結晶成長方法は以上述べたように実施し
得るもので、結晶板に段差等の凹凸部(溝でも良い)を
設けることにより、半導体単結晶基板上への成長の際の
汚れを効果的に取り除き得る。又フォルトミネッセンス
測定等により、単結晶基板上の成長膜が強い発光を示す
ことが観測され、不純物のゲッタリング効果を持つこと
が判明した。更にメルトバック量も減り、メルトバック
後の形状の再現性及びその上へのエピタキシャル成長層
の形状の再現性が向上する。
EFFECTS OF THE INVENTION The semiconductor crystal growth method of the present invention can be carried out as described above, and by providing the crystal plate with uneven portions (such as grooves) such as steps, it is possible to grow the semiconductor crystal on a semiconductor single crystal substrate. It can effectively remove dirt. In addition, it was found that the grown film on the single crystal substrate showed strong luminescence by means of fault luminescence measurement, etc., and it was found to have an effect of gettering impurities. Further, the meltback amount is also reduced, and the reproducibility of the shape after the meltback and the reproducibility of the shape of the epitaxial growth layer thereon are improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は従来のスライドボート方式による液相エピタキ
シャル成長法を示す説明図、第2図(a)は本発明の第
1実施例におけるスライドボート方式による液相エピタ
キシャル成長法を示す説明図、同図(b)は同成長法に
用いる結晶板の平面図、第3図は本発明の第2実施例に
おける気相エピタキシャル成長法を示す説明図、第4図
(a)及び(b)並びに第5図(a)〜(c)は結晶成
長後の表面状態を示す説明図である。 11……基板ホルダー、12……半導体単結晶基板、13……
結晶成長溶液、14……結晶板、14a……段差、15……ス
ライドボート、21……サセプタ、22……半導体単結晶基
板、23……結晶板、24……石英反応管、25……結晶成長
用ガス流入口。
FIG. 1 is an explanatory view showing a conventional liquid phase epitaxial growth method by a slide boat method, and FIG. 2 (a) is an explanatory view showing a liquid phase epitaxial growth method by a slide boat method in the first embodiment of the present invention. b) is a plan view of a crystal plate used in the growth method, FIG. 3 is an explanatory view showing a vapor phase epitaxial growth method in a second embodiment of the present invention, FIGS. 4 (a) and (b) and FIG. 5 ( (a)-(c) is explanatory drawing which shows the surface state after crystal growth. 11 …… Substrate holder, 12 …… Semiconductor single crystal substrate, 13 ……
Crystal growth solution, 14 ... Crystal plate, 14a ... Step, 15 ... Slide boat, 21 ... Susceptor, 22 ... Semiconductor single crystal substrate, 23 ... Crystal plate, 24 ... Quartz reaction tube, 25 ... Gas inlet for crystal growth.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】スライドボード式液相エピタキシャル成長
法又は気相エピタキシャル成長法において、 半導体単結晶基板の横に、表面に段差や溝等の深さ0.5
μm以上、ビッチ1μm以上の凹凸部を逆メサ状に有す
る結晶板を配置し、結晶成長溶液又は結晶成長ガスを前
記結晶板上を通過させた後前記半導体単結晶基板に達せ
しめる半導体結晶成長方法。
1. A slide board type liquid phase epitaxial growth method or a vapor phase epitaxial growth method, wherein a depth of a step, a groove or the like on a surface of a semiconductor single crystal substrate is 0.5.
A semiconductor crystal growth method in which a crystal plate having concavities and convexities of μm or more and a bitch of 1 μm or more is arranged in an inverted mesa shape, and a crystal growth solution or a crystal growth gas is passed over the crystal plate and then reaches the semiconductor single crystal substrate. .
JP57229441A 1982-12-28 1982-12-28 Semiconductor crystal growth method Expired - Lifetime JPH0763052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57229441A JPH0763052B2 (en) 1982-12-28 1982-12-28 Semiconductor crystal growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57229441A JPH0763052B2 (en) 1982-12-28 1982-12-28 Semiconductor crystal growth method

Publications (2)

Publication Number Publication Date
JPS59123221A JPS59123221A (en) 1984-07-17
JPH0763052B2 true JPH0763052B2 (en) 1995-07-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP57229441A Expired - Lifetime JPH0763052B2 (en) 1982-12-28 1982-12-28 Semiconductor crystal growth method

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JPS5334465A (en) * 1976-09-10 1978-03-31 Sharp Corp Manufacture for semiconductor epitaxial grown layer
JPS5792598A (en) * 1980-11-26 1982-06-09 Fujitsu Ltd Unit for liquid-phase epitaxial growth

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