JP3142312B2 - Crystal growth method for hexagonal semiconductor - Google Patents
Crystal growth method for hexagonal semiconductorInfo
- Publication number
- JP3142312B2 JP3142312B2 JP03189108A JP18910891A JP3142312B2 JP 3142312 B2 JP3142312 B2 JP 3142312B2 JP 03189108 A JP03189108 A JP 03189108A JP 18910891 A JP18910891 A JP 18910891A JP 3142312 B2 JP3142312 B2 JP 3142312B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- crystal
- growth
- growing
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は可視発光ダイオードまた
は耐環境素子に使用する六方晶半導体の結晶成長方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for growing a hexagonal semiconductor used for a visible light emitting diode or an environment-resistant device.
【０００２】[0002]
【従来の技術】炭化珪素は広い禁制帯幅を持ち（２．２
〜３．３ｅＶ）、かつｐｎ接合やモス（ＭＯＳ）構造を
容易につくることができる。このため、高温動作素子、
大電力素子、放射線検出器、可視発光素子として期待が
なされている。しかし、工業的な生産が行えない理由
は、結晶成長が難しいという欠点があるためである。2. Description of the Related Art Silicon carbide has a wide band gap (2.2).
３3.3 eV), and a pn junction or a MOS (MOS) structure can be easily formed. For this reason, high-temperature operating elements,
It is expected to be used as a large power element, a radiation detector, and a visible light emitting element. However, industrial production cannot be performed because of the drawback that crystal growth is difficult.
【０００３】デバイスをつくるような高品質な結晶は単
結晶基板上にエピタキシャル成長を行うことにより得ら
れる。その方法としては、グラファイト坩堝中にＳｉ融
液を溜めた後、基板を該融液に浸し、坩堝から溶け出し
たカーボンを基板上に析出させるという液相成長（ＬＰ
Ｅ）法、及び、ＳｉとＣの水素化物または塩化物のガス
を基板上に導入し熱分解させ成長させる化学堆積（ＣＶ
Ｄ）法の２通りが主に行われている。しかし、これまで
ＣＶＤ法では発光素子として使用できる程度の結晶が得
られていない。これに対し、ＬＰＥ法ではたとえばＪｐ
ｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．，２６，Ｌ１８１５（１
９７９）に示されているように、螺旋転位による異常成
長が起こり表面モフォロジーが悪くなるという問題があ
った。このような結晶で作成したダイオードは通電中に
特性が劣化するといった問題があった。これを解決する
方法として特開昭６３−１７９５１６号に示されるよう
に基板の方向をずらした基板（以下オフ（ｏｆｆ）基板
と称す）を使うという方法が用いられていた。しかし、
この方法では図３に示すように、膜厚を厚く成長すると
表面に１方向のうねりができ、その後の製造プロセスで
電極パターンがきれいにできず、歩留りが悪かった。ま
た、オフ基板を切り出すとき、オフしない基板より一つ
のインゴットからとれる枚数が少なく、基板表面の研磨
も難しいなどの問題があった。また、結晶欠陥といった
観点から見てもオフ基板が得られるわけではなく、イン
クルージョンの様な大きな結晶欠陥に対しては、オフ基
板でない方が欠陥が広がらないことが判ってきた。[0003] High quality crystals, such as those used to make devices, can be obtained by epitaxial growth on a single crystal substrate. Liquid phase growth (LP) involves storing a Si melt in a graphite crucible, immersing the substrate in the melt, and depositing carbon dissolved from the crucible on the substrate.
E) method, and chemical deposition (CV) in which a hydride or chloride gas of Si and C is introduced onto a substrate and thermally decomposed and grown.
D) Two methods are mainly performed. However, a crystal that can be used as a light emitting element has not been obtained by the CVD method. On the other hand, in the LPE method, for example, Jp
n. J. Appl. Phys. , 26, L1815 (1
979), there has been a problem that abnormal growth due to screw dislocations occurs and surface morphology deteriorates. The diode made of such a crystal has a problem that the characteristics are deteriorated during energization. As a method for solving this problem, a method has been used in which a substrate whose direction is shifted (hereinafter referred to as an "off" substrate) is used as shown in JP-A-63-179516. But,
In this method, as shown in FIG. 3, when the film was grown to a large thickness, undulations were formed on the surface in one direction, and the electrode pattern could not be cleaned in the subsequent manufacturing process, resulting in poor yield. Further, when cutting off the substrate, there is a problem that the number of pieces that can be taken from one ingot is smaller than that of the substrate that is not turned off, and polishing of the substrate surface is difficult. Also, from the viewpoint of crystal defects, an off-substrate is not necessarily obtained, and it has been found that a defect which is not an off-substrate does not spread to a large crystal defect such as an inclusion.
【０００４】[0004]
【発明が解決しようとする課題】このように従来の成長
方法で成長した結晶は、基板表面のモフォロジーが悪
く、製品化を行ったとき歩留りを低下させる原因となっ
ていた。As described above, the crystals grown by the conventional growth method have poor morphology on the substrate surface, which causes a reduction in yield when commercialized.
【０００５】本発明は上記事情を考慮しなされたもの
で、その目的とするところは、ＳｉＣ結晶において、欠
陥の少なく表面モフォロジーの良好なＳｉＣ結晶の成長
方法を提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for growing a SiC crystal having few defects and good surface morphology.
【０００６】[0006]
【課題を解決するための手段】本発明の六方晶半導体の
結晶成長方法は、（０００１）面を有する六方晶基板を
用意する工程と、前記基板の主面に複数の凹凸部を形成
する工程と、これらの凹凸部が形成された前記主面に前
記基板と同じ結晶構造の単結晶を成長する工程とを備
え、この工程における単結晶の成長は、前記凹凸部の側
面から結晶を成長させることにより 、 前記凹凸部を埋め 、
さらに前記主面上に成長させることを特徴とするもので
ある。さらに、本発明の六方晶半導体の結晶成長方法に
おいては、前記凹凸部は前記主面に線状に形成されるこ
とを特徴とするものである。さらに、本発明の六方晶半
導体の結晶成長方法においては、前記単結晶は、ＧａＮ
あるいはＡｌＮからなることを特徴とするものである。According to the present invention, there is provided a method for growing a crystal of a hexagonal semiconductor, comprising the steps of: preparing a hexagonal substrate having a (0001) plane; and forming a plurality of irregularities on the main surface of the substrate. If, Bei and a step of growing a single crystal having the same crystal structure as the substrate to the main surface of these uneven portions are formed
For example, the growth of the single crystal in this step, by growing the crystal from the side surface of the concave-convex portion, it fills the uneven portion,
Further, it is characterized in that it is grown on the main surface. Furthermore, in the method for growing a crystal of a hexagonal semiconductor according to the present invention, the uneven portion is formed linearly on the main surface. Further, in the method for growing a hexagonal semiconductor crystal according to the present invention, the single crystal may be GaN.
Alternatively, it is characterized by being made of AlN.
【０００７】[0007]
【作用】六方晶半導体例えばＳｉＣにおいては、（００
０１）面が最も成長する速度が遅く、そのため成長面を
（０００１）面からずらすとずらした方向に非常に成長
しやすい。このため、従来（０００１）面から数度ずら
した面を使用して成長速度を高くして結晶成長を行って
いた。また、このような成長条件で行った結晶には欠陥
が少ないことが判っていた。しかし、このような成長で
は細かい（０００１）面のステップが多く存在し、これ
が表面モフォロジーを悪くする原因となっている。本発
明では（０００１）面からずらすことなく表面に溝を形
成し、溝の側面から、結晶を成長を行っている。このよ
うにすると、結晶は溝を埋めさらに成長する。また、こ
のようにして成長した結晶の表面は非常に平滑であるこ
とが発明者の実験結果で判った。In a hexagonal semiconductor such as SiC, (00
The (01) plane has the slowest growth rate, and therefore, if the growth plane is shifted from the (0001) plane, it is very easy to grow in the shifted direction. For this reason, crystal growth has been conventionally performed at a high growth rate using a plane shifted several degrees from the (0001) plane. It has also been found that crystals grown under such growth conditions have few defects. However, in such growth, many fine (0001) plane steps are present, which causes the surface morphology to deteriorate. In the present invention, grooves are formed on the surface without shifting from the (0001) plane, and crystals are grown from the side surfaces of the grooves. In this way, the crystal fills the trench and grows further. Further, it has been found from the experimental results of the inventor that the surface of the crystal thus grown is very smooth.
【０００８】なお、本発明は従来用いられているグラフ
エピタキシーといわれる方法とはまったく作用の異なる
ものである。グラフエピタキシーでは基板は成長結晶と
はまったく異なった別の結晶か、単結晶ではない基板を
用いて、その表面に水平方向のパターンを形成し、その
構造に沿ってまず優先核を成長させそれを種結晶として
成長をするものである。しかし本方法では優先核の成長
は起こらない。本発明ではＳｉＣにおいては〈０００
１〉方向とそれ以外の方向で結晶成長速度が異なること
を使用しているもので成長がもっとも遅い〈０００１〉
以外の方向に成長を行うようにしている。このようにす
ることにより、もっとも成長の遅い〈０００１〉方向に
垂直な（０００１）面が現れることを使用するものであ
る。従来のオフ基板を使用する方法でも成長速度の差を
利用するがこの場合成長しやすい（０００１）面は基板
の表面とはある角度を有している。このため、オフ基板
では基板の表面にうねりを生じることとなる。このよう
に、平滑な面をつくる為には、（０００１）面上に成長
を行わなくてはならない。本発明はこの（０００１）面
上に成長し、且つ成長速度の面依存性を利用するといっ
た従来互いに矛盾することを実現使用とするものであ
る。The operation of the present invention is completely different from that of a conventional method called graph epitaxy. In graph epitaxy, the substrate is a completely different crystal from the growth crystal or a substrate that is not a single crystal, a horizontal pattern is formed on the surface, first a preferential nucleus is grown along the structure, and It grows as a seed crystal. However, this method does not cause growth of priority nuclei. In the present invention, in SiC, <000
<0001>, which uses the fact that the crystal growth rate is different between the 1> direction and the other directions, and is the slowest growing
Growth in other directions. In this manner, the fact that a (0001) plane perpendicular to the <0001> direction in which growth is the slowest appears is used. A conventional method using an off-substrate also utilizes the difference in growth rate. In this case, the (0001) plane where growth is easy has a certain angle with respect to the surface of the substrate. For this reason, the off-substrate causes undulation on the surface of the substrate. Thus, in order to form a smooth surface, growth must be performed on the (0001) plane. The present invention realizes the conventional contradiction of growing on the (0001) plane and utilizing the plane dependence of the growth rate.
【０００９】[0009]
【実施例】以下、本発明の実施例について説明する。図
１に本発明に使用する基板を断面図で示す。基板１はア
チソン法で作製された基板を用い、（０００１）面に平
行に研磨する。その後、（１１２０）または（１１０
０）方向に表面をダイアモンドの針で表面に線を切るこ
とによって溝１１が形成された基板（０００１）面１ａ
が形成される。その後、Ｓｉ融液を溶媒とした液相エピ
タキシャル（ＬＰＥ）法により表面に結晶を成長させ
る。ＬＰＥの成長法は以下のように行う。まず、グラフ
ァイト製の坩堝にシリコンを収容し高周波で加熱する。
グラファイト坩堝には温度差を設け、低温部にＳｉＣ基
板を浸す。そして、成長温度は１６５０℃、成長雰囲気
はＡｒで行った。Embodiments of the present invention will be described below. FIG. 1 is a sectional view showing a substrate used in the present invention. The substrate 1 is a substrate manufactured by the Acheson method, and is polished in parallel with the (0001) plane. Then, (1120) or (110)
The substrate (0001) surface 1a in which the groove 11 is formed by cutting a line on the surface with a diamond needle in the 0) direction.
Is formed. Thereafter, crystals are grown on the surface by liquid phase epitaxy (LPE) using the Si melt as a solvent. The LPE growth method is performed as follows. First, silicon is accommodated in a graphite crucible and heated at high frequency.
A temperature difference is provided in the graphite crucible, and the SiC substrate is immersed in a low temperature part. The growth temperature was 1650 ° C., and the growth atmosphere was Ar.
【００１０】図２に、基板１上に溝１１を形成し５μｍ
程度に薄く成長させた時の表面写真を模写して示す。溝
の縁から成長した結晶は表面が非常に平滑であり、さら
に膜厚を厚くすると表面に何の模様も見られなくなっ
た。また、図３には基板主面に設けられた凹凸部のう
ち、凸部（畝）２１が前記図２におけると同様に示され
ている。これは、従来技術の（０００１）よりずらした
面上に成長させた時に比較して非常に表面状態の改善が
はかられた結果である。また、この結晶を用いることに
より製品の歩留りが大幅に改善された。Referring to FIG. 2, a groove 11 is formed on
A photo of the surface when grown to a small thickness is shown. The crystal grown from the edge of the groove had a very smooth surface, and when the film thickness was further increased, no pattern could be seen on the surface. FIG. 3 shows a projection (ridge) 21 among the projections and depressions provided on the main surface of the substrate, as in FIG. This is a result of greatly improving the surface state as compared with the case of growing on a plane shifted from (0001) of the prior art. In addition, the use of this crystal greatly improved the product yield.
【００１１】本発明は上記実施例に限らない。本実施例
では（０００１）面上にダイアモンドの針を用いて溝を
形成したが、溝はエッチング法により形成することもで
きる。特にこの場合溝の幅や成長する方位の制御が容易
になり、膜の制御が容易になる。また、このとき、反応
性イオンエッチング（ＲＩＥ）等の気相エッチング法を
用いることにより容易に溝の形を制御することができ、
その結果成長する結晶の特性も良くなる。The present invention is not limited to the above embodiment. In this embodiment, the groove is formed on the (0001) plane using a diamond needle, but the groove may be formed by an etching method. In particular, in this case, it is easy to control the width of the groove and the growing direction, and the control of the film is easy. At this time, the shape of the groove can be easily controlled by using a gas phase etching method such as reactive ion etching (RIE).
As a result, the characteristics of the grown crystal are improved.
【００１２】次に、前記本実施例では成長は液相法によ
って実施したが、昇華法のような気相法で成長した時も
単結晶化率の向上がはかられた。また、ＣＶＤ法に本発
明を用いた場合、結晶中の欠陥が大幅に低下することが
発明者等の研究により判明した。Next, in this embodiment, the growth was carried out by the liquid phase method. However, even when the growth was carried out by the gas phase method such as the sublimation method, the single crystallization ratio was improved. Further, when the present invention is used in the CVD method, it has been found from the studies by the inventors that the defects in the crystal are significantly reduced.
【００１３】また、溝の方向はどちらの方向に向いても
よいが、（１１２０）または（１１００）方向に刻んだ
ときが最もきれいな成長を行える。本発明は（０００
１）方向のＳｉ面、Ｃ面いずれの場合も同じ効果を有す
る。The direction of the groove may be any direction, but the finest growth can be achieved when the groove is cut in the (1120) or (1100) direction. The present invention provides (000
The same effect is obtained in both the Si plane and the C plane in the 1) direction.
【００１４】さらに、本発明を使用して成長する結晶は
ＳｉＣだけではない。結晶形が同じ六方晶溝造を有し、
格子定数の近い結晶を成長する時にも有効である。特
に、ＡｌＮ、ＧａＮは格子常数が近く、非常に有利であ
る。図４に本発明を用いＳｉＣ上にＧａＮのＭＩＳ発光
ダイオードを成長形成したものを例示する。図中、１は
ＳｉＣ基板で、その主面は溝が形成された（０００１）
面１ａである。前記（０００１）面にはＧａＮエピ層２
が形成され、これに設けられた一方の電極４ａと、前記
ＧａＮエピ層２にＺｎドープＧａＮ層３を介して設けら
れた他方の電極４ｂが夫々形成されている。この実施例
によって従来の発光ダイオードに比し発光光度が２倍を
超える発光ダイオードが得られた。なお、図中の６は電
極を導出するボンディングワイヤである。Further, the crystal grown using the present invention is not just SiC. The crystal form has the same hexagonal groove structure,
It is also effective when growing a crystal having a close lattice constant. In particular, AlN and GaN have very close lattice constants and are very advantageous. FIG. 4 illustrates an example in which a GaN MIS light emitting diode is grown and formed on SiC using the present invention. In the figure, reference numeral 1 denotes a SiC substrate, the main surface of which is formed with a groove (0001).
Surface 1a. The (0001) plane has a GaN epi layer 2
Are formed, and one electrode 4a provided thereon and the other electrode 4b provided on the GaN epi layer 2 via the Zn-doped GaN layer 3 are formed. According to this embodiment, a light emitting diode having a luminous intensity more than twice that of the conventional light emitting diode was obtained. Incidentally, reference numeral 6 in the figure denotes a bonding wire for leading out an electrode.
【００１５】その他、本発明はその主旨に反しない限り
種々変形して使用することができる。In addition, the present invention can be used in various modifications without departing from the gist thereof.
【００１６】[0016]
【発明の効果】本発明によれば、ＳｉＣ単結晶をＳｉＣ
等の六方晶基板上に成長させた場合に表面状態が悪くな
る欠点が解消され、発光効率のすぐれた発光ダイオード
が得られる。その結果製品の歩留まりが大幅に向上し、
従って、製品の製造原価が大幅に低下する顕著な効果が
ある。According to the present invention, a SiC single crystal is
And the like, the disadvantage that the surface condition is deteriorated when grown on a hexagonal substrate is eliminated, and a light emitting diode with excellent luminous efficiency can be obtained. As a result, the product yield has been greatly improved,
Therefore, there is a remarkable effect that the production cost of the product is greatly reduced.
【図１】本発明による基板の形状を説明するための断面
図。FIG. 1 is a sectional view for explaining the shape of a substrate according to the present invention.
【図２】溝上に５μｍ程度成長させた時の表面状態を示
す断面図。FIG. 2 is a cross-sectional view showing a surface state when the semiconductor device is grown on a groove by about 5 μm.
【図３】従来方法による成長の表面状態を示す図。FIG. 3 is a diagram showing a surface state of growth by a conventional method.
【図４】本発明によるＳｉＣ上を用いて形成されたＧａ
ＮのＭＩＳ発光ダイオードの断面図。FIG. 4 shows Ga formed on SiC according to the present invention.
Sectional drawing of N MIS light emitting diode.
１ ＳｉＣ基板 １ａ 溝が形成された（０００１）面 ２ ＧａＮエピ層 ３ ＺｎドープＧａＮ層 ４ Ａｌ電極 ５ ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 SiC substrate 1a (0001) surface with groove 2 GaN epi layer 3 Zn-doped GaN layer 4 Al electrode 5 Bonding wire
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/18 H01L 21/20 H01L 21/34 H01L 21/36 H01L 21/84 H01L 21/208 H01L 21/368 H01L 21/205 H01L 21/31 H01L 21/365 H01L 21/469 H01L 21/86 Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/18 H01L 21/20 H01L 21/34 H01L 21/36 H01L 21/84 H01L 21/208 H01L 21/368 H01L 21 / 205 H01L 21/31 H01L 21/365 H01L 21/469 H01L 21/86
Claims (3)
意する工程と、前記基板の主面に複数の凹凸部を形成す
る工程と、これらの凹凸部が形成された前記主面に前記
基板と同じ結晶構造の単結晶を成長する工程とを備え、
この工程における単結晶の成長は、前記凹凸部の側面か
ら結晶を成長させることにより 、 前記凹凸部を埋め 、 さら
に前記主面上に成長させることを特徴とする六方晶半導
体の結晶成長方法。1. A step of preparing a hexagonal substrate having a (0001) plane, a step of forming a plurality of uneven portions on a main surface of the substrate, and a step of forming the substrate on the main surface on which the uneven portions are formed. and a step of growing a single crystal having the same crystal structure as,
Growth of a single crystal in this step, by growing the crystal from the side surface of the concave-convex portion, fills the uneven portion, further
The hexagonal semiconductor crystal growth method characterized by growing on the principal surface to.
ることを特徴とする請求項１記載の六方晶半導体の結晶
成長方法。2. The method for growing a hexagonal semiconductor crystal according to claim 1, wherein said uneven portion is formed linearly on said main surface.
らなることを特徴とする請求項１記載の六方晶半導体の
結晶成長方法。3. The method of growing a hexagonal semiconductor according to claim 1, wherein the single crystal is made of GaN or AlN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03189108A JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03189108A JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536602A JPH0536602A (en) | 1993-02-12 |
| JP3142312B2 true JP3142312B2 (en) | 2001-03-07 |
Family
ID=16235507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03189108A Expired - Lifetime JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3142312B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201262B1 (en) * | 1997-10-07 | 2001-03-13 | Cree, Inc. | Group III nitride photonic devices on silicon carbide substrates with conductive buffer interlay structure |
| US6335546B1 (en) | 1998-07-31 | 2002-01-01 | Sharp Kabushiki Kaisha | Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device |
| JP3201475B2 (en) | 1998-09-14 | 2001-08-20 | 松下電器産業株式会社 | Semiconductor device and method of manufacturing the same |
| KR100568300B1 (en) * | 2004-03-31 | 2006-04-05 | 삼성전기주식회사 | Nitride semiconductor light emitting diode and method of producing the same |
| JP6040866B2 (en) * | 2013-05-29 | 2016-12-07 | トヨタ自動車株式会社 | Method for producing SiC single crystal |
-
1991
- 1991-07-30 JP JP03189108A patent/JP3142312B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0536602A (en) | 1993-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6380051B1 (en) | Layered structure including a nitride compound semiconductor film and method for making the same | |
| US5915194A (en) | Method for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereon | |
| EP1258544B1 (en) | Compound crystal and method of manufacturing same | |
| JP5531983B2 (en) | Method for manufacturing group III-V nitride semiconductor substrate | |
| JP5323792B2 (en) | Method for manufacturing gallium nitride semiconductor structure, method for manufacturing semiconductor structure, and semiconductor structure | |
| JP4651207B2 (en) | Semiconductor substrate and manufacturing method thereof | |
| JP2005101475A (en) | Iii-v group nitride semiconductor substrate and method for manufacturing the same | |
| JP2001122693A (en) | Ground substrate for crystal growth and method of producing substrate using the same | |
| JPH11162847A (en) | Semiconductor substrate and formation thereof | |
| CA2747574A1 (en) | Manufacturing of low defect density free-standing gallium nitride substrates and devices fabricated thereof | |
| JPH06105797B2 (en) | Semiconductor substrate and manufacturing method thereof | |
| US6461944B2 (en) | Methods for growth of relatively large step-free SiC crystal surfaces | |
| JP3127624B2 (en) | Method for growing heteroepitaxial layer | |
| JP4664464B2 (en) | Silicon carbide single crystal wafer with small mosaic | |
| JP3142312B2 (en) | Crystal growth method for hexagonal semiconductor | |
| KR100450781B1 (en) | Method for manufacturing GaN single crystal | |
| KR20030019151A (en) | Method for preparing compound single crystal | |
| JPH07131067A (en) | Method for manufacturing silicon carbide wafer and method for manufacturing silicon carbide light emitting diode element | |
| EP1122341A1 (en) | Single crystal SiC | |
| US4218270A (en) | Method of fabricating electroluminescent element utilizing multi-stage epitaxial deposition and substrate removal techniques | |
| JP2004035360A (en) | GaN SINGLE CRYSTAL SUBSTRATE, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, AND ITS MANUFACTURING METHOD | |
| JP2677221B2 (en) | Method for growing nitride-based III-V compound semiconductor crystal | |
| KR19980072406A (en) | Gallium nitride substrate for light emitting device and manufacturing method thereof | |
| Yang et al. | Improvement of GaN layer quality by using the bulk-GaN buffer structure grown by metalorganic chemical vapor deposition | |
| JP3560180B2 (en) | Method for producing ZnSe homoepitaxial single crystal film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071222 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081222 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091222 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091222 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101222 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111222 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111222 Year of fee payment: 11 |