JPH0760993B2 - Comparator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a comparator for determining whether the voltage of an input signal is higher or lower than a preset reference voltage,
In particular, the present invention relates to a comparator including a transistor differential amplifier circuit with positive feedback.

[Prior Art] FIG. 3 shows a conventional comparator of this type.

In the drawing, 1 and 2 are input signal terminals, 3 and 4 are clock signal input terminals, 5 and 6 are output signal terminals, and 7 is a power supply terminal.
Further, 10 and 13 are transistors that form a differential amplifier circuit (hereinafter referred to as comparison transistors), 11 and 12 are transistors that form a differential amplifier circuit with positive feedback (hereinafter, referred to as
Latch transistor). Based on the clock signals from the clock signal input terminals 3 and 4, the transistors 14 and 15 are differential circuits which switch the current from the constant current source 30 to either the comparison transistor 10 or 13 or the latch transistor 11 or 12. It constitutes an amplifier circuit.

The transistors 14 and 15 switch between the following two modes depending on the polarity of the voltage of the clock signal applied to the clock signal input terminals 3 and 4.

When the voltage of the clock signal applied to the terminal 3 is higher than that of the terminal 4, a current flows through the transistor 14 and the differential amplifier circuit of the comparison transistors 10 and 13 operates, and the differential amplifier of one of the latch transistors 11 and 12 operates. The amplifier circuit does not work. Therefore, at this time, a voltage corresponding to the voltage of the input signal applied to the input signal terminals 1 and 2 is obtained across the load resistors 40 and 41 (comparison mode).

Next, when the voltage of the clock signal applied to the terminal 3 becomes lower than that of the terminal 4, a current flows through the transistor 15 and the differential amplifier circuits of the latch transistors 11 and 12 operate to differentially amplify the differential transistors of the comparison transistors 10 and 13. The circuit does not work (latch mode).

At the moment of switching to the latch mode, load resistance 40,4
Since the voltage across 1 is stored in the collector capacitance of each transistor 10-13, the maximum amplitude voltage in the polarity determined in the previous comparison mode is the output signal terminal 5,6.
Can be obtained.

[Problems to be Solved] In the conventional comparator described above, when the voltage between the input signal terminals 1 and 2 is gradually changed while the high-speed clock signal of several tens MHz is applied, the output signal terminal 5, There was a problem that hysteresis occurred in the change of the output voltage between 6 and high-precision voltage comparison could not be performed.

This problem will be described in more detail with reference to the hysteresis characteristic diagram of FIG.

In the drawing, point G is used as a reference voltage, and when the input voltage is lower than the voltage value at point G, the output voltage should be low, and when it is high, the output voltage should be high. However,
If the input voltage is changed to the area B once after reaching the area C, the output voltage remains low until it reaches the point F even if it exceeds the point G, and the output voltage remains high for the first time in the area D. Becomes Further, when the input voltage is changed from the D region to the A region, the output voltage is kept high until it reaches the E point even if it exceeds the G point. The widths E to F of the hysteresis become wider as the frequency of the clock signal becomes faster. As a result, it becomes impossible to perform highly accurate voltage comparison with the high-speed clock signal.

The present invention has been made in consideration of the above problems,
An object of the present invention is to provide a comparator capable of performing highly accurate comparison operation even at high speed operation.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first transistor differential amplifier circuit and positive feedback from the collector of each transistor to the base of a pair of transistors via an independent emitter floor. And a third transistor differential amplifier circuit in which the current from the constant current source is switched and supplied to either one of the first and second transistor differential amplifier circuits based on the clock signal. And a pair of collectors in the first and second transistor differential amplifier circuits are respectively connected to a common load resistor to form a comparison circuit, and the comparison circuit is cascaded in plural stages. Connect the load resistance in each comparison circuit in the first stage on the input side to 2 / of the load resistance in each comparison circuit in the second and subsequent stages.
In addition to setting the resistance value to 3 or less, connect a transistor with the collector and base shorted between the common connection point of the load resistance of the input side first stage comparison circuit and the power supply line, and input side first stage comparison circuit. The voltage applied to the load resistance at is smaller than the voltage applied to the load resistance in the second and subsequent comparison circuits by the voltage drop of the added transistor, and the phase of the clock signal is odd and even. It is configured in reverse phase with.

EXAMPLES Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a partial configuration of the embodiment. In addition,
The same or corresponding portions as those in FIG. 3 shown above are designated by the same reference numerals, and detailed description thereof will be omitted.

In the drawing, 20 and 23 are transistors (hereinafter referred to as comparison transistors) that form a differential amplifier circuit, and
It corresponds to 3 comparison transistors. Reference numerals 21 and 22 denote transistors (hereinafter, referred to as latch transistors) that form a differential amplifier circuit with positive feedback, and correspond to the latch transistors 11 and 12. The transistors 24 and 25 are differential amplifier circuits in which the current from the constant current source 33 is switched to flow to either one of the comparison transistors 20 and 23 or the latch transistors 21 and 22 based on the clock signal from the clock signal input terminals 3 and 4. Consists of 1
It corresponds to 4,15 transistors.

That is, the comparator of the present embodiment has a configuration in which a comparison circuit including a comparison transistor, a latch transistor, a transistor for switching the differential amplifier circuit, and a member associated therewith is connected in two stages. That is, the first-stage comparison circuit (hereinafter simply referred to as the second stage) 200 is connected to the comparison transistors 20 and 23, and the bases of the transistors 24 and 25 are connected to the clock signal input terminals 3 and 4, respectively. In addition, a voltage is applied to the load resistors 42 and 43 from another power supply terminal 8.

Here, the load resistance 40, 41 of the first stage 100 is set to a small resistance value of 2/3 or less of the load resistance 42, 43 of the second stage 200, and conversely the load of the second stage 200 is set. The resistors 42 and 43 are set to large resistance values so that a standard voltage amplitude can be obtained. The voltage applied to the load resistors 40 and 41 of the first stage 100 is set to a value smaller than the voltage applied to the load resistors 42 and 43 of the second stage 200. Furthermore, the transistors 14 and 15 and the transistors 24 and 25 are connected so that the applied clock signals have opposite phases.

In the comparator having the above-described configuration, the clock signals applied to the first stage 100 and the second stage 200 have opposite phases, so that the voltage of the clock signal applied to the terminal 3 is higher than that of the terminal 4. In this case, the first stage 100 is the comparison mode and the second stage is the latch mode. On the other hand, when it is low, the first stage 100 is in the latch mode and the second stage 200 is in the comparison mode.

In such a comparator, when the first stage 100 is in the latch mode, the voltage amplitude obtained across the load resistors 40, 41 having a small value is small, but the load resistors 42, 43 of the second stage 200 are small. If is set to a large value such that a standard voltage amplitude can be obtained, the voltage obtained at the output signal terminals 5 and 6 of the second stage 200 in the comparison mode can be made sufficiently large.

Further, as a result of making the load resistances 40 and 41 of the first stage 100 small, the time constants determined by these resistance values and the collector capacitances of the comparison transistors 10 and 13 and the latch transistors 11 and 12 become small, so The width of hysteresis can be narrowed. This will be described in more detail with reference to FIG.

FIG. 5 shows the relationship between the output waveform and the clock signal waveform when the conventional comparator shown in FIG. 3 is operated with the voltage applied to the input signal terminals 1 and 2 being sufficiently small. In the figure, (a) shows the case where the frequency of the clock signal is low, and (b) shows the case where the frequency of the clock signal is high.

In the drawing, when the clock signal P is low, it operates in the comparison mode, and when it is high, it operates in the latch mode.

Then, when the frequency of the clock signal is low (FIG. 5 (a)), there is a steady section as shown in FIG. In this section, the discharge section due to the time constant determined by the resistance values of the load resistors 40 and 41 and the collector capacitances of the comparison transistors 10 and 13 and the latch transistors 11 and 12 has passed sufficiently. The output signal O having a voltage proportional to the applied voltage is output.

However, when the frequency of the clock signal P is high (FIG. 5 (b)), the discharge is not yet sufficiently performed in the section shown by I, and therefore the voltage of the output signal O is not proportional to the input voltage, It depends on the polarity of the voltage during the latch operation.

In other words, for a small input voltage, if the discharge interval due to the time constant determined by the resistance values of the load resistors 40 and 41 and the collector capacitances of the comparison transistors 10 and 13 and the latch transistors 11 and 12 does not pass enough, A voltage proportional to is not obtained at the output signal terminals 5 and 6. However, when the frequency of the clock signal P is high, the level of the clock signal P changes before passing through the discharge section, and eventually a stable output signal cannot be obtained.

Therefore, in the present embodiment described above, the time constant is reduced by reducing the resistance value of the load resistors 40 and 41, and as a result, the width of the discharge section, that is, the width of the hysteresis is narrowed, and even if the clock signal has a high frequency. It was possible to obtain an accurate output signal.

FIG. 2 is a circuit diagram showing a comparator according to an embodiment of the present invention.

In this embodiment, a preamplifier 101 composed of transistors 51 to 54 is added to the input side of the comparator shown in FIG. 1, and transistors 16 and 1 are added to the comparator circuits 100 and 200 of each stage.
7, 26, 27 and an emitter floor composed of constant current sources 31, 32 or 34, 35 are added.

Preamplifier 101 composed of the transistors 51 to 54
Amplifies the voltage applied to the input signal terminals 1 and 2 and outputs it to the first stage 100. Therefore, the width of the hysteresis when evaluated at the input point becomes smaller by the gain of the preamplifier 101. In addition, transistors 16, 17, 26, 2
7 and the emitter floor consisting of the constant current sources 31, 32 or 34, 35 are added, the latch transistors 11, 12
Or the collector-base voltage of 21,22 becomes large,
As a result, the collector capacitance is reduced, the time constant is further reduced, and the width of hysteresis during operation of the high-speed clock signal can be reduced.

Furthermore, in the present embodiment, the power source terminal is designated by the reference numeral 7.
Only the number of the load resistors 40 and 41 is made common, and a voltage is dropped by the transistor 50 and applied to the common connection point of the load resistors 40 and 41.

In addition, in the first stage 100 and the second stage 200, the clock signals are applied in opposite phases, and the load resistors 40 and 41 are connected to the load resistor 4
The configuration such that the resistance value is 2/3 or less of 2,43 is the same as that shown in FIG.

The present invention is not limited to the above embodiment. For example, a comparator circuit having the same configuration as the second-stage comparator circuit may be further connected in one or more stages.

[Effects of the Invention] As described above, according to the present invention, the plurality of stages of the comparison circuits are connected in series, and the load resistance in the first stage comparison circuit on the input side is equal to the load resistance in each of the second and subsequent comparison circuits. By setting the resistance value to 2/3 or less, and decreasing the time constant in the input side comparison circuit, the discharge at the time of switching from the latch mode to the comparison mode is performed rapidly, and an accurate voltage proportional to the input voltage is promptly output. Since it is possible to output to, there is an effect that a highly accurate comparison operation can be performed even at a high speed operation.

Also, since the load resistance in the second and subsequent comparison circuits is set to a large value, the logic amplitude of the final output can be increased to a general level, so the parallel type A / D
Even when applied to a device that logically processes the logical output of a comparator such as a converter, it is possible to obtain the effect that a system that is sufficiently robust against external noise and the like can be configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a partial configuration of an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a comparator according to an embodiment of the present invention, FIG. 3 is a circuit diagram showing a conventional comparator, FIG. 4 is a hysteresis characteristic diagram of the comparator, and FIG. 5 (a) is a clock signal. FIG. 5B is a voltage waveform diagram when the frequency is low, and FIG. 5B is a voltage waveform diagram when the frequency of the clock signal is high. 1,2: Input signal terminal 3,4: Clock input terminal 5,6: Output signal terminal, 7,8: Power supply terminal 10,13: Comparison transistor 11,12: Latch transistor 14,15: Transistor 16,17: Transistor 20,23: Comparison transistor 21,22: Latch transistor 24,25: Transistor 26,27: Transistor 30 to 38: Constant current source, 40 to 43: Load resistance 50 to 54: Transistor 100: First stage comparison circuit 200: Second stage comparison circuit 101: Preamplifier

Claims (1)

[Claims] 1. A first transistor differential amplifier circuit, and a second transistor differential amplifier circuit in which positive feedback is applied from the collector of each transistor to the base of a pair of transistors via an independent emitter floor. A third transistor differential amplifier circuit for switching and flowing a current from a constant current source to either one of the first and second transistor differential amplifier circuits based on a clock signal; A pair of collectors in the differential amplifier circuit are connected to a common load resistor to form a comparison circuit, and the comparison circuits are connected in multiple stages to connect the load in each comparison circuit in the first stage of the input side. Set the resistance to 2/3 or less of the load resistance in each comparison circuit from the second stage onward, and connect the common connection point of the load resistance of the comparison circuit in the first stage on the input side to the power supply line. , A transistor with a shorted collector and base is connected, and the voltage applied to the load resistance in the input side first stage comparison circuit is added more than the voltage applied to the load resistance in each of the second and subsequent stage comparison circuits. A comparator characterized in that the value is made smaller by the voltage drop of the transistor and the phase of the clock signal is made opposite in odd and even stages.