JPH0752715B2 - Method for forming polycrystalline silicon thin film - Google Patents

Description

The present invention relates to an improved method for forming a polycrystalline silicon thin film, and more particularly to a method for forming a polycrystalline silicon thin film that constitutes a semiconductor device such as a field effect thin film transistor. Regarding improvement.

<Prior Art> In recent years, a polycrystalline silicon thin film has been actively researched for use as an active region of an SOI device or for application to a thin film transistor of a liquid crystal display device. In these applications, not only when a polycrystalline silicon thin film is used as an active layer, but when it is used as a gate electrode, from the viewpoint of facilitating termination of dangling bonds due to hydrogenation to an active region immediately below the gate electrode, It is required to manufacture polycrystalline silicon having a small number of dangling bonds per unit area, that is, having a large grain size.

In order to achieve the above object, there is a first method of forming polycrystalline silicon so that the grain size becomes large when the polycrystalline silicon is deposited using ions or the like. But this first
Method has problems in throughput, cost and quality, and is not suitable for practical use.

Therefore, the non-single-crystal silicon deposited on the substrate is subjected to accelerated implantation of silicon ions to modify the internal structure into a completely amorphous structure, and then thermal annealing is performed to cause solid phase growth of silicon for crystallization. A second method of forming polycrystalline silicon has been developed.

<Problems to be Solved by the Invention> In the above-described second method, the implantation of silicon ions is performed over the entire surface of the non-single-crystal silicon to completely amorphize it, so that there is no recrystallization nucleus. Therefore, when crystallizing the entire surface of the non-single-crystal silicon, the solid-phase growth temperature is required to be 600 ° C. or higher by relying on a thermal process for nucleation of recrystallization. Therefore, for example, with the increase in screen size of liquid crystal displays,
Even if you want to use a cheaper glass substrate instead of fused quartz for the display substrate, the strain point temperature of the glass is 550 ~ 6
Since it is 00 ° C., which is lower than the solid phase growth temperature, there is a problem that a low-cost substrate cannot be used as a transparent substrate of a thin film transistor using polycrystalline silicon.

Further, since the position of the recrystallized nucleus cannot be artificially controlled, the grown crystal grains are in contact with each other, and there is a limit in increasing the grain size of the polycrystalline silicon. There is a problem of non-uniformity and poor reproducibility.

<Means for Solving Problems> The present invention has been made to solve the above-mentioned problems, and is to use polycrystalline silicon having a large grain size under a low temperature process.
Provided is a method for forming a polycrystalline silicon thin film capable of forming an in-plane grain size distribution uniformly and with good reproducibility.

A method of forming a polycrystalline silicon thin film according to the present invention comprises a step of forming a polycrystalline silicon thin film on a substrate, a step of forming dot-shaped mask patterns having a constant interval on the polycrystalline silicon thin film, and the dot-shaped mask. A step of implanting silicon ions into the polycrystalline silicon thin film using the pattern as a mask to form an amorphous silicon layer; and the amorphous silicon using the polycrystalline silicon thin film under the dot-shaped mask pattern as a recrystallization nucleus. And a step of performing solid phase growth of the layer.

Further, in the method for forming a polycrystalline silicon thin film according to the present invention, the cross-sectional shape of the dot-shaped mask pattern is pseudo-conical.

<Operation> As in the present invention, during the process of implanting silicon ions into polycrystalline silicon to make it amorphous and then crystallizing the amorphous layer by annealing to form polycrystalline silicon, By selectively performing the ion implantation to be performed, it is possible to leave a recrystallization nucleus at a desired position in the amorphous layer. Therefore, annealing non-single-crystal silicon that has undergone such ion implantation promotes only crystallization centered on localized recrystallization nuclei, has a uniform in-plane distribution, and has a large grain size. It is possible to form a silicon thin film with good reproducibility.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following examples.

FIG. 1 is a sectional view showing the structure of this embodiment. As shown in FIG. 1, a thermal oxide film 2 having a film thickness of 400 nm is formed on a p-type {100} silicon substrate 1, and a polycrystalline silicon thin film 3 is further formed.
Is formed with a film thickness of 100 nm. At this time, the polycrystalline silicon thin film 3 is formed by a vacuum deposition method under the conditions of a substrate temperature of 45.
The temperature is 0 ° C, the degree of vacuum is 5 × 10 ^-5 Pa, and the film formation rate is 10 nm / min. Then, S is formed on the polycrystalline silicon thin film 3 by the atmospheric pressure CVD method.
Form an iO ₂ film. The SiO ₂ film is formed to have a film thickness of 250 nm at a substrate temperature of 420 ° C. using monosilane and oxygen as source gases.

Then, a photoresist is deposited on the SiO ₂ film, and a dot-shaped resist pattern having a diameter of 0.5 μm and an interval of 0.6 μm is formed by the photolithography method. Using the resist pattern as a mask, the SiO ₂ film is etched with buffered hydrofluoric acid (1%) to form a SiO ₂ pattern 4, and then the resist pattern is peeled off. At this time, an overetching condition is set as an etching condition to obtain a pseudo-conical SiO ₂ pattern 4 as shown in FIG.

Then, using the SiO ₂ pattern 4 as a mask, the polycrystalline silicon thin film 3 is irradiated with 1 silicon ion at an acceleration voltage of 130 KeV.
× 10 ¹⁵ / cm ² injected, further silicon ions 1 × 10 ¹⁵ pieces under the same conditions the silicon substrate 1 is rotated several degrees / cm ² injected. Since the ion implantation apparatus used here is designed to hold the substrate at an inclination of about 7 degrees with respect to the ion incident direction, by rotating the substrate as described above, channeling can be avoided, and The polycrystalline silicon thin film 3 can be completely amorphized except just under the center of the pseudo-cone.

Then, after completely removing the SiO ₂ pattern 4 with hydrofluoric acid (2.5%), furnace annealing at 550 ° C. for 90 hours in a nitrogen atmosphere was performed to remove the region directly below the pseudo-cone and not ion-implanted. As a nucleus, the amorphous silicon thin film 3 is recrystallized.

A sample based on this example manufactured as described above is used as a sample A, and in order to compare with the sample A, silicon ions are added to the polycrystalline silicon thin film 3 without forming the SiO ₂ pattern 4 serving as a mask at the time of ion implantation. A sample (Sample B) which was annealed after the implantation and a sample (Sample C) in which the polycrystalline silicon thin film 3 was not subjected to any treatment such as ion implantation and annealing were prepared. At this time,
Other steps are performed in the same manner as in this embodiment.

FIG. 2 shows the samples A, B and C which were subjected to X-ray diffraction,
It shows the diffraction intensity from the 3 {111} plane of polycrystalline silicon at that time. As is apparent from the figure, the diffraction intensity of the sample A according to the present embodiment reaches 10 times the diffraction intensity of the sample C which has not been subjected to any treatment such as ion implantation and annealing. The crystal grain size is growing large. No diffraction peak is observed in the sample B in which the ion implantation mask is not formed, and the polycrystalline silicon thin film 3 which has been made amorphous by the ion implantation hardly recrystallizes.

FIG. 3 shows the results of measuring the particle sizes of the samples A, B and C by a transmission electron microscope. As is clear from FIG. 3, the sample A based on this example has a significantly larger particle size and a smaller particle size dispersion than the samples B and C.

FIG. 4 shows the measurement results of the Raman scattering spectra of the above samples A and C. For comparison, a spectrum of single crystal silicon (D in the figure) is also added. As is clear from FIG. 4, the spectrum from the sample A according to the present example is closer to single crystal silicon in both peak position and peak shape, as compared with the sample C which is not subjected to any treatment such as ion implantation and annealing. It can be seen that the grain size of the sample A is larger than that of the sample C.

Furthermore, in order to investigate the electrical characteristics of the polycrystalline silicon thin film 3, ″ B ⁺ was injected at 1 × 10 ¹⁴ pieces / cm ² at an acceleration voltage of 15 KeV, and 5
After performing an activation heat treatment at 50 ° C. for 1 hour, the resistivity of the polycrystalline silicon thin film 3 was measured. This was carried out for sample A based on this example and sample C which was not subjected to any treatment such as ion implantation or annealing, and the results are shown in FIG. As is apparent from FIG. 5, the resistivity of the sample A according to this example is 5 × 10 ⁻² Ω · cm, which is about 1 of the resistivity of the sample C which has not been subjected to any treatment such as ion implantation or annealing. It has decreased to / 100, suggesting a decrease in dangling bonds in polycrystalline silicon.

The experiments shown in FIGS. 2 to 5 confirmed that a polycrystalline silicon thin film having a large grain size and an in-plane uniform grain size distribution could be formed by this example.

In the present embodiment, when the silicon ions were implanted into the polycrystalline silicon thin film 3, the ion acceleration voltage and the ion implantation amount were set to 130 KeV and 1 × 10 ¹⁵ ions / cm ² , respectively, but the present invention is not limited to this. Instead, any ion acceleration voltage and ion implantation amount may be applied as long as they can completely amorphize a region other than a very small region directly below the SiO ₂ pattern.

Further, in the above-described embodiment, when the amorphous silicon thin film 3 is annealed, solid-phase grown and recrystallized, the annealing temperature is set to 550 ° C. and the annealing time is set to 90 hours. The present invention is not limited to this, and in the amorphous layer formed by the previous step of ion implantation, a polycrystalline silicon thin film which is amorphized within a range where new nucleation cannot be performed mainly by a thermal process. 3 Any annealing temperature and annealing time may be applied as long as they are recrystallized over the entire surface.

<Effects of the Invention> As described above, according to the present invention, a polycrystalline silicon thin film having a large grain size and a small number of dangling bonds is formed on an amorphous insulating substrate with uniform grain size distribution and good reproducibility. It becomes possible to do.

Therefore, when a thin film transistor is formed by using the polycrystalline silicon thin film according to the present invention as an active layer, carrier mobility can be improved, threshold voltage can be reduced, and these characteristics can be made uniform. When used as a gate electrode material,
Since hydrogenation of the active layer can be carried out extremely efficiently, a device further utilizing the above characteristics can be formed. In addition, since the polycrystalline silicon according to the present invention has a high impurity activation rate, a low resistivity is realized, and when used as a wiring material, the speed of a semiconductor device can be increased. Considering application to a liquid crystal display, since it has high carrier mobility, it becomes possible to incorporate a drive circuit such as a shift register.

Also, by making the cross-sectional shape of the dot-shaped mask pattern into a pseudo-conical shape, it is possible to confine the re-growth nuclei to a finer area below the mask pattern resolution. Thus, a uniform particle size distribution can be obtained.

Thus, when a polycrystalline silicon thin film is formed by using the present invention, its application range is widened and the characteristics of a semiconductor device formed by using this thin film can be improved. large.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, FIG. 2 is a comparison diagram of diffraction intensity from a silicon {111} plane by X-ray diffraction, and FIG. 3 is a comparison diagram of particle size dispersion. FIG. 4 is a comparison diagram of Raman scattering spectrum intensity with respect to wave number, and FIG. 5 is a comparison diagram of electrical resistivity. 1: p-type silicon substrate, 2: thermal oxide film, 3: polycrystalline silicon thin film, 4: SiO ₂ pattern

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-170518 (JP, A) JP-A-60-143624 (JP, A) JP-A-60-164316 (JP, A)

Claims (2)

[Claims] 1. A step of forming a polycrystalline silicon thin film on a substrate, a step of forming dot-shaped mask patterns having a constant interval on the polycrystalline silicon thin film, and the step of forming the polycrystalline mask using the dot-shaped mask pattern as a mask. A step of implanting silicon ions into the crystalline silicon thin film to form an amorphous silicon layer, and solid phase growth of the amorphous silicon layer using the polycrystalline silicon thin film under the dot-shaped mask pattern as a recrystallization nucleus A method of forming a polycrystalline silicon thin film, comprising the steps of: 2. The cross-sectional shape of the dot-shaped mask pattern is a pseudo-conical shape.
Item 6. A method for forming a polycrystalline silicon thin film according to item.