JP2872425B2 - Method for forming semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device using an optical annealing method capable of obtaining a high-quality semiconductor layer.

[0002]

2. Description of the Related Art As one method in the field of crystal formation technology for growing a crystalline thin film on an amorphous substrate, an amorphous thin film previously formed on a substrate is subjected to a heat treatment at a temperature lower than a melting point. A solid-phase growth method for crystallization has been proposed.

For example, a Si thin film formed on an amorphous insulator substrate and made amorphous by ion implantation is subjected to a heat treatment at 600 ° C. for several tens of hours in an N ₂ atmosphere to obtain a large particle size on the order of microns. It has been reported that dendritic polycrystals are formed and the characteristics of the transistors produced there are good. (T. Noguchi, H. Hayashi &
H. Oshima 1987, Mat. Res. Soc.
Symp. Proc. , 106, Polysilico
n and Interfaces, 293, Else
via Science Publishing, N
ew York, 1988).

[0004] As other methods, a method of irradiating an ultraviolet laser or a method of irradiating an infrared lamp has been proposed in order to improve the thin film and device characteristics.
(Takashi Noguchi, et al., JP-A-61-289620),
(Ino, Tani, Richo Technical Rep
ort No. 14, p4. November 198
5).

[0005] The lamp heating method described in the two reports and the application deposits a Si thin film on a quartz substrate,
Si wafers are stacked and brought into contact with the Si thin film,
Lamp light is transmitted through the quartz substrate and the Si thin film,
The Si thin film on the quartz substrate is to be heated by heat conduction caused by contact with the generated heat absorbed by the Si wafer. According to this method, there are problems such as non-adhesion and non-uniformity from a microscopic point of view caused by simply superimposing the good absorbers, or contamination and fusion.

For example, it is a well-known fact that Si Wafer generally has a swell of several μm even though it is smooth. Therefore, it is impossible to bring the Si thin film and the Si wafer into close contact with each other by contact (overlap),
The heat quantity received by the Si thin film becomes non-uniform. As a result, a temperature distribution is formed in the Si thin film to be heated. This temperature non-uniformity is an obstacle to making the structural change inside the crystal uniform, and adversely affects device characteristics. Further, when the temperature is raised to a temperature close to the melting point, there is a problem that the Si thin film and the Si wafer, which is a light absorber, are fused, and the process cannot be shifted to the element manufacturing process.

[Purpose] An object of the present invention is to solve the above-mentioned problems of the prior art and to form a semiconductor device by performing a uniform heat treatment over a large area and using a photo-annealing method of a semiconductor layer having a uniform semiconductor characteristic. Is to provide a way.

It is another object of the present invention to provide a method for forming a semiconductor layer having uniform semiconductor characteristics over a large area and forming a semiconductor device using the semiconductor layer.

[0009]

According to the present invention, an undersubstrate is provided.
A step of preparing a substrate having a semiconductor layer provided on the base substrate, an insulating layer provided on the semiconductor layer, and a light absorber layer provided on the insulating layer; Irradiating the light absorbing layer with the incoherent light to generate thermal energy, annealing the semiconductor layer using the thermal energy, after the annealing step, A method for forming a semiconductor device including a step of forming a gate electrode by removing a part thereof and a step of forming source and drain regions, wherein at least a part of the insulating layer is used as a gate insulating film.

[0010]

The details of the operation and configuration of the present invention will be described below together with the knowledge obtained in making the present invention.

FIG. 1 shows the relationship between the blackbody emission spectrum of a commonly used tungsten halogen lamp light (2200K) and the wavelength of light to be irradiated with the absorption coefficient of Si and the absorption coefficient of free carriers in Si. .

As shown in FIG. 1, the absorption coefficient at the basic absorption edge of Si rapidly increases at a wavelength of 1.2 μm or less.
On the other hand, 2200K of tungsten halogen lamp
The blackbody emission spectrum in the above ranges over a wide range of infrared light with a cutoff wavelength of 3.5 μm or less and 0.4 μm or more of quartz glass. Further, when looking at the wavelength dependence of the free carrier-absorbing component, it can be seen that at a wavelength of 1 μm or more, it extends to the longer wavelength side, and the higher the concentration of carriers, the higher the light absorption rate.

From the above, the following three facts are clear. Quartz substrates can hardly be heated by infrared irradiation. Although the light in the wavelength range of about 1 μm or less is absorbed by the Si layer, it is only a very small part of the lamp light. Si
Increasing the carrier in the layer increases the light absorption,
The lamp light can be used effectively.

In addition to the above three facts, the light absorption in the Si layer depends on the thick film. When the Si layer is used as a semiconductor layer for a transistor, the thickness of the Si layer is particularly preferably 0.1 μm or less in consideration of electrical characteristics such as leak current. However, the lamp light is almost transmitted through the Si layer having a thickness of about 0.1 μm on the quartz substrate, and the absorption of the light is extremely small.

Therefore, for example, in the case of a 7500 μm-thick Si wafer, even if an incoherent lamp light having an irradiation intensity capable of raising the temperature to 1200 ° C. is irradiated, a layer thickness of 0.1 mm disposed on a quartz substrate which is a light transmitting material. The Si layer of only 1 μm is heated only to about several hundred degrees Celsius.

Meanwhile, as another finding, it is already known that a metal has a higher light absorptivity than a Si layer.

According to the present invention, an absorption layer is deposited on the Si layer via an insulator in order to raise the temperature sufficiently to anneal the thin Si layer on the light transmitting substrate. FIG. 2 shows a layer configuration as a basic mode.

As shown in FIG. 2, a semiconductor layer 22 of Si or the like, an insulating layer 23, a light absorbing layer 24, and a protective layer 25 are sequentially provided on a light transmitting substrate 21 of quartz or the like.

In order to form a substrate having a layer structure shown in FIG. 2, first, Si, S is formed on a light-transmitting substrate by an ordinary method of forming a deposited film.
A semiconductor layer 22 of iGe, GaAs, InP or the like is formed.

Here, in order to form a thin film electronic device using the semiconductor layer annealed according to the present invention, the thickness of the semiconductor layer 2 is preferably 0.05 μm or more.
3 μm or less, more preferably 0.06 μm or more and 0.2 μm
m or less is desirable.

Subsequently, an insulating layer 23 is formed as a separation layer by a usual deposition film forming method. As the insulating layer 23, for example, silicon oxide, silicon nitride, SiO ₂ N _y , tantalum oxide, or the like is used.

The thickness of the insulating layer 23 is preferably 0.05 μm or more and 1 μm or less, more preferably 0.05 μm or less.
μm or more and 0.5 μm or less, and most preferably 0.05 μm or more and 0.1 μm or less.
4 and an insulating layer 23 during device formation.
For use as part of a device component.

Subsequently, a light absorbing layer 24 is formed on the insulating layer 23. Examples of the material of the light absorbing layer 24 include polycrystalline Si, amorphous Si, and polycrystalline SiGe.

Further, a doped semiconductor material, such as phosphorus-doped non-quality Si, boron-doped amorphous Si, arsenic-doped amorphous Si, or the like, which is intended to increase absorption by having free carriers, is used for forming the light absorbing layer 24. It may be used as a material.

For example, a polycrystalline Si layer having a layer thickness of 0.5 μm to which P is added at 10 ²⁰ / cm ³ is heated to about 100 ° C. by heating under light irradiation under the same light irradiation conditions as compared with a layer without P added. . The metal used as the material of the light absorbing layer 24 is, for example, W (tungsten), Mo (molybdenum), WSi
(Tungsten silicide), MoSi (molybdenum silicide) or the like is preferably used.

When the light intensity is high, the surface roughness may be prevented by covering the surface of the light absorbing layer 24 with a protective layer 25 for preventing evaporation and evaporation. The protective layer 25 is made of, for example, SiO ₂ or Si ₃ N ₄ or SiO ₂ / Si
₃ is light-transmissive, such as two-layer structure of N ₄ can be formed using a material to withstand high temperatures. When the lamp light is applied to the multilayer structure from above, the light passes through the protective layer 25 and the absorbing layer 24.
And the absorption layer 24 is heated. As a result, through the separation layer 24, the semiconductor layer 22 having a thickness that is not heated by transmitting light is sufficiently heated by heat conduction. When light is irradiated from below, the light from the lamp passes through, for example, a quartz substrate 21 and further passes through a semiconductor layer (active layer) 22 and a separation layer 23 to be absorbed by an absorption layer 24 so that the light is absorbed by the absorption layer 24. 24 is heated. When the light is irradiated from above and below, the effect of increasing the temperature of the light absorbing layer is further improved. As shown in FIG. 3, the absorption layer 24 may be between the semiconductor layer (active layer) 22 and the substrate 21,
Further, the substrate temperature can be increased by arranging it on the back surface of the substrate 21 to further enhance controllability and reduce distortion.

The thickness of the light absorbing layer is preferably 0.5 μm in order to sufficiently absorb incident light and raise the temperature of the semiconductor layer.
Not less than 2 μm and more preferably not less than 0.5 μm and 1.5
μm or less, and most preferably 0.5 μm or more and 1.0 μm or less.

When amorphous Si or polycrystalline Si having a fine grain size is used as the starting material of the semiconductor layer 22, grain growth occurs, crystal grains grow on the order of microns, and the influence of grain boundaries is reduced. Therefore, device characteristics are improved. As described above, the dendritic polycrystal having a large particle size on the order of microns is formed on the semiconductor layer 22.
When the starting material is used, the twin defects existing at high density in the semiconductor layer 22 are significantly reduced.

In particular, when annealing by light irradiation at a high temperature of 1000 ° C. or more and 1420 ° C. or less is preferable as the temperature of the heat treatment applied to the crystal group,
Metastases disappear efficiently.

A semiconductor layer or a metal light absorbing layer is formed by depositing an upper or lower part of the Si thin film on the light transmissive substrate, or both upper and lower parts with an insulating material layer interposed therebetween to secure adhesion. By irradiating light, the temperature rise of the Si thin film is assisted, and the controllability and uniformity thereof can be improved.

Further, by using the light absorption layer as a part of the structure of the semiconductor device, the process can be simplified.

In addition, during the irradiation for using the incoherent light, it is possible to prevent a non-uniform heat treatment temperature due to light interference, so that the entire film can be heat-treated uniformly.

The intensity of light irradiation is preferably 0.1 W
/ Cm ² or more and 300 W / cm ² or less, more preferably 10 W
/ Cm ² or more and 150 W / cm ² or less is desirable for batch heat treatment of a large area in a short time.

The heat treatment temperature of the semiconductor layer heated by light irradiation is preferably 1200 ° C. to 1400 ° C., more preferably 1250 ° C. to 1400 ° C., and most preferably 1 ° C. to 1400 ° C.
The temperature is preferably from 300 ° C. to 1380 ° C. in order to obtain a high-quality semiconductor layer.

Next, a case where the Si layer having the above-mentioned multilayer structure is used for a field effect transistor will be described.
The semiconductor layer 22 is used as a channel portion 31 by being processed by a normal semiconductor process, the separation layer 23 is used as a gate insulating layer 38, and the light absorbing layer 2 is used.
4 is diverted to the gate electrode layer 37. In order to form the high-concentration impurity added regions of the source 32 and the drain 33 shown in FIG. 4, the source 32 and the drain 3 of the separation layer 23 shown in FIG.
An opening is provided in a portion corresponding to No. 3 and polycrystalline Si doped with impurities is used for the light absorbing layer 24, and is formed by heat diffusion at the time of lamp heating or by ion implantation into the opening by a normal semiconductor process. Is also good.

For electrical contact with the source 32, the drain 33, and the gate electrode layer 37, a gate electrode 34 and a source electrode 3 made of a conductive material such as aluminum are used.
5. A drain electrode 36 is provided. The characteristics of the thin film electric field transistor manufactured as described above are improved according to the lamp heating temperature.

[0038]

The following examples are provided to further clarify the present invention, but the present invention is not limited to only the following examples.

Example 1 A quartz glass plate 21 having a size of 10 cm × 10 cm and a thickness of 500 μm was subjected to reduced pressure CVD at a pressure of 0.3 Torr.
At a substrate temperature of 620 ° C., SiH ₄ was thermally decomposed to deposit a polycrystalline Si layer (active layer) 22 having a fine crystal grain diameter of about 500 ° on average with a thickness of 0.1 μm.

On the polycrystalline Si layer 22, a substrate temperature 400
A SiH ₄ gas and an O ₂ gas were introduced under the conditions of a temperature of 760 Torr and a temperature of 760 Torr, and a SiO ₂ layer 23 was formed by a thermal CVD method with a thickness of 500 °.

Subsequently, low pressure CVD is performed on the SiO ₂ layer 23.
The SiH ₄ gas is thermally decomposed under conditions of a pressure of 0.3 Torr and a substrate temperature of 620 ° C. to form a polycrystalline Si layer having a thickness of 5000 ° C. and phosphorus ions of 10 ²⁰ ions / cm ^3.
The light absorption layer 24 containing phosphorus ions at a high concentration was formed.

Further, an SiO ₂ layer 25 having a thickness of 1 μm was formed thereon as a protective layer at a substrate temperature of 400 ° C. and a pressure of 760 Torr.
Under the condition of r, a SiH ₄ gas and an O ₂ gas were introduced and formed by a thermal CVD method.

The substrate having the multilayer structure shown in FIG. 2 was irradiated with tungsten halogen lamp light from above and below the substrate at an intensity of 78 W / cm ² for 3 minutes. The irradiation atmosphere was N ₂ , and Si wafer provided separately from the substrate for temperature measurement.
When the temperature was measured with an optical pyrometer using fer as a temperature monitor, the temperature at an irradiation time of 3 minutes was 1380.
° C.

By this irradiation, an n ⁺ po having a layer thickness of 0.5 μm is formed.
The thermal energy due to the light absorbed by the lySi layer 24 is
Si is added to the 0.1 μm thick poly Si layer 22 with no addition.
The heat was conducted to the Si layer 22 by conduction through the O ₂ layer 23. By this heat treatment, the crystal grain size of the Si layer 22 was increased to hundreds or more times to a grain size of several μm. Further, the surface of the Si layer was not roughened by the cap effect of the protective layer 25.

Subsequently, a field-effect transistor was formed using a substrate annealed by light irradiation as described above, using a conventional IC.
It was formed using a process.

Hereinafter, a process for forming the field effect transistor will be described with reference to FIGS.

First, the protective layer 25 was removed by etching using mild hydrofluoric acid. Subsequently, in order to form a gate region, the light absorption layer 24 is removed by etching to leave a portion of the gate electrode layer 37, thereby forming a gate electrode layer. An opening for forming a source and a drain is provided in the separation layer 23, and a gate insulating layer is formed. Layer 38
Was formed (FIG. 4).

A dose of 5 × 10 ¹⁵ io of P ions is implanted into the semiconductor layer 22 exposed at the opening by ion implantation.
Ions were implanted at ns / cm ² to form a source 32 and a drain 33 (FIG. 5).

After the formation of the source 32 and the drain 33, the S 32 is formed at a substrate temperature of 400 ° C. and a pressure of 760 Torr.
iH ₄ gas and O ₂ gas are introduced, and the layer thickness is 1 μm by the CVD method.
A SiO ₂ layer was formed as a protective layer 39, a gate electrode layer 37, to form a contact hole for electrical contact with the source 32 and drain 33 (Fig. 6).

In order to obtain electrical contact with the gate electrode layer 37, the source 32, and the drain 33, aluminum is deposited as an electrode material, and the gate electrode 34, the source electrode 35, and the drain electrode 36 are formed by patterning. A transistor was formed (FIG. 7).

When the characteristics of the transistor thus formed were evaluated, the carrier mobility was 100 cm ² / V.
The threshold voltage was about 1.5 V, the sub-threshold characteristic was 300 mV / decade, and the transistor characteristics were good. That is, the semiconductor layer 22 annealed according to the present example had sufficient electric characteristics as an active region of the semiconductor device.

Further, according to this embodiment, the annealed substrate is a light absorbing layer 24 made of polycrystalline Si containing a large amount of phosphorus atoms, a semiconductor layer 22 made of large grain Si having excellent semiconductor characteristics, and Since it has the separation layer 23 made of an insulating material for separating the light absorption layer 24 and the semiconductor layer 22,
Not only can the source 32 and the drain 33 be formed in the semiconductor layer 22, but also the gate insulating layer 3 can be formed by using the separation layer 23.
8 was formed, and the gate electrode layer 37 was formed using the light absorbing layer 24. Therefore, according to the present invention, a small number of steps can be performed without providing a step of newly forming an insulating material layer for a gate insulating layer and a highly doped layer for a gate electrode layer following an annealing treatment for obtaining a high-quality semiconductor layer. A semiconductor device could be formed.

Example 2 First, a non-deposited CVD method using SiH ₄ as a source gas under the conditions of a pressure of 0.3 Torr and a substrate temperature of 550 ° C. was performed on a quartz glass base material 121 having a size of 10 cm × 10 cm and a thickness of 500 μm. The crystalline Si layer 122 has a thickness of 0.1 μm.
m was formed.

Subsequently, a pressure of 7 is applied on the amorphous Si layer 122.
After forming a separation layer 123 made of SiO ₂ by a CVD method using SiH ₄ and O ₂ as source gases under the conditions of 60 Torr and a substrate temperature of 400 ° C., the substrate is transferred to a sputtering film forming apparatus, and At a pressure of 10 mTorr,
A tungsten layer was formed at a substrate temperature of room temperature in an argon atmosphere by a sputtering method at a thickness of 5000 ° to form a light absorbing layer 124.

On the light absorbing layer 124 made of tungsten, a first protective layer 125 made of SiO _{2 is} formed to a thickness of 1 μm under the same conditions as the above-mentioned separation layer, and the first protective layer 125
5 under reduced pressure CVD using source gases SiH ₂ Cl ₂ and NH ₃ at a pressure of 0.5 Torr and a substrate temperature of 800 ° C.
The second protective layer 126 made of Si ₃ N _{4 is formed} to a thickness of 500
基 体 Base 101 formed and having protective layer 127 having a two-layer structure
Was formed (FIG. 8).

The substrate 101 was irradiated with tungsten halogen lamp light at an intensity of 60 W / cm ^{2 from} above (in the direction of arrow hν in FIG. 8) the substrate 101 for one minute.

The monitor temperature of the silicon wafer provided separately from the substrate 101 for the temperature measurement was 1350 ° C. by light irradiation for one minute.

Subsequently, a field effect transistor was formed by a normal IC process using the substrate 101 annealed by the above-mentioned light irradiation.

First, the protective layer 127 is removed using phosphoric acid and hydrofluoric acid, and the light absorbing layer 124 in other parts except the gate electrode 137 is removed using reactive ion etching to remove the source and the drain. The place to be formed is the separation layer 123
An opening is formed by using the gate 1
A substrate having a gate insulating layer 37 and a gate insulating layer 138 was formed.

Subsequently, P ions were implanted into the opening at a dose of 4 × 10 ¹⁵ ions / cm ² to form a source 13.
2 and a drain 133 were formed (FIG. 1).
0).

Subsequently, a pressure of 760 Torr,
SiH ₄ and O _{2 were used} as source gases at a substrate temperature of 400 ° C.
Protective layer 139 having a layer thickness of 1 μm by a CVD method using
Are formed, and the source 132, the drain 133, and the gate 1 are formed.
Contact holes for exposing the respective 37 were formed (FIG. 11).

Subsequently, 100 electrical contacts are made to make electrical contact with the source 132, the drain 133, and the gate 137.
An electrode layer of aluminum was formed to a thickness of 1 μm by sputtering at rr and room temperature, and was patterned to form a field effect transistor shown in FIG. When the carrier mobility and sub-threshold characteristics of the field-effect transistor obtained in this way were measured, extremely good transistor characteristics were shown.

In order to examine the effect of the annealing of this embodiment, a field effect transistor was prepared in the same manner except that the optical annealing of this embodiment was not performed, and its carrier mobility and sub-threshold characteristics were measured. Comparative example).

Table 1 summarizes the characteristics of each of the transistor of this embodiment and the transistor of the comparative example.

[0065]

[Table 1]

As is clear from Table 1, the transistor subjected to the optical annealing of this example had a high carrier mobility and a low sub-threshold characteristic, and had very good transistor characteristics.

When the silicon layer 122 was observed with a transmission electron microscope, the silicon layer 122 was a polycrystalline silicon layer having an average particle diameter of 10 μm.

According to the present embodiment, the protective layer 127 is made of S
Due to the double structure of the first protective layer 125 made of iO ₂ and the second protective layer 126 made of Si ₃ N ₄ , the surface of the Si layer could be formed extremely flat after the treatment. The flatness was maintained as the Si layer was deposited.

Example 3 A layer was formed on a base material 221 made of quartz having a size of 15 cm × 15 cm and a thickness of 500 μm by a reduced pressure CVD method using SiH ₄ as a raw material scum under the conditions of a pressure of 0.3 Torr and a substrate temperature of 620 ° C. 0.1 μm thick polycrystalline Si layer 222
Is formed and Si ⁺ ions are applied to the polycrystalline Si layer at an accelerating voltage of 5.
The polycrystalline Si layer 222 was made amorphous by ion implantation under the conditions of 0 KeV and a dose of 2 × 10 ¹⁵ ions / cm ² to form a substrate having the amorphous Si layer 222 (FIG. 13).

The substrate is heat-treated at 600 ° C. for 50 hours in an N ₂ atmosphere, and the dendritic crystal layer 222 having a maximum grain size of 5 μm is formed in the amorphous Si layer 222 by solid phase growth.
Was formed.

[0071] The substrate having a該樹branch crystal layer 222 is oxidized thickness 500Å heat from the surface side in an oxidizing atmosphere SiO ₂
A layer 223 was formed to be an insulating layer. The dendritic crystal layer 222 remaining without being oxidized is a polycrystalline Si layer 22 having a thickness of about 500 °.
It became 4.

A 0.5 μm-thick polycrystalline Si layer 2 was formed on the insulating layer 223 by a reduced pressure CVD method using SiH ₄ as a source gas under the condition of a pressure of 0.3 Torr and a substrate temperature of 620 ° C.
25 on the polycrystalline Si layer 225 at a pressure of 20 mT.
The layer thickness is set to 0.
A 1 μm Ti layer 226 was formed to form a light absorbing layer.

As a protective layer, a pressure of 7
A layer thickness of 1.0 μm by a CVD method using SiH ₄ and O ₂ as source gases at a substrate temperature of 60 Torr and a temperature of 400 ° C.
The formation of the SiO ₂ layer 227. A polycrystalline Si layer 228 having a thickness of 0.6 μm was formed on the back surface of the base material 221 to form a light absorbing layer on the back surface of the base.

Thus, the base shown in FIG. 14 was prepared.

The substrate was irradiated with tungsten lamp light having an intensity of 70 W / cm ² from both sides of the substrate for 3 minutes. The temperature monitor of the Si wafer when irradiated with light for 3 minutes under these irradiation conditions showed 1380 ° C.

The polycrystalline Si layer 225, which is a light absorbing layer, and the Ti layer 226 reacted with _{each other} to form TiSi ₂ by the light irradiation.

Large-grain dendritic polycrystalline layer 2 having a maximum grain size of 5 μm
In No. 24, the dislocation groups existed in the grains before the light annealing treatment, but the dislocation groups almost disappeared after the light annealing treatment,
Very good crystallinity was obtained.

A field effect transistor was formed in the same manner as in Example 1 using the substrate.

The obtained field effect transistor had almost the same excellent characteristics as those manufactured on a Si single crystal wafer.

Example 4 An Si layer having a thickness of 0.1 μm was deposited on a quartz substrate (100 mmφ) by a vacuum evaporation method under the conditions of a substrate temperature of 200 ° C., a pressure of 1 × 10 ⁻⁸ Torr, and a deposition rate of 1 ° / Sec.

This Si layer is made of amorphous S
Although it was an i-layer, a heat treatment at 600 ° C. for 50 hours in N ₂ resulted in a dendritic polycrystalline layer having a large grain size equivalent to that of Example 3.

Subsequently, a Ta ₂ O ₅ layer is deposited as a separation layer on the dendritic polycrystalline layer by a thickness of 500 ° by a sputtering method, and then polycrystalline Si to which P is added at 10 ²⁰ atoms / cm ³ or more is added.
The layer was deposited to a thickness of 0.5 μm to form a light absorbing layer. Then CV
By a method D, a SiO ₂ layer was deposited to a thickness of 1.0 μm to form a substrate as a protective layer.

A tungsten halogen lamp having an intensity of 72 W / cm ² was irradiated from above and below the substrate for 3 minutes. S
The i-wafer monitor temperature was set to 1345 by light irradiation for 3 minutes.
° C. A field-effect transistor was fabricated in the same manner as in Example 1, except that the polycrystalline Si layer used as the absorption layer was diverted to the gate. As a result, the characteristics were as good as those of the field-effect transistor fabricated on the Si wafer. .

As a result of observation with a transmission electron microscope, it was found that the number of defects existing in the Si active layer near the interface was greatly reduced.

[0085] The quartz glass substrate of Example 5 100 mm, the pressure 0.3Torr by low pressure CVD, the SiH ₄ is thermally decomposed at a substrate temperature 620 ° C., a polycrystalline Si layer having fine crystal grains having an average grain size of about 500Å (Semiconductor layer) is deposited at a thickness of 0.1 μm and then S
An iO ₂ layer is formed to a thickness of 500 ° by thermal oxidation. Further a polycrystalline Si layer thickness 5000Å is deposited again by the above-mentioned polycrystalline Si layer forming conditions and the same low pressure CVD method, the high concentrations of the P 10 ²¹ atoms / cm ³ by diffusion from the phosphorus glass polycrystalline Si Add to layer (light absorbing layer).

The substrate having a multilayer structure thus formed has a thickness of 7
A tungsten halogen lamp was irradiated from above and below the substrate for 3 minutes at an intensity of 5 W / cm ² . Irradiation atmosphere is N ₂
And When the temperature was measured with an optical pyrometer using Si wafer as a temperature monitor, the temperature within an irradiation time of 3 minutes was 1380 ° C.

By this irradiation, an n ⁺ po having a layer thickness of 0.5 μm is formed.
The thermal energy due to the light absorbed by the ly Si layer is transmitted to the non-added 0.1 μm poly Si layer via the SiO ₂ layer to raise the temperature of the semiconductor layer. By this heat treatment, the grain size of the polycrystalline Si layer was increased by several hundred times or more to 3 μm.

After the irradiation, a field effect transistor was fabricated in the same manner as in Example 1 by using the n ⁺ poly Si of the light absorbing layer as a gate using a normal IC process, and showed good characteristics.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between a wavelength and an absorption coefficient of silicon.

FIG. 2 is a schematic explanatory diagram for explaining the present invention.

FIG. 3 is a schematic explanatory view for explaining the present invention.

FIG. 4 is a schematic explanatory view of a semiconductor device.

FIG. 5 is a schematic illustration of a process for forming a semiconductor device.

FIG. 6 is a schematic explanatory view of a process of forming a semiconductor device.

FIG. 7 is a schematic explanatory view of a step of forming a semiconductor device.

FIG. 8 is a schematic explanatory view of a semiconductor device forming process.

FIG. 9 is a schematic explanatory view of a step of forming a semiconductor device.

FIG. 10 is a schematic explanatory view of a step of forming a semiconductor device.

FIG. 11 is a schematic explanatory view of a step of forming a semiconductor device.

FIG. 12 is a schematic explanatory view of a step of forming a semiconductor device.

FIG. 13 is a schematic explanatory diagram for explaining the present invention.

FIG. 14 is a schematic explanatory view for explaining the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/20 H01L 29/786

Claims (7)

(57) [Claims] A base having a base substrate, a semiconductor layer provided on the base substrate, an insulating layer provided on the semiconductor layer, and a light absorber layer provided on the insulating layer is provided. Irradiating the substrate with incoherent light, causing the light absorber layer to absorb the incoherent light, generating thermal energy, and annealing the semiconductor layer using the thermal energy. After the step, a step of forming a gate electrode by removing a part of the light absorber layer, and a step of forming source and drain regions, wherein at least a part of the insulating layer is a gate insulating film Formation method. 2. The method for forming a semiconductor device according to claim 1, wherein the semiconductor layer and the base substrate are made of a material that transmits the incoherent light. 3. The method according to claim 1, wherein a protective layer is formed on the light absorbing layer. 4. The method according to claim 1, wherein the semiconductor layer comprises a silicon-containing semiconductor material. 5. The method according to claim 1, wherein the light-absorbent layer comprises a semiconductor or a metal material. 6. The method according to claim 1, further comprising removing a part of the insulating layer by etching. 7. The method according to claim 1, wherein ion implantation is performed in the semiconductor layer.