JPH04212410A - Light annealing method for semiconductor layer and forming method for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a forming method of a semiconductor device by using a light annealing method for obtaining a semiconductor layer having uniform semiconductor characteristics and said semiconductor layer. CONSTITUTION:A substratum wherein an excellent absorbing body 24 for an incoherent light is arranged on a semiconductor layer 22 via an insulating layer 23 is irradiated with the incoherent light, and light annealing is performed. In the title forming method of a semiconductor device, the above-mentioned substratum is used, and the above-mentioned insulating layer also is utilized as a part of a semiconductor device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoannealing method for obtaining a high quality semiconductor layer and a method for forming a semiconductor device using the semiconductor layer.

0002

[Prior Art] One method in the field of crystal formation technology for growing a crystalline thin film on an amorphous substrate is to heat-treat the amorphous thin film previously formed on the substrate at a temperature below its melting point. , a solid-phase growth method for crystallization has been proposed.

For example, a Si thin film formed on an amorphous insulating substrate and made amorphous by ion implantation is heat-treated at 600° C. for several tens of hours in an N2 atmosphere to form large grains on the order of microns. It has been reported that the transistors formed thereon have good characteristics. (T. Noguchi, H. Hayashi &
H. Oshima1987, Mat. Res. Soc.
．． Symp. Proc. ,106,Polysilic
on and Interfaces, 293, E
lsevier Science Publish
ing, New York, 1988).

As other methods, methods of irradiating with an ultraviolet laser and methods of irradiating with infrared lamp light have been proposed in order to improve the characteristics of the thin film and the device. (Takashi Noguchi et al., JP-A-61-289620), (
Ino, Tani, Richo Technical Re
port no. 14, p4. November19
85).

The lamp heating method described in these two reports and applications involves depositing a Si thin film on a quartz substrate;
Layering Si wafers and bringing them into contact with the Si thin film,
The lamp light passes through the quartz substrate and the Si thin film,
The idea is to heat the Si thin film on the quartz substrate by thermal conduction through contact with the generated heat absorbed by the Si wafer. According to this method, there are problems such as non-adhesion and non-uniformity from a microscopic point of view, contamination, and fusion caused by simply superimposing good absorbers.

For example, it is a well-known fact that although Si Wafer is smooth, it generally has undulations of several μm. For this reason, it is impossible to bring the Si thin film and the Si wafer into complete contact with each other (overlapping them), resulting in non-uniformity in the amount of heat received by the Si thin film. As a result, a temperature distribution is created within the Si thin film that is heated. This temperature non-uniformity becomes a hindrance to making uniform structural changes inside the crystal, which in turn adversely affects device characteristics. Furthermore, when the temperature is raised to near the melting point, the Si thin film and the Si wafer, which is a light absorber, are fused together, making it impossible to proceed to the device manufacturing process.

[Objective] An object of the present invention is to provide a method for optically annealing a semiconductor layer, which can perform uniform heat treatment over a large area and have uniform semiconductor characteristics, by solving the problems of the prior art described above.

Another object of the present invention is to provide a method for forming a semiconductor layer having uniform semiconductor characteristics over a large area and for forming a semiconductor device using the semiconductor layer.

[0009]

Means for Solving the Problems The method of photo-annealing a semiconductor layer of the present invention is a method of photo-annealing a semiconductor layer disposed on a base substrate, in which a good absorber of incoherent light is provided to the semiconductor layer via an insulating layer. It is characterized by performing an incoherent light irradiation treatment on a substrate on which a layer is arranged.

The method for forming a semiconductor device of the present invention is a method for forming a semiconductor device having an active region in a semiconductor layer disposed on an underlying substrate. The method is characterized in that the layer is subjected to incoherent light irradiation treatment, and patterned so that at least a portion of the semiconductor layer becomes an active region and at least a portion of the good absorber layer becomes an electrode.

[0011] The details of the operation and structure of the present invention will be explained below along with the knowledge obtained in making the present invention.

FIG. 1 shows the relationship between the blackbody radiation spectrum of commonly used tungsten halogen lamp light (2200K), the absorption coefficient of Si, and the absorption coefficient of free carriers in Si with the wavelength of the irradiated light. .

As shown in FIG. 1, the absorption coefficient of the basic absorption edge of Si increases rapidly at a wavelength of 1.2 μm or less. In contrast, the 2200K of a tungsten halogen lamp
The blackbody radiation spectrum in quartz glass covers a wide range of infrared rays from below the cutoff wavelength of 3.5 μm to 0.4 μm or more. Furthermore, looking at the wavelength dependence of the free carrier-absorption component, it can be seen that it extends toward longer wavelengths at wavelengths of 1 μm or more, and the higher the concentration of carriers, the higher the light absorption rate.

From the above, the following three facts are clear. ■Quartz substrates can hardly be heated by infrared irradiation. (2) The Si layer absorbs light in a wavelength range of approximately 1 μm or less, but this is only a small portion of the lamp light. ■Si
Increasing the carrier content in the layer increases the light absorption rate,
Lamp light can be used effectively.

In addition to the above three facts, light absorption into the Si layer is dependent on the thickness of the Si layer. Considering electrical characteristics such as leakage current, when using a Si layer as a semiconductor layer for a transistor, the thickness of the Si layer is 0.
．． A thickness of 1 μm or less is particularly desirable. However, most of the lamp light passes through the Si layer with a thickness of about 0.1 μm on the quartz substrate, and the amount of light absorbed is extremely small.

For this reason, for example, if a Si wafer is 7500 μm thick, even if it is irradiated with incoherent lamp light with an irradiation intensity that can raise the temperature to 1200° C., the layer thickness of a 0.5 μm layer placed on a quartz substrate, which is a light-transmitting material, will be irradiated with incoherent lamp light with an irradiation intensity that can raise the temperature to 1200° C. The Si layer, which is only 1 μm thick, can only be heated to about several hundred degrees Celsius.

[0017] As another finding, it is already known that metal has a higher light absorption rate than a Si layer.

In the present invention, an absorption layer is deposited on the thin Si layer with an insulator interposed therebetween in order to raise the temperature sufficiently to anneal the thin Si layer on the light-transmitting substrate. The basic layer structure is shown in FIG.

As shown in FIG. 2, a semiconductor layer 22 made of Si or the like, an insulating layer 23, a light absorption layer 24, and a protective layer 25 are provided in this order on a light-transmissive substrate 21 made of quartz or the like.

To form a substrate having the layered structure shown in FIG. 2, Si, S
A semiconductor layer 22 of iGe, GaAs, InP, etc. is formed.

In order to form a thin film electronic device using the semiconductor layer annealed according to the present invention, the thickness of the semiconductor layer 2 is preferably 0.05 μm or more.
3 μm or less, more preferably 0.06 μm or more 0.2 μm
m or less is desirable.

Subsequently, an insulating layer 23 is formed as a separation layer by a normal deposited film forming method. As the insulating layer 23, silicon oxide, silicon nitride, SiO2Ny, tantalum oxide, etc. are used, for example.

The thickness of the insulating layer 23 is preferably from 0.05 μm to 1 μm, more preferably from 0.05 μm to 1 μm.
μm or more and 0.5 μm or less, optimally 0.05 μm or more and 0
．． The semiconductor layer 22 and the light absorption layer 24 should be 1 μm or less.
It is desirable to use insulating layer 23 as part of the device component during device formation.

Subsequently, a light absorption layer 24 is formed on the insulating layer 23. Examples of the material for the light absorption layer 24 include polycrystalline Si, amorphous Si, and polycrystalline SiGe.

In addition, a doped semiconductor material designed to increase absorption by having free carriers, such as phosphorus-doped non-quality Si, boron-doped amorphous Si, arsenic-doped amorphous Si, etc., may be used in the light absorption layer 24. It may also be used as a material.

For example, a 0.5 μm thick polycrystalline Si layer doped with P at 10 20 /cm 3 becomes about 100° C. higher when heated by light irradiation under the same light irradiation conditions than a layer without addition. Further, examples of metals that can be used as materials for the light absorption layer 24 include W (tungsten), Mo (molybdenum), and WSi.
(tungsten silicide), MoSi (molybdenum silicide), etc. are preferably used.

When the light intensity is strong, the surface roughening may be prevented by covering the light absorbing layer 24 with a protective layer 25 for preventing surface roughening and evaporation. The protective layer 25 includes, for example, SiO2, Si3N4, or SiO2/
A material that is optically transparent and resistant to high temperatures, such as a two-layer structure of Si3N4, can be used. When the multilayer structure is irradiated with lamp light from above, the light passes through the protective layer 25 and is absorbed by the absorption layer 24, thereby raising the temperature of the absorption layer 24. the result,
Through the separation layer 24, the semiconductor layer 22, which has a thickness that would normally not be heated by transmitting light, is sufficiently heated by thermal conduction. When the light is emitted from the bottom, the light from the lamp is
For example, it passes through the quartz substrate 21, and furthermore, the semiconductor layer (active layer).
The light is absorbed by the absorption layer 24 through the light absorption layer 22 and the separation layer 23, and the temperature of the light absorption layer 24 is increased. If the light is irradiated from above and below, the effect of increasing the temperature of the light absorption layer will be further improved. Absorbent layer 2 as shown in Figure 3
4 may be placed between the semiconductor layer (active layer) 22 and the substrate 21, or may be placed on the back surface of the substrate 21 to increase the substrate temperature,
It is also possible to improve controllability and reduce distortion.

The thickness of the light absorption layer is preferably 0.5 μm in order to sufficiently absorb incident light and raise the temperature of the semiconductor layer.
2μm or more, more preferably 0.5μm or more and 1.5μm or more
The thickness is preferably 0.5 μm or more and 1.0 μm or less, preferably 0.5 μm or more and 1.0 μm or less.

When amorphous Si or polycrystalline Si with a fine grain size is used as the starting material for the semiconductor layer 22, grain growth occurs and crystal grains grow to the micron order, reducing the influence of grain boundaries. Therefore, device characteristics are improved. The semiconductor layer 22 is made of large-grain dendritic polycrystals on the micron order as described above.
When used as a starting material, twin defects present in high density in the semiconductor layer 22 are significantly reduced.

In particular, it is preferable that the temperature of the heat treatment applied to the crystal group be at a high temperature of 1000° C. or more and 1420° C. or less, and that the annealing is performed by light irradiation to eliminate stacking faults and stacking defects inside the semiconductor layer 22.
Transference is efficiently eliminated.

A semiconductor layer or a metal good light absorption layer is formed on the top or bottom of the Si thin film on the light-transmitting substrate, or on both the top and bottom, through an insulating material layer, and after ensuring adhesion. By irradiating light, it is possible to assist in raising the temperature of the Si thin film and improve its controllability and uniformity.

Furthermore, by using the light-absorbing layer as part of the structure of the semiconductor element, the process can be simplified.

Furthermore, since it is possible to prevent uneven heat treatment temperature due to light interference during irradiation using incoherent light, the entire film can be uniformly heat treated.

The intensity of light irradiation is preferably 0.1W.
/cm2 or more and 300W/cm2 or less, preferably 10
It is desirable to set it to W/cm2 or more and 150 W/cm2 or less in order to heat-treat a large area at once in a short time.

The heat treatment temperature of the semiconductor layer heated by light irradiation is preferably 1200° C. or more and 1400° C. or less, more preferably 1250° C. or more and 1400° C. or less, and optimally 1250° C. or more and 1400° C. or less.
In order to obtain a high quality semiconductor layer, it is desirable to set the temperature to 300° C. or higher and 1380° C. or lower.

Next, the case where the Si layer having the multilayer structure described above is used in a field effect transistor will be explained. The semiconductor layer 22 is processed by a normal semiconductor process to be used as a channel portion 31, the separation layer 23 is used as a gate insulating layer 38, and the light absorption layer 2 is used as a gate insulating layer 38.
4 is used as the gate electrode layer 37. To form the highly doped regions of the source 32 and drain 33 shown in FIG. 4, the source 32 and drain 3 of the isolation layer 23 shown in FIG.
An opening is provided in the portion corresponding to 3, and polycrystalline Si doped with impurities is used for the light absorption layer 24, and it is formed by thermal diffusion during lamp heating, or ions are implanted into the opening by a normal semiconductor process. Also good.

For electrical contact with the source 32, drain 33, and gate electrode layer 37, a gate electrode 34 and a source electrode 3 are made of a conductive material such as aluminum.
5. Provide a drain electrode 36. The characteristics of the thin film field transistor manufactured as described above improve depending on the lamp heating temperature.

[0038]

[Examples] Hereinafter, examples will be described to further clarify the present invention, but the present invention is in no way limited to the examples described below.

Example 1 A quartz glass plate 21 with a size of 10 cm x 10 cm and a thickness of 500 μm was coated with a pressure of 0.3 Torr by low pressure CVD.
SiH4 was thermally decomposed at a substrate temperature of 620° C., and a polycrystalline Si layer (active layer) 22 having a fine crystal grain size of about 500 Å on average was deposited to a thickness of 0.1 μm.

[0040] On the polycrystalline Si layer 22, a substrate temperature of 400°C is applied.
℃ and a pressure of 760 Torr, SiH 4 gas and O 2 gas were introduced to form a SiO 2 layer 23 with a thickness of 500 Å by thermal CVD.

[0041] Subsequently, low pressure CVD is performed on the SiO2 layer 23.
By the method, SiH4 gas was thermally decomposed under the conditions of a pressure of 0.3 Torr and a substrate temperature of 620°C to form a polycrystalline Si layer with a layer thickness of 5000 Å, and phosphorus ions were decomposed at a rate of 1020 ions/cm.
Ions were implanted to a concentration of 3 to form a light absorption layer 24 containing a high concentration of phosphorus ions.

Furthermore, a SiO2 layer 25 with a thickness of 1 μm is placed on top of the protective layer at a substrate temperature of 400° C. and a pressure of 760 Torr.
It was formed by thermal CVD method by introducing SiH4 gas and O2 gas under the conditions of r.

The substrate having the multilayer structure shown in FIG. 2 was irradiated with tungsten halogen lamp light from above and below for 3 minutes at an intensity of 78 W/cm 2 . The irradiation atmosphere was N2, and a Si w was installed separately from the base for temperature measurement.
When I measured the temperature with an optical pyrometer using afer as a temperature monitor, the temperature after 3 minutes of irradiation was 138.
It was 0°C.

This irradiation results in a layer thickness of 0.5 μm.
The thermal energy due to the light absorbed by the lySi layer 24 is
Additive-free poly-Si layer 22 with a layer thickness of 0.1 μm
The heat was conducted through the iO2 layer 23 and the Si layer 22 was subjected to heat treatment. By this heat treatment, the crystal grain size of the Si layer 22 was enlarged several hundred times or more to a grain size of several μm. Further, due to the capping effect of the protective layer 25, the surface of the Si layer was not roughened.

Next, using the substrate annealed by light irradiation as described above, a field effect transistor is formed into an ordinary IC.
formed using the process.

Hereinafter, the steps for forming the field effect transistor will be explained with reference to FIGS. 4 to 7.

First, the protective layer 25 was removed by etching using buffered hydrofluoric acid. Subsequently, in order to form a gate region, the light absorption layer 24 is etched away leaving a portion of the gate electrode layer 37 to form a gate electrode layer, an opening for forming a source and a drain is provided in the isolation layer 23, and gate insulation is removed. layer 38
was formed (Figure 4).

P ions are implanted into the semiconductor layer 22 exposed through the opening at a dose of 5×10 15 i.
Ion implantation was performed at ons/cm2 to form a source 32 and a drain 33 (FIG. 5).

After forming the source 32 and drain 33, S is heated at a substrate temperature of 400° C. and a pressure of 760 Torr.
Introducing iH4 gas and O2 gas and using CVD method to create a layer thickness of 1μ
A SiO2 layer of m thickness was formed as a protective layer 39, and contact holes for electrical contact with the gate electrode layer 37, source 32, and drain 33 were formed (FIG. 6).

In order to obtain electrical contact with the gate electrode layer 37, source 32, and drain 33, aluminum is deposited as an electrode material, and the gate electrode 34, source electrode 35, and drain electrode 36 are formed by patterning, and the field effect A transistor was formed (FIG. 7).

When the characteristics of the transistor thus formed were evaluated, the carrier mobility was 100 cm2/V.
sec or more, the threshold was about 1.5V, the subthreshold characteristic was 300mV/decade, and it had good transistor characteristics. That is, the semiconductor layer 22 annealed according to this example had sufficient electrical properties as an active region of a semiconductor device.

According to this embodiment, the annealed substrate includes a light absorption layer 24 made of polycrystalline Si containing a large amount of phosphorus atoms, a semiconductor layer 22 made of large grain size Si having excellent semiconductor properties, and Since it has a separation layer 23 made of an insulating material that separates the light absorption layer 24 and the semiconductor layer 22,
Not only can a source 32 and a drain 33 be formed in the semiconductor layer 22, but also a gate insulating layer 3 can be formed using the separation layer 23.
8 could be formed, and the gate electrode layer 37 could be formed using the light absorption layer 24. Therefore, according to the present invention, following the annealing treatment to obtain a high-quality semiconductor layer, there is no need to newly form an insulating material layer for the gate insulating layer and a highly doped layer for the gate electrode layer, with fewer steps. A semiconductor device could be formed.

Example 2 First, an amorphous material was formed on a base material 121 made of quartz glass having a size of 10 cm x 10 cm and a thickness of 500 μm by a low pressure CVD method using SiH4 as a raw material gas at a pressure of 0.3 Torr and a substrate temperature of 550°C. The layer thickness of the quality Si layer 122 is 0.1μ.
m was formed.

Subsequently, a pressure of 7° is applied to the amorphous Si layer 122.
After forming a separation layer 123 made of SiO2 by the CVD method using SiH4 and O2 as source gases under conditions of 60 Torr and a substrate temperature of 400°C, the substrate was transferred to a sputter film forming apparatus, and a pressure of 10 mTorr was applied onto the separation layer 123.
A tungsten layer with a thickness of 5000 Å was formed by sputtering in an argon atmosphere at room temperature and the substrate temperature to form a light absorption layer 124.

A first protective layer 125 made of SiO2 is formed to a thickness of 1 μm on the light absorption layer 124 made of tungsten under the same conditions as the above-mentioned separation layer, and the first protective layer 125 is
Reduced pressure CV using raw material gases SiH2Cl2 and NH3 under the conditions of a pressure of 0.5 Torr and a substrate temperature of 800° C.
The second protective layer 126 made of Si3N4 was formed with a layer thickness of 5 using method D.
Substrate 1 having a protective layer 127 of 00 Å and having a two-layer structure
01 was formed (FIG. 8).

The substrate 101 was irradiated with tungsten halogen lamp light at an intensity of 60 W/cm 2 from above the substrate 101 (in the direction of the arrow hv in FIG. 8) for 1 minute.

The monitor temperature of the silicon wafer, which was provided separately from the base 101 for temperature measurement, reached 1350° C. after 1 minute of light irradiation.

Subsequently, a field effect transistor was formed by a normal IC process using the substrate 101 which had been annealed by light irradiation as described above.

First, the protective layer 127 is removed using phosphoric acid and hydrofluoric acid, and the other parts of the light absorption layer 124 are removed using reactive ion etching, leaving only the gate electrode 137, and the source and drain are removed. An opening is formed using a metal so that the part to be formed is exposed from the separation layer 123, and the gate 1
37 and a gate insulating layer 138 were formed.

Next, P ions are implanted into the opening at a dose of 4×10 15 ions/cm 2 to form the source 1.
32 and a drain 133 were formed (Figure 1
0).

[0061] Subsequently, a pressure of 760 Torr was applied to the base.
SiH4 and O were used as source gases at a substrate temperature of 400°C.
A protective layer 13 with a layer thickness of 1 μm was formed by the CVD method using
9, and contact holes were formed to expose the source 132, drain 133, and gate 137, respectively (FIG. 11).

[0062] Next, 100To
An aluminum electrode layer having a thickness of 1 μm was formed using a sputtering method at room temperature and patterned to form a field effect transistor shown in FIG. The carrier mobility and subthreshold characteristics of the field effect transistor thus obtained were measured and showed very good transistor characteristics.

In order to investigate the effect of the annealing in this example, a field effect transistor was fabricated in the same manner as in this example except that the photo-annealing was not performed, and its carrier mobility and subthreshold characteristics were measured ( comparative example).

Table 1 summarizes the characteristics of the transistor of this example and the transistor of the comparative example.

[0065]

[Table 1]

As is clear from Table 1, the photo-annealed transistor of this example had high carrier mobility and low subthreshold characteristics, and had extremely good transistor characteristics.

Further, when the silicon layer 122 was observed under a transmission electron microscope, it was found that the silicon layer 122 was a polycrystalline silicon layer with an average grain size of 10 μm.

Further, according to this embodiment, the protective layer 127 is
Because of the dual structure of the first protective layer 125 made of iO2 and the second protective layer 126 made of Si3N4, the surface of the Si layer could be formed to be extremely flat after processing. Its flatness was maintained as the Si layer was deposited.

Example 3 A layer thickness was deposited on a base material 221 made of quartz having a size of 15 cm x 15 cm and a thickness of 500 μm by a low pressure CVD method using SiH4 as raw material waste under conditions of a pressure of 0.3 Torr and a substrate temperature of 620° C. 0.1 μm polycrystalline Si layer 222
is formed, and Si+ ions are accelerated in the polycrystalline Si layer at a voltage of 5
Ion implantation was performed under the conditions of 0 KeV and a dose of 2×10 15 ions/cm 2 to make the polycrystalline Si layer 222 amorphous, thereby forming a substrate having an amorphous Si layer 222 (FIG. 13).

The substrate is heat-treated at 600° C. for 50 hours in a N2 atmosphere, and a large-grain dendrite layer 222 with a maximum grain size of 5 μm is formed in the amorphous Si layer 222 by solid phase growth.
was formed.

The substrate having the dendrite layer 222 is thermally oxidized from the surface side to a thickness of 500 Å in an oxidizing atmosphere to form SiO2.
A layer 223 was formed to serve as an insulating layer. The dendrite layer 222 that remains unoxidized is a polycrystalline Si layer 22 with a thickness of approximately 500 Å.
It became 4.

A polycrystalline Si layer 2 with a thickness of 0.5 μm is formed on the insulating layer 223 by a low pressure CVD method using SiH4 as a raw material gas under conditions of a pressure of 0.3 Torr and a substrate temperature of 620° C.
25 is formed, and a pressure of 20 mT is applied on the polycrystalline Si layer 225.
A layer with a thickness of 0.0 is formed by sputtering at a substrate temperature of room temperature.
A 1 μm thick Ti layer 226 was formed to serve as a light absorption layer.

[0073] Pressure 7 is applied as a protective layer on the light absorption layer 226.
A layer thickness of 1.0 μm was obtained by CVD using SiH4 and O2 as raw material gases at a substrate temperature of 60 Torr and 400°C.
A SiO2 layer 227 of m thickness was formed. A polycrystalline Si layer 228 having a thickness of 0.6 μm was formed on the back surface of the base material 221 to serve as a light absorption layer on the back surface of the substrate.

In this manner, the substrate shown in FIG. 14 was produced.

[0075] The substrate was irradiated with tungsten lamp light having an intensity of 70 W/cm2 for 3 minutes from both sides of the substrate. The temperature monitor of the Si wafer when irradiated with light for 3 minutes under these irradiation conditions showed a temperature of 1380°C.

By the above-described light irradiation, the polycrystalline Si layer 225 and the Ti layer 226, which are light absorption layers, reacted to form TiSi2.

Large grain dendritic polycrystalline layer 2 with a maximum grain size of 5 μm
In No. 24, dislocation groups existed within the grains before photoannealing, but after photoannealing, most of the dislocation groups disappeared.
Very good crystallinity was obtained.

A field effect transistor was formed using the substrate in the same manner as in Example 1.

The obtained field effect transistor had almost the same excellent characteristics as that produced on a Si single crystal wafer.

Example 4 A Si layer was deposited to a thickness of 0.1 μm on a quartz substrate (100 mmφ) by vacuum evaporation at a substrate temperature of 200° C., a pressure of 1×10 −8 Torr, and a deposition rate of 1 Å/Sec.

[0081] This Si layer is amorphous S as it is deposited.
The i-layer was heat-treated at 600° C. for 50 hours in N2 to become a large-grain dendritic polycrystalline layer similar to that of Example 3.

Subsequently, a Ta2O5 layer with a thickness of 500 Å was deposited on the dendritic polycrystalline layer as a separation layer by sputtering, and then a polycrystalline Si layer doped with P at 1020 atoms/cm3 or more was deposited with a thickness of 0.5 μm. It was used as a light absorption layer. Subsequently, a SiO2 layer having a thickness of 1.0 .mu.m was deposited by the CVD method to form a substrate serving as a protective layer.

[0083] Light from a tungsten halogen lamp having an intensity of 72 W/cm2 was irradiated from above and below the substrate for 3 minutes. S
The i-wafer monitor temperature was 1345 after 3 minutes of light irradiation.
It became ℃. A field effect transistor was fabricated in the same manner as in Example 1 by using the polycrystalline Si layer used as an absorption layer as a gate, and as a result, its characteristics showed good characteristics equivalent to those of a field effect transistor fabricated on a Si wafer. .

As a result of observation using a transmission electron microscope, it was found that the defect group existing in the Si active layer near the interface was significantly reduced.

Example 5 A polycrystalline Si layer (with fine crystal grains with an average grain size of about 500 Å) was formed on a 100 mmφ quartz glass substrate by thermally decomposing SiH4 at a pressure of 0.3 Torr and a substrate temperature of 620° C. using the low-pressure CVD method. After depositing a semiconductor layer) with a thickness of 0.1 μm, S
An iO2 layer with a thickness of 500 Å is formed by thermal oxidation. Furthermore, a polycrystalline Si layer with a layer thickness of 5000 Å was deposited again using the same low-pressure CVD method as the conditions for forming the polycrystalline Si layer described above, and P was diffused from the phosphorus glass into the polycrystalline Si layer at a high concentration of 1021 atoms/cm3. Add (light absorption layer).

[0086] 7.
Tungsten halogen lamp light was irradiated from above and below the substrate at an intensity of 5 W/cm 2 for 3 minutes. The irradiation atmosphere is N2
And so. When measured with an optical pyrometer using the Si wafer as a temperature monitor, the temperature was 1380° C. within 3 minutes of irradiation time.

This irradiation results in an n+po layer with a thickness of 0.5 μm.
The thermal energy due to the light absorbed by the ly Si layer is
The SiO was added to the additive-free 0.1 μm poly Si layer.
It conducts through the two layers and raises the temperature of the semiconductor layer. This heat treatment reduces the grain size of the polycrystalline Si layer to 3 μm, which is several hundred times larger.
It was expanded to.

After the irradiation, a field effect transistor was fabricated in the same manner as in Example 1 using the n+poly Si of the light absorption layer as a gate using a normal IC process, and it showed good characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the relationship between wavelength and absorption coefficient of silicon.

FIG. 2 is a schematic explanatory diagram for explaining the present invention.

FIG. 3 is a schematic explanatory diagram for explaining the present invention.

FIG. 4 is a schematic explanatory diagram of a semiconductor device.

FIG. 5 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 6 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 7 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 8 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 9 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 10 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 11 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 12 is a schematic explanatory diagram of a process for forming a semiconductor device.

FIG. 13 is a schematic explanatory diagram for explaining the present invention.

FIG. 14 is a schematic explanatory diagram for explaining the present invention.

Claims (8)

[Claims] 1. A method of photo-annealing a semiconductor layer disposed on a base substrate, comprising performing incoherent light irradiation treatment on a substrate in which a good absorber layer for incoherent light is disposed on the semiconductor layer via an insulating layer. A method for optically annealing a semiconductor layer, characterized by: 2. The method of photo-annealing a semiconductor layer according to claim 1, wherein the good absorber layer is disposed above or below the semiconductor layer or both. 3. The method of photo-annealing a semiconductor layer according to claim 1, wherein the substrate has a protective layer on the outermost surface. 4. The method of photo-annealing a semiconductor layer according to claim 1, wherein the semiconductor layer is made of a silicon-based semiconductor material. 5. The method of photo-annealing a semiconductor layer according to claim 1, wherein the good absorber layer is made of a semiconductor material or a metal material. 6. A method for forming a semiconductor device having an active region in a semiconductor layer disposed on a base substrate, the semiconductor layer having a good absorber layer for incoherent light disposed thereon via an insulating layer is subjected to incoherent light irradiation treatment. A method for forming a semiconductor device, comprising patterning the semiconductor layer to make at least a part of the semiconductor layer an active region and to make at least a part of the good absorber layer an electrode. 7. The method of forming a semiconductor device according to claim 6, wherein a portion of the insulating layer is removed by etching. 8. The method for forming a semiconductor device according to claim 6, wherein ions are implanted into the semiconductor layer.