JPH0752411B2 - Failure detection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a failure detection method for an information processing apparatus, and more particularly to a failure detection method for controlling transmission / reception between information processing apparatuses by a request reply method.

(Prior Art) Conventionally, when a failure in transmission / reception control between information processing apparatuses is detected by the request reply method, there is no detection circuit that focuses on the failure and the internal information processing apparatus on the transmission side does not have a detection circuit. This was done by detecting that the processing of an instruction within the maximum execution time of one instruction was not completed (detected when no reply was received).

FIG. 2 is a block diagram showing an example of realizing the memory access method adopting the request reply method according to the prior art. In FIG. 2, 201 is an arithmetic and control unit, 202-
204 is a request code register of a different format, 205 is a logical address register, 206 is a real address register, 207, 208 and 214 are write data registers of different formats, 209 is a real address conversion buffer, 210 is a cache, and 211 is a memory access address. Register, 212
Is a selection circuit, 213 is a reply data register, 215 is a memory access control circuit, 216 is a request flip-flop, 217 is a request flag buffer write address register, 218 is a request flag buffer read address register, and 219 is a request flag buffer. Reference numeral 220 is a first reply reception flip-flop, 221 is a second reply reception flip-flop, and 222 is a memory control unit.

In FIG. 2, the request code is set in the request code register 202, the logical address is set in the logical address register 205, and the store data is set in the write data register 207 as information for accessing the memory from the arithmetic control unit 201. A request is sent from the arithmetic control unit 201 to the memory access control circuit 215. The memory access control circuit 215 determines the type of memory access from the contents of the request code register 202, sets the result of real address conversion by the real address conversion buffer 209 to the real address register 206, and sets the request code to the request code register 203. Then, the store data is set in the write data register 208.
If data is present in the cache 210 in the read request, the data is returned to the operation control unit 201 through the selection circuit 212 capable of selecting reply data from the memory control unit 222. If it is a write request, an instruction to write the data in the write data register 208 to the cache 210 is given.

When data is not present in the cache 210 for read request, or for write request, memory controller
A request code is set in the request code register 204 to indicate data read / write to 222, a memory read / write address is set in the memory access address register 211, and write data is set in the write data register 214. In addition, the request flip-flop 216 is set and the request is sent.

When the request flip-flop 216 is set, the request flag from the request code register 204 is written in the request flag buffer 219, and the buffer write address register 217 is updated for the next writing. Similarly, if there are continuous requests to the memory control unit 222, the request flag is buffered to the request flag buffer 219 and the content of the buffer write address register 217 is updated.

After that, as the memory access ends, the memory control unit 22
2 returns the first reply or the second and subsequent replies.

Generally, after reading 8 bytes of memory, when the first 8 bytes of data in block read (8 transfers of 8 bytes) are returned, and the first reply is given to the store, the block is read. When the subsequent 8 bytes other than the first read are transferred and the data for 7 times are returned, the second and subsequent replies are returned.

1st reply 1st reply reception flip-flop
When received at 220, the first reply is sent together with the contents of the request flag buffer 219 to the memory access control circuit 215.
Then, the memory access control circuit 215 determines the type of reply and controls whether or not the request data is returned to the arithmetic control unit 201. At the same time, the next request flag buffer 21
The request flag buffer read address register 218 is updated to read the contents of 9.

When the second and subsequent replies are received by the second and subsequent reply reception flip-flops 221, the memory access control circuit 215
To the cache 210 to report that the second and subsequent replies have occurred, and to write the block load data set in the memory read data register 213 transferred in synchronization with the reply signal from the memory control unit 222 to the cache 210. There is.

As described above, in the prior art, no special failure detection circuit for request reply control has been prepared.

(Problems to be Solved by the Invention) Since the control failure of the above-mentioned conventional request reply method has no direct detection means, it indirectly causes an inter-instruction time-out (for example, because the waiting reply does not return). Execution of instructions does not end.) Or, it becomes impossible to point out the failure point by entering into an unpredictable situation due to garbled data (for example, many replies are returned or the order of replies is incorrect). It had the drawback of being difficult. A failure detection method that detects an error by comparing the request start number with the reply start number when a response is received from the processor with the start number added to the request is sent to the memory. However, this system has a drawback in that the processor does not have a buffer for the activation number and only one activation is allowed from a certain processor's point of view.

An object of the present invention is to receive a first reply, or a plurality of second and subsequent replies in response to one request, and continuously send a request flag buffer before receiving the first reply after sending a request. A failure detection method configured to enable the sending of requests and detect whether or not the number of replies received after the second exceeds a specified value to eliminate the above-mentioned drawbacks and point out the failure location. To provide.

(Means for Solving Problems) A failure occurrence method according to the present invention is a failure detection method in a system for controlling transmission / reception between information processing devices by a request reply method, and is a first method in response to one request. First receiving means for receiving a reply, second receiving means for receiving a plurality of replies of second and subsequent replies in response to the request, and a first reply of the request after sending the request. A request flag buffer having a capacity capable of continuously sending requests until it is received by the first receiving means, and a write address of the request flag buffer is held and updated when the request is sent. Request flag buffer write address register and read address of the request flag buffer A request flag buffer read address register which is held and updated when a reply is received by the first receiving unit, a reply valid waiting flag set by the request flag buffer, and a reply valid reply flag by the first receiving unit. A reply counter which is cleared upon reception and which counts the number of receptions when the second and subsequent replies are received by the second receiving means, and for detecting that the number of receptions count value of this reply counter exceeds a prescribed value. Specified value excess detection means, and reply valid wait for resetting the reply valid wait flag when the second and subsequent replies are received by the second receiving means when the specified value excess detection means detects the specified value excess Flag resetting means and the second means when the reply valid waiting flag is in a reset state. And a failure occurrence detecting means for detecting that a failure has occurred in the system for controlling transmission / reception when the second and subsequent replies are received by the receiving means.

Further, in the fault detection method, it is detected that a fault has occurred in the system for controlling the transmission / reception when the upper bit of the reply counter becomes "1".

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a block diagram showing an embodiment for realizing the failure detection method according to the present invention, and shows only a request reply control unit different from the block diagram according to the conventional technique shown in FIG.

In FIG. 1, 101 is a request code register, 102
Is a memory access address register, 103 is a reply data register, 104 is a write data register, 105 is a request flip-flop, 106 is a memory access control circuit, 107 is a request flag buffer read address register, and 108 is a request flag buffer write. Address register, 109 is request flag buffer, 110 to 11
2, 122 and 116 are first to fifth comparison circuits, 113, 117 and 1 respectively.
Reference numeral 18 is a first to third AND gate 114, a second and subsequent reply valid indication flags, 115 is a second and subsequent reply counters, 119 and 120 are first and second and subsequent reply reception flip-flops, and 121 is a request reply counter. , 123 is a reply flag register, 124 is a failure processing control unit, 126 and 127 are NAND gates respectively, and 125 is a memory control unit.

In this embodiment, the type of request is read request 1,
It is limited to three types, read request 2 and write request. Read request 1 gives only the first reply to one request, read request 2
Gives a first reply followed by second to eighth replies for one request, and a write request gives a first reply for one request. In addition, the number of requests that can be continuously sent before the reply is received is
It is explained below as 15 pieces.

First, the operation when sending a request will be described.

When the request flip-flop 105 is set and is in the request sending state, the request code register 101
Of the contents of read request 1 / read request 2 /
Information for classifying the write request is stored in the request flag buffer 109 composed of 16 words. That is, in this case, the above information is stored in the word position indicated by the request flag buffer write address register 108 (initial value is all bits “0”) composed of 5 bits of the request flag buffer 109, and at the same time, The contents of the request flag buffer write address register 108 are counted up to indicate the next word position. The initial value is all "0" and the request reply counter 121, which is composed of 5 bits, is counted up and the number of requests waiting for reply is displayed. Here, the count-up is suppressed when the reply is received.

Next, the operation when receiving a reply will be described.

For read request 1, the first reply is reported by setting the first reply receive flip-flop 119. A request flag read from the word position of the request flag buffer 109 indicated by the request flag buffer read address register 107, which is composed of 5 bits and whose initial value is set to all bits "0", and the first flag The reply flag of the reply flag register 123, which is reported at the same time as the reply, is compared by the third comparison circuit 112. When the two do not match, it is determined that the reply is different from the predicted reply, and is reported to the failure processing unit 124 as a request reply control failure. further,
Count down the request reply counter 121,
Request flag buffer read address register 10 to prepare for the next operation of request flag buffer 109.
Count up 7.

For the read request 2, the reply is reported by the first reply setting the first reply reception flip-flop 119. In addition to the operation similar to the read request 1, the reply of the second and subsequent replies following the reply is sent. The reply counter 115 consisting of 4 bits for counting the number is cleared to the initial value (all bits "0") and the second and subsequent replies are waited. Then, when the second and subsequent replies are reported by setting the second reply reception flip-flop 120, the reply counter 115 is counted up, and the reply valid waiting flag V114 for the read request 2 (before the first reply reception is received). When the second AND gate 117 detects that the second and subsequent replies have been received, it is determined that the reply is different from the predicted reply. Then, it reports to the failure processing control unit 124 as a request reply control failure.

Further, the reply counter 115 is counted up by the second and subsequent replies, and the contents R2C = 6 of the reply counter 115 sent by the NAND gates 126 and 127 are compared with the fifth comparison in order to detect the last wait for the second and subsequent replies. When the circuit 116 detects the second and subsequent replies at that time, the V flag F / F 114 is reset by the output of the third AND gate 118 to invalidate the reply wait for the read request 2. If you receive the second and subsequent replies,
When R2C> 7 and the upper 1 bit of the reply counter 115 becomes "1", it is judged that an extra reply has been received, and it is reported to the failure processing control section 124 as a request reply control failure.

The operation for the store request is the same as that for the read request 1.

Further, the difference between the buffer write address register 108 for controlling the writing / reading of the request flag buffer 109 and the request flag buffer reading address register 107 is always 15 at maximum, and the request reply control becomes unexpected due to the request preceding. In order not to go down, a mismatch output at the first comparison circuit 110 of the upper bit between the buffer write address register 108 and the request flag buffer read address register 107, and a lower 4
The AND circuit 113 of the bit and the coincidence output in the second comparison circuit 111 is detected by the first AND gate 113, and the failure processing control unit 12
Report to request 4 as request reply control failure.

Also, in order not to fall into an unexpected situation of request reply control due to the reply preceding when the request is not sent,
The request reply counter 121 detects that all the bits are "1" (counter value is "-1") by the fourth comparison circuit 122, and further requests the request reply so that the request reply control does not fall into an unexpected situation. The failure processing control unit 12 detects that the upper 1 bit of the reply counter 121 is "1" (counter: overflow).
Report request reply control failure to 4.

(Effects of the Invention) As described above, according to the present invention, the first reply or the plurality of second and subsequent replies is received in response to one request, and before the first reply is received after the request is transmitted. Request flag buffer enables continuous sending of requests and detects whether or not the number of replies received from the second and subsequent replies exceeds a specified value, adding a small amount of hardware and making a control failure in the request reply method. Can be detected promptly, and moreover, the location of the failure can be correctly limited.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment for realizing the failure detection system according to the present invention. FIG. 2 is a block diagram showing an example of realizing the fault detection method according to the prior art. 101,202 to 204 …… Request code register 102,211 …… Memory access address register 103,213 …… Reply data register 104,207,208,214 …… Write data register 105,216 …… Request flip-flop 106,215 …… Memory access control circuit 107,218 …… Request flag buffer read Address register 108,217 …… Request flag buffer write Address register 109,219 …… Request flag buffer 110 to 112,122,116 …… Comparison circuit 113,117,118 …… AND gate 114 …… Second and subsequent replies valid display flag 115 …… Second and subsequent replies Counter 119 …… First reply reception flip-flop 120,221 …… Second and subsequent reply reception flip-flops 121 …… Request reply counter 123 …… Reply flag register 124 …… Fault processing control unit 125,222 …… Memory control unit 126,127… … NAND gate 201 …… Operation control unit 205 …… Logical address register 206 …… Real address register 210 …… Cashing 212 …… Selection circuit

Claims (2)

[Claims] 1. A failure detection method for a system for controlling transmission / reception between information processing apparatuses by a request reply method, comprising: first receiving means for receiving a first reply in response to one request; and the request. Corresponding to the second receiving means for receiving a plurality of replies of the second and subsequent ones, and continuously until the first reply of the request is received by the first receiving means after the request is transmitted. And a request flag buffer having a capacity capable of sending a request, a request flag buffer write address register that holds a write address of the request flag buffer and is updated when the request is sent, and a request flag buffer The read address is retained and updated when the reply is received by the first receiving means. A request flag buffer read address register, a reply valid waiting flag set by the request flag buffer, cleared when a reply is received by the first receiving means, and a second or subsequent one by the second receiving means Reply counter that counts the number of receptions when receiving a reply, and a specified value excess detection means for detecting that the received count value of this reply counter exceeds the specified value, and the specified value exceeded detection means Reply valid wait flag resetting means for resetting the reply valid waiting flag when the second and subsequent replies are received by the second receiving means when the excess is detected, and when the reply valid waiting flag is in a reset state When the second and subsequent replies are received by the second receiving means, Fault detection method characterized by having a failure detection means for detecting that a failure occurs in the system for controlling the signal. 2. The upper bit of the reply counter is "1"
The failure detection method according to claim 1, wherein the failure detection method detects the occurrence of a failure in the system that controls the transmission and reception.