JPS6240544A - Fault detecting system - Google Patents

Abstract

PURPOSE:To point out a faulty part by constituting the titled system so that a request can be sent out continuously before receiving a reply, an detecting whether the number of reception of the second and its subsequent replies has exceeded a prescribed value or not. CONSTITUTION:With respect to a read request 1, the first reply is reported by setting the first reply receiving flip-flop 119. A request flag which has been read out of a word position of a request flag buffer 109, and a reply flag of a reply flag register 123 which is reported simultaneously with the first reply are compared by a comparing circuit 112. When both of them do not coincide, it is reported as a request reply control fault to a fault processing part 124. Also, a reply counter 115 is counted up by the second and its subsequent, replies, and when one upper bit becomes '1', it is decided to have received a surplus reply and it is reported as a request reply control fault.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a failure detection method for information processing devices, and particularly to a failure detection method for controlling transmission and reception between information processing devices using a request-reply method.

(Prior art) Conventionally, when detecting a failure in transmission/reception control between information processing devices using the request-reply method, there was no detection circuit that specifically focused on the failure, and the information processing device on the sending side did not have a detection circuit that specifically focused on the failure. This was accomplished by detecting that the processing of an instruction was not completed within the maximum execution time of one instruction (detected when no rewrite was received).

FIG. 2 is a block diagram showing an example of implementing a memory access method using a request reply method according to the prior art. In FIG. 2, 201 is an arithmetic control unit;
02 to 204 are request code registers with different formats, 205 is a logical address register, 206 is a real address register, 207, 208, 214 are write data registers with different formats, 209 is a real address translation buffer, and 210 is a medium address register. 211 memory access address register, 212 selection circuit, 2
15 is a data register, 215 is a memory access control circuit, 216 is a request clip-flop, 2
1T is a request flag buffer write address register z, 218 is a request flag buffer read address register, 219 is a request flag buffer, 220
is the first reply reception clip 70, and 221 is the second reply reception clip.
Reference numeral 20 and 222 for receiving a reply is a memory control unit.

In FIG. 2, a request code is set in a request code register 202 as information for accessing the memory from an arithmetic control unit 201, a logical address is set in a logical address register 205, store data is set in a write data register 207, and arithmetic control is performed. A request is sent from the unit 201 to the memory access control circuit 215. The memory access control circuit 215 determines the type of memory access from the contents of the request code register 202, sets the result of real address translation in the real address translation buffer 209 to the real address register 206, and sets the request code to the request code register 203. , stores the store data to the write data register 20B. If the data exists in the cache 210 in the read request, the memory control unit 222
The data is returned to the arithmetic control unit 201 through a selection circuit 212 that can select the data from the computer. If it is a ride request, an instruction to write the data in the write data register 208 to the cache 210 is given.

When the data does not exist in the cache 210 due to a read request, or when a ride request is made, a request code is set in the request code register 204 to instruct the memory control unit 222 to read/write data, and a memory read/write address is set. Set the memory access address register 211, write data to the write data register 214, and in addition request 7. The request is sent by setting the flipfrog 216.

When the request clip flop 216 is set,
The request flag from the request code register 204 is written into the request flag buffer 219, and the buffer write address register 211 is updated for the next write. Similarly, if there are consecutive requests to the memory control unit 222, the request flag is buffered in the request 7 lag patch 7a 219 and the contents of the buffer write address register 217 are updated.

Thereafter, upon completion of memory access, the memory control unit 2
22, the first reply or the second and subsequent regraes are returned.

In general, after reading 8 bytes of memory, when the first 8 bytes of data in a block read (transferred 8 times by 8 bytes) are returned, and when the first reply is given to a store and the block is When the subsequent 8 bytes other than the first read are transferred and the data for seven times is returned, the second and subsequent rewrites are returned.

When the first reply is received by the first reply reception flip-flop 220, the request flag buffer 219
The first reply is sent to the memory control unit 222 along with the content of the reply, and the memory control unit 222 determines the type of reply.
Controls whether or not request data is returned to the calculation control unit 201. At the same time, the request 7 lag buffer read address register 218 is updated to read the contents of the next request flag buffer 219.

When the second and subsequent replies are received by the second and subsequent reply reception flip-flops 221, the existence of the second and subsequent replies is reported to the memory access control circuit 215, and the memory control unit 222 synchronizes with the gray signal. It controls writing of the block load data set in the memory read data register 213 to be transferred to the cache 210.

As explained above, in the prior art, a special failure detection circuit particularly related to request reply control was not prepared.

(Problems to be Solved by the Invention) Since there is no direct means of detecting control failures in the conventional request-reply method described above, it is indirectly caused by inter-instruction timeouts (for example, when a waiting reply is not returned). ) or an unpredictable situation due to data corruption (e.g., too many replies, or rewriting in the wrong order) makes it difficult to pinpoint the failure point. It had the disadvantage of being.

An object of the present invention is to receive a first reply or a plurality of second and subsequent regraes in response to one request, and to continuously write data to a request flag buffer before receiving the first reply after sending the request. The system is configured to eliminate the above drawbacks and point out failure points by detecting whether or not the number of replies received after the second one exceeds a specified value. The object of the present invention is to provide a fault detection method.

(Means for Solving the Problems) The failure detection method according to the present invention is for a system that controls transmission and reception between information processing devices using a request reply method, and includes a receiving means, a request flag buffer, and a request flag buffer. It is configured to include a flag 74 sofa write address register, a request flag buffer read address register, second and subsequent reply counters, and detection means.

The receiving means is for receiving a first reply, or a first reply and a plurality of regraes subsequent to the first reply in response to one request.

The request flag buffer has a capacity that allows continuous requests to be sent after the request is sent and before the first retry of the request is received.

The request flag buffer write address register is
This is for updating the write address of the request 7 lag buffer when sending a request.

The request flag buffer read address register is
This is for updating the read address of the request flag buffer when receiving a reply.

The second and subsequent reply counters are cleared when the first retry is received, and are for counting the number of received replies from the second and subsequent replies.

The detection means is for detecting that the reception number count value of the second and subsequent reply counters exceeds a specified value.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention, and only shows a request reply control section that is different from the conventional block diagram shown in FIG.

In FIG. 1, 101 is a request code register;
102 is a memory access address register, 10s line ply data register, 104 is a write data register, 10s is a request 7 lip flop, 106 is a memory access control circuit, 107 is a request 7 lag buffer read address register, 108 is a request flag buffer write address register, 109 is a request flag buffer, 110-11! , 122.116 are the first to fifth comparison circuits, 113°117.118 respectively.
are the first to eighth AND gates, respectively; 114 is a second and subsequent retry valid display flag; 11B is a second and subsequent reply counter; 119;

120 respectively the first and second and subsequent reply reception 7
Lip 70, 121 is a request retry counter, 123 is a reply flag register, 1!4 is a fault processing control unit, 126 and 127 are NAND gates, 1
25 is a memory control section.

In this example, the request type is read request 1,
Limited to three types: lead request 2 and ride request. Read request 1 gives only the first reply to one request, and read request 2
gives the first reply and the following 2nd to 8th replies to one request, and the ride request gives the first reply to one request. Further, the following description will be made assuming that the number of requests that can be sent out consecutively before receiving a reply is 15.

First, the operation when sending a request will be explained.

When the request flip-flop 106 is set and enters the request sending state, the request code register 1
Information for classifying read request 1/read request 2/ride request among the contents of 01 is stored in request flag buffer 109 consisting of 16 words. That is, in this case, the request flag buffer write address register 108 consists of 5 bits of the request flag buffer 109 (initial value is 1 for all bits).
The above information is stored in the word position indicated by 0I), and at the same time the request flag buffer write address register 1 is stored.
The contents of 08 are counted up to indicate the next word position. The initial value is %ON for all bits, and the request retry counter 121, which is composed of 5 bits, is counted up and the number of requests waiting to be replayed is displayed. Here, when a reply is received, count-up is suppressed.

Next, the operation at the time of regrie reception will be explained. - For read request 1, a first retry is reported by setting the first reply receiving clip 70 knob 22G. It consists of 5 bits: 1. Initial value is all bits%
The request flag successively read from the word position of the request flag buffer 109 indicated by the request flag buffer read address register 107 set in OI and the rewrite flag of the reply flag register 123 reported simultaneously with the first reply are A comparison circuit 112 compares the signals. If there is a mismatch between the two, it is determined that the reply is different from the predicted reply, and the failure processing unit 1
24 is reported as a request reply control failure.

Furthermore, the request reply counter 121 is counted down, and the request 7 lag buffer read address register 101 is counted up in order to prepare for the next request flag buffer 109 operation.

For read request 2, the first rewrite is reported by sending the first reply reception clip 70 knob 119, and in addition to the same operation as read request 1, the second and subsequent requests following the reply are The retry counter 115, which is composed of 4 pits for counting the number of rewrites, is cleared to the initial value (all bits %OI) and waits for the second and subsequent replies. Subsequently, the second and subsequent rewrites are performed by the second reply reception 7 rewrite flop 120.
When it is reported by setting, the retry counter 115 is counted up, and the reply valid wait flag V for read request 2 (read out from the request flag buffer 109 and held before receiving the first reply). ) is reset, the second AND gate 11 indicates that the second and subsequent replies have been received.
7, it is determined that the reply is different from the predicted reply, and is reported to the failure processing control unit 124 as a request reply control failure.

Further, the retry counter 116 is counted up by the second and subsequent retry, and in order to detect the waiting for the last reply after the second, the contents of the retry counter 115 R2C are sent by the NAND gates 126 and 127.
=6 is detected by the fifth comparison circuit 116, and when the second and subsequent replies are received, the output of the third AND gate 118 resets the v flag F/F 114 and waits for a reply to read request 2. Disable.

Furthermore, when the second and subsequent replies are received, R2O) becomes 7, and when the upper 1 bit of the reply counter 116 becomes %11, it is determined that an extra reply has been received, and a request reply control failure is reported to the failure processing control unit 124. do.

For store requests, the operation is the same as read request 1.

Additionally, a buffer write address register 108 controls writing/reading of the request flag buffer 109.
and request flag buffer read address register 1
07, the maximum difference is always 15, and the buffer write address register 108 and the request flag buffer read address register 101 are used to prevent the serial reply control from falling into an unexpected situation due to request advance.
A first AND gate 1113 detects the logical product of the mismatch output from the first comparison circuit 110 for the upper bits and the match output from the second comparison circuit 111 for the lower four pits. This is reported as a request reply control failure to the failure processing control unit 124.

In addition, to prevent unforeseen situations from occurring in the Sirikuni reply control due to advance retry when a request has not been sent,
The request reply counter 121 has all bits 111 (
The fourth comparison circuit 12 determines that the counter value is %1#).
2, and further detects that the upper 1 bit of the request retry counter 121 is 111 (counter: overflow) and handles the failure so that the silicon reply control does not fall into an unexpected situation due to request precedence. A request reply control failure is reported to the control unit 124.

(Effects of the Invention) As explained above, the present invention receives the first reply or a plurality of second and subsequent replies in response to one request, and before receiving the first replay after sending the request. By making it possible to send requests continuously to the request flag buffer and by detecting whether the number of received replies after the second one exceeds a specified value, a request re-grid method can be implemented with the addition of less hardware. This has the advantage of being able to quickly detect control failures and correctly localizing the location of the failure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention. FIG. 2 is a block diagram showing an example of implementing a failure detection method according to the prior art. 101.202-204... Reference request code register 102.211... Memory access address register 10! , 213...Reply data register 104.
207, 208, 214 Φ/Write arter register 106.216...Request free flag frog 106.215...Memory access control circuit 107.
218...Request flag buffer successive address register 108.217...Request flag buffer write address register 109.19...Request flag buffers 110 to 112, 122.116...Comparison circuit 113.
117, 118... AND gate 114... φ2nd and subsequent reply valid display 7 lag 115... 2nd and subsequent glue ply color/re 119...
First reply reception flip 70 knob 120.221... Second and subsequent reply reception 7 rig 70 knob 121... Request reply color/re 12! ---・
Reply flag register 124...failure processing control unit 12B, 222...mesh control unit 128.127---NAND gate 201...arithmetic control unit 205---logical address register 206@-real address register 210...Kakyu 212...-Selection circuit

Claims (1)

[Claims] A fault detection method for a system that controls transmission and reception between information processing devices using a request-reply method, in which a first reply, or a plurality of replies including the first reply and the second and subsequent replies are received in response to one request. a request flag buffer having a capacity capable of continuously transmitting requests after transmitting the request and before receiving the first reply of the request; a request flag buffer write address register for updating the write address of the flag buffer; a request flag buffer read address register for updating the read address of the request flag buffer when receiving the reply; and receiving the first reply. a second and subsequent reply counter for counting the number of received replies from the second and subsequent replies; and a second and subsequent reply counter for detecting that the reception count value of the second and subsequent reply counters exceeds a specified value. 1. A failure detection method comprising: a detection means.