JPS6240545A - Fault detecting system - Google Patents

Abstract

PURPOSE:To point out a faulty part by constituting the titled system so that a request can be sent out continuously before receiving the first reply, and deciding the second and its subsequent replies. CONSTITUTION:With respect to a read request 1, the first reply is reported by setting the first reply receiving flip-flop 119. A request flag which has been read out of a word position of a request flag buffer 109, and a reply flag of a reply flag register 123 which is reported simultaneously with the first reply are compared by a comparing circuit 112. When both of them do not coincide, it is reported as a request reply control fault to a fault processing part 124. Also, when a reply effective waiting flag read out and held from a request flag buffer 109 has been reset, when it is detected by an AND gate 117 that the second and its subsequent replies have been received, it is reported as a request reply control fault.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a fault detection method for an information processing device, and
The present invention relates to a failure detection method for controlling transmission and reception between information processing devices using the JQuest reply method.

(Prior art) Conventionally, when detecting a failure in transmission/reception control between information processing devices using the request-reply method, there is no detection circuit that specifically focuses on the failure, and the information processing device on the sending side has a This was accomplished by detecting that the processing of an instruction was not completed within the maximum execution time of one instruction (detected when no reply was received).

FIG. 2 is a block diagram showing an example of implementing a memory access method using a request reply method according to the prior art. In FIG. 2, 201 is an arithmetic control unit;
02 to 204 are request code registers of different formats, 20s is a logical address register, 206 is a real address register, 207, 208, 214 are each included data registers of different formats, 209 is a real address translation buffer, and 210 is a Cache, 211 is a memory access address register, 212 is a selection circuit, 2
13 is a reply data register, 216 is a memory access control circuit, 216 is a request flip-flop, 2
11 is a request flag buffer write address register, 218 is a request flag buffer read address register, 219 is a request flag buffer, 220
is the first reply reception flip-frog, 221 is the second
The following reply reception flip-flop 222 is a memory control unit.

In FIG. 2, the request code register 20 is set as information for accessing the memory from the arithmetic control unit 201, the logical address is set in the logical address register 205, and store data is set in the write data register 201. , a request is sent from the arithmetic control unit 201 to the memory access control circuit 215. The memory access control circuit 215 determines the type of memory access from the contents of the request code register 202, sets the result of real address conversion in the real address conversion buffer 209 to the real address register 206, and sets and stores the request code in the request code register 203. Write data and set it in data register 20B. If the data exists in the cache 210 in the read request, the memory control unit 222
The data is returned to the arithmetic control unit 201 through a selection circuit 212 that can select the starting ply data. If it is a ride request, an instruction to write the data in the write data register 20B to the cache 210 is given.

When the data does not exist in the cache 21 (1) due to a read request, or when a ride request is made, a request code is sent to the request code register 204 to instruct the memory control unit 222 to read/write the data.
, the memory read/write address is set in the memory access address register 211, the write data is set in the write data register 214, and in addition, the request flip-flop 21B is set to send the request.

When the request flip-flop 21B is set,
The request flag from the request code register 204 is written to the request flag back 7219, and the buffer write address register 21γ is updated for the next write. Similarly, if there are consecutive requests to the memory control unit 222, the request flag is buffered in the request flag buffer 7219 and the contents of the buffer write address register 217 are updated.

Thereafter, upon completion of memory access, the memory control unit 2
22 returns the first reply or the second and subsequent replies. In general, after reading 8 bytes of memory, when the first 8 bytes of data in a block read (8 bytes transferred 8 times) are returned, and when the first reply is sent to a store, the block When the subsequent 8 bytes other than the first read are transferred and the data for seven times is returned, the second and subsequent replies are returned.

When the first reply is received by the first reply reception flip-flop 220, the request flag buffer 219
The first reply is sent to the memory control unit 222 along with the contents of the message, the memory control unit 222 determines the type of reply, and
Controls whether or not request data is returned to the calculation control unit 201. At the same time, the request flag buffer read address register 218 is updated in order to read the contents of the primary request flag buffer 219.

When the second and subsequent replies are received by the second and subsequent reply reception flip-frog 221, the existence of the second and subsequent replies is reported to the memory access control circuit 215, and the memory control unit 222 transfers it in synchronization with the reply signal. The block load data set in the memory read data register 213 is controlled to be written to the cache 210.

As explained above, in the prior art, a special failure detection circuit particularly related to request reply control was not prepared.

(Problems to be Solved by the Invention) Since there is no direct means of detecting control failures in the conventional request-reply method described above, it is possible to indirectly detect inter-instruction timeouts (for example, when a waiting reply is not returned and an instruction execution does not finish), or unpredictable situations due to day or evening events (for example, a situation where many replies are returned or replies are sent in the wrong order)
The problem was that it was difficult to pinpoint the location of the failure.

An object of the present invention is to receive a first reply or a plurality of second and subsequent replies in response to one request, and to continuously receive requests using a request flag buffer before receiving the first reply after sending the request. It is an object of the present invention to provide a fault detection method configured to enable transmission, eliminate the above-mentioned drawbacks by determining the second and subsequent replies, and point out the location of the fault.

(Means for Solving Problems) The failure detection method according to the present invention is for a system that controls transmission and reception between information processing devices using a request reply method, and includes a receiving means, a request flag buffer, and a request flag buffer. It is configured to include a write address register, a request 7 lag buffer read address register, a reply counter, a plurality of reply reception type display means, and a detection means.

The receiving means is for receiving a first reply or a plurality of replies including the first reply and the second and subsequent replies in response to one request.

The request flag buffer has a capacity that allows continuous requests to be sent after the request is sent and before the first reply to the request is received.

The request 7 lugba sofa I address register is
This is for updating the write address of the request 7 lugba sofa when sending a request.

The request flag buffer continuous address register is
This is for updating the read address of the request flag buffer when receiving a reply.

The reply counter is for counting the number of replies received after the second reply.

The multiple reply reception type display means is set by being recognized from the request flag buffer, and is configured so that it can be reset by logical product of the reply counter value (default value - 1) and the second and subsequent replies. .

The detection means is for detecting that the second and subsequent replies have been received while the multiple reply reception type display means is off.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention, and only shows a request reply control section that is different from the conventional block diagram shown in FIG.

In FIG. 1, 101 is a request code register;
102 is a memory access address register, 103 is a reply data register, 104 is a write data register, 105 is a request free flag flop, 106 is a memory access control circuit, 107 is a request flag buffer read address register, 108 is a request flag Buffer write address register, 109 is request 7 lag computer, 110 to 112, 122, and 116 are first to fifth comparison circuits, respectively, 113゜117.118
．． 126 are the first to fourth AND games), 114
is the second and subsequent and reply valid display flags, 115 is the reply counter for the second and subsequent ones, and 119 and 120 are the first and subsequent replies, respectively.
and second and subsequent reply receiving flag flops, 12
1 is a request reply counter, 123 is a reply flag register, 124 is a failure processing control section, and 125 is a memory control section.

In this embodiment, read request S type request 1,
Lead request 2 and ride request 8s
limited to types. Read request 1 gives only the first reply to one request, and read request 2
gives the first reply and the following 2nd to 8th replies to one request, and the ride request gives the first reply to one request. Further, the following description will be made assuming that the number of requests that can be sent out consecutively before receiving a reply is 15.

First, the operation when sending a request will be explained.

When the request free flag 105 is set and the request is sent, the request code register 1 is set.
Information for classifying read request 1/read request 2/ride request among the contents of 01 is stored in request flag buffer 109 consisting of 16 words. That is, in this case, the request flag buffer write address register 108 (initial value is all bits) consisting of 5 bits of the request flag buffer 109
Store the above information in the word position indicated by 0 #),
At the same time, the contents of the request flag buffer write address register 108 are counted and amplified to indicate the next word position. In addition, the initial value is 5 bits for all bits %OI, and a query stripply counter 121 is counted up to display the number of requests waiting for a reply. Here, when a reply is received, count-up is suppressed.

Next, the operation when receiving a reply will be explained.

For read request 1, the first reply is reported by setting the first reply reception frig flag 220. The request flag is read from the word position of the request flag buffer 109 indicated by the request flag buffer read address register 101, which consists of 5 bits, and the initial value is set to all bits %OI, and the request flag is reported simultaneously with the first reply. The reply flag of the reply flag register 123 is compared with the reply flag of the reply flag register 123 by the third comparison circuit 112. When the two do not match, it is determined that the reply is different from the predicted reply, and is reported to the failure processing unit 124 as a request request control failure. Furthermore, the request reply counter 121 is counted down, and the next request 7 lag buffer 109 is counted down.
In order to prepare for the operation, the request flag buffer read address register 101 is counted up.

For read request 2, the first reply is reported by setting the first reply reception 7 logic flop 119, and in addition to the same operation as read request 1, the second and subsequent replies following the reply are A reply counter 116 consisting of 4 bits for counting the number of is cleared to an initial value (total bits % Q #) and waits for the second and subsequent replies. Subsequently, the second and subsequent replies are sent to the second reply reception 7 reply block 1.
When the request is reported by setting 20, the reply counter 116 is counted up and read request 2 is sent.
When the reply valid wait 7 lag V (read out from the request flag buffer 101 and held before receiving the first reply) is reset,
When the second AND gate 111 detects that the second and subsequent replies have been received, it is determined that the reply is different from the predicted reply, and is reported to the failure processing control unit 124 as a request reply control failure.

Furthermore, the reply counter 115 is counted up by the second and subsequent replies, and in order to detect waiting for the last reply after the second reply, the content R of the reply counter 116 is increased.
When the fifth comparison circuit 116 detects 2C=6 and receives the second and subsequent replies, the third AND gate 11
8 and the output of the fourth AND gate 126)) The flag F/F 114 is reset to disable the reply wait for the read request 2. Furthermore, when the second and subsequent replies are received, the error processing control unit 12 determines that an extra reply has been received.
4 Report as a helicopter request rib control failure.

For store requests, the operation is the same as read request 1.

Additionally, a buffer write address register 108 controls writing/reading of the request flag buffer 109.
and request flag buffer read address register 1
07, the maximum difference is always 15, and the buffer write address register 108 and the request flag buffer read address register 101 are used to prevent request response control from falling into an unexpected situation due to request precedence.
The first AND gate 11iS detects the AND of the mismatch output of the first comparator circuit 11Q for the upper bits and the match output of the second comparator circuit 111 for the lower 4 bits, and detects the fault. This is reported as a request reply control failure to the processing control unit 124.

In addition, to prevent request reply control from falling into an unexpected situation by pre-replying when a request has not been sent,
Request reply counter 121 indicates all pits 111 (
The fourth comparison circuit 12 determines that the counter value is %l#).
2, and further detects that the upper 1 bit of the request reply counter 121 is 111 (color/rinio-puff 0-) to prevent the request reply control from falling into an unexpected situation due to request precedence. Reports a request reply control failure to the processing control unit 124.

(Effects of the Invention) As explained above, the present invention receives a first reply or a plurality of second and subsequent replies in response to one request, and before receiving the first reply after sending the request. By making it possible to send multiple requests in succession over the request 7 lag buffer and determining the second and subsequent replies, it is possible to quickly detect control failures in the request-reply method with the addition of less hardware. This has the effect of allowing accurate limitation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention. FIG. 2 is a block diagram showing an example of implementing a failure detection method according to the prior art. 101.202-204...Request code register 102.211...Memory access address register 10i211S-...Reply data register 104.
207.208, 214-m--Write data register 105.216--Request 7 Rig flop 106.2115--Memory access control circuit 107
．． 218・11@Request flag buffer read address register 108.217---Request flag 7a Write address register 109.219...φRequest flag buffer 110 to 112, 122, 116・Juku comparison circuit 113.
117, 118.126 ・ ・ ・ AND gate 114 @ Reply valid display 7 lag from e number 2 onwards F/F 116... Reply counter 119 from fist 2 onwards...
First reply reception flip frog 120.221...Second and subsequent reply reception clip frog 121...Request reply counter 123...
Reply flag register 124...Fault processing control unit 125.222...Memory control unit 201...Arithmetic control unit 206...Logical address register 206...Real address register 210--Cache 212... selection circuit

Claims (1)

[Claims] A fault detection method for a system that controls transmission and reception between information processing devices using a request-reply method, in which a first reply, or a plurality of replies including the first reply and the second and subsequent replies are received in response to one request. a request flag buffer having a capacity capable of continuously transmitting requests after transmitting the request and before receiving the first reply of the request; a request flag buffer write address register for updating the write address of the flag buffer; a request flag buffer read address register for updating the read address of the request flag buffer when receiving the reply; and a request flag buffer read address register for updating the read address of the request flag buffer when receiving the reply, and receiving the second and subsequent replies. a reply counter for counting the number of replies recognized from the request flag buffer and set;
a plurality of reply reception type display means that can be reset by a logical product of the value of the reply counter (definition value - 1) and the second and subsequent replies; 1. A failure detection method comprising: a detection means for detecting that a subsequent reply has been received.