JPH0750746B2 - Memory cell for complementary MOS static RAM - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a structure of a complementary MOS static RAM memory cell structure.

[Conventional technology]

A memory cell for a static RAM (Random-Access-Memory) of a complementary MOS (Metal-Oxide-Semicondactor) has a circuit configuration shown in FIG. N-channel MOSFET (Fi
The sources of N1 and N2 are connected to the ground potential (marked as GND), and P-channel MOSFET P1
And the sources of P2 are connected to a power supply (denoted VDD). N
Drain of channel type MOSFET N1 and P channel type MOSFET P1, N channel type MOSFET N2 and P channel type MO
The gates of SFETP2 are commonly connected at node A, the drains of N-channel type MOSFET N2 and P-channel type MOSFET P2, N-channel type MOSFET N1 and P-channel type MOSF.
The gates of ETP1 are commonly connected at node B. The N-channel type MOSFET N3 is connected between the node A and the bit line D, the N-channel type MOSFET N4 is connected between the node 2 and the bit line D, and the word line W is connected to each gate.
In this structure, both the P-channel type MOSFET and the N-channel type MOSFET are conventionally formed on the conductive substrate, and a large amount of element isolation region has been required. Methods have been proposed to reduce the area. An example of this is shown in FIG. FIG. 4 (a) is a plan view and FIG. 4 (b) is FIG. 4 (a).
FIG. 9 is a sectional view taken along line XX ′ in FIG. 301 is an N-type region formed on a single crystal silicon substrate 315 that serves as the drain and source of MOSFET N1 in FIG. 3, 302 is an N-type polycrystalline silicon layer that serves as a gate common to MOSFETs N1 and P1, and 303 is a polycrystalline silicon layer. A silicon film thin film for forming MOSFET P1 provided on the upper part of 302. 304 is an N-type region that forms MOSFETs N2 and N4, 305 is an N-type polycrystalline silicon layer that will be the gates of MOSFETs N2 and P2, 306 is a silicon film thin film that forms MOSFET P2, and 307 is
N-type polycrystalline silicon layer serving as the gates of MOSFETs N3 and N4, 308
Is an N-type region forming the MOSFET N3. Reference numeral 313 is a contact hole portion, and 314 is a metal layer forming a wiring. Regions e and f in FIG. 4 (a) are connection regions corresponding to the nodes AB in FIG. 3, respectively. FIG. 4 (b) is a sectional view taken along the line XX 'of the region e in FIG. 4 (a) and shows the structure of the node A. Reference numeral 310 is a silicon oxide layer that serves as a gate insulating film or an element isolation layer of the MOSFET on the substrate, an opening of 310 of 311 and 312 is an insulating film made of, for example, silicon oxide. The connection method with V _DD , GND or bit line D in FIG.

[Problems to be solved by the invention]

In the memory cell for complementary MOS static RAM using the conventional thin film transistor described above, nodes A and B in FIG.
In the example of the region e shown in FIG.
N-type region 301 and N-type polycrystalline silicon 305 are silicon oxide layers
Although the connection is made at the opening 311 of the 310, the connection between the N-type polycrystalline silicon 305 and the P-type silicon thin film 303 is performed by once forming the interlayer insulating film 312 and separating them from each other, and then opening the contact hole 313. Then, the connection is made by the metal wiring layer 314. Therefore, a region for opening two contact holes 313 is necessary, which limits the reduction of the memory cell. Also,
Since the metal wiring layer 314 is used, there is a drawback that the wiring area such as the bit line and the power source is restricted to prevent the reduction of the memory cell, or the design of a new wiring layer passing over the wiring layer 314 is complicated. .

[Means for solving problems]

According to the present invention, the first and second MOSFETs of the first conductivity type are formed on a semiconductor substrate, and the third and fourth MOSFETs of the second conductivity type are formed in a silicon thin film. 1
And the gate electrodes of the third MOSFET are commonly formed by the first polycrystalline silicon layer of the first conductivity type, and the gate electrodes of the second and fourth MOSFETs are formed.
The gate electrode of the MOSFET is commonly formed by a second polycrystalline silicon layer of the first conductivity type, the sources of the first and second MOSFETs are connected to a first potential, and the third and fourth MOSFs are connected.
The source of ET is connected to a second potential and said first
A part where a part of the drain of the MOSFET and a part of one main surface of the second polycrystalline silicon layer are directly connected, and a part of the other part of the second polycrystalline silicon layer immediately above the connected part. A first contact for electrically connecting a part of the main surface with a part of the drain of the third MOSFET in contact with the second polycrystalline silicon layer and the drain of the third MOSFET. A first connection region composed of a portion formed with a conductive material, a part of the drain of the second MOSFET and a part of one main surface of the first polycrystalline silicon layer were directly connected. And a portion of the other main surface of the first polycrystalline silicon layer and the fourth portion immediately above the connected portion.
The part where the drain of the MOSFET is in contact with a part of the first
Complementary type characterized in that it has a second connection region composed of a polycrystalline silicon layer and a second conductive material portion for conducting mutual conduction between the drain of the fourth MOSFET. A memory cell for MOS static RAM can be obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) and 1 (b) show an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is an X- line in FIG. 1 (a). It is a X'sectional view. 1 is MO in FIG.
An N-type region on the single-crystal silicon substrate 115 forming the SFET N1; 2 is an N-type polycrystalline silicon layer serving as the gates of the MOSFETs N1 and P1; 3 is an MO provided on the N-type polycrystalline silicon layer.
Silicon thin film forming SFETP1, 4 is an N-type region forming MOSFETN2, N4, 5 is an N-type polycrystalline silicon layer serving as a gate of MOSFETN2, P2, 6 is a silicon thin film forming MOSFETP2, 7 is MOSFETN3, An N-type polycrystalline silicon layer serving as a gate of N4, 8 is an N-type region forming MOSFET N3, and a and b are connection regions corresponding to nodes A and B, respectively. Reference numeral 9 is a conductor layer made of a metal or a metal silicide for connecting the N-type polycrystalline silicon layer 5 and the silicon thin film 3, 10 is an element isolation region made of, for example, silicon oxide, 11 is an opening portion of the silicon oxide 10, and 12 is, for example, oxidized. It is an insulating layer made of silicon.

Next, the structure of the region a will be described in more detail with reference to FIG. The N-type region 1 is connected to the N-type polycrystalline silicon 5 through the opening 11 of the silicon oxide film 10. Next, the P-type silicon thin film 3 is brought into contact with the upper surface of the N-type polycrystalline silicon 5. At this time, a PN junction is formed on the connection surface. Here, a conductor layer 9 that overlaps both the N-type polycrystalline silicon 5 and the silicon thin film 3 and makes a resistive connection with them is provided on the direct contact area, and the bidirectional Take continuity. Therefore, the contact area between the N-type polycrystalline silicon 5 and the silicon thin film may be extremely small, and the area of the conductor layer 9 may be the minimum area in the manufacturing process. Furthermore, since the conductor layer 9 has a sufficient effect even if it is a thin layer, it is easy to form the insulating layer 12 on the upper portion, and it is possible to freely provide another wiring on the upper portion of the same region.

2 (a) and 2 (b) show another embodiment of the present invention. 2 (a) is a plan view and FIG. 2 (b) is a second view.
It is a XX 'sectional view of FIG. Symbols 201 to 212 in the figure correspond to 1 to 12 in FIG. 1, and c and d correspond to a and b in FIG. 1, respectively. The difference between FIG. 2 and FIG. 1 is the conductor layer 20.
9 is sandwiched between the N-type polycrystalline silicon 205 and the silicon thin film 203. In this embodiment, N
Since the conductor layer having a low resistance is provided immediately after the formation of the type polycrystalline silicon layer, it is possible to measure the low resistance of the wiring by forming the conductor layer also in the portion where the N type polycrystalline silicon is used as the wiring.

〔The invention's effect〕

As described above, according to the present invention, the N-type polycrystalline silicon layer and the silicon thin film are brought into contact with each other in a minute area, and the conductor layer for conducting bidirectional conduction may be the minimum area in manufacturing. is there. Further, the wiring can be freely passed through the upper portion of the connection region, and the design can be simplified.

[Brief description of drawings]

1 (a) is a plan view of an embodiment of the present invention, FIG. 1 (b) is a sectional view taken along line XX 'of FIG. 1 (a), and FIG. 2 (a).
Is a plan view of another embodiment of the present invention, FIG. 2 (b) is a sectional view taken along line XX 'of FIG. 2 (b), and FIG. 3 is a circuit diagram of a memory cell for complementary MOS static RAM. FIG. 4 (a) is a plan view of the conventional example, and FIG. 4 (b) is a sectional view taken along line XX 'of FIG. 4 (a). 1,4,8,201,204,208,301,304,308 …… N-type region of single crystal silicon substrate, 2,5,7,202,205,207,302,305,307 …… N
Type polycrystalline silicon, 3,6,203,206,303,306 …… Silicon thin film, 9,209 …… Conductor layer, 10,210,310 …… Silicon oxide, 11,211,311 …… Silicon oxide openings, 12,212,312…
… Insulating layer, 313 …… Contact hole, 314 …… Wiring layer, 115,
215,315 …… single crystal silicon substrate, a, b, c, d, e, f …… connection region, N1, N2, N3, N4 …… N-channel MOSFET, W ……
Word line, D, ... bit line, V _DD ... power supply, A, B ... node.

Claims (3)

[Claims] 1. A first conductivity type first and second MOSFET formed on a semiconductor substrate, and a second conductivity type third and fourth MOSFET formed in a silicon thin film. The gate electrodes of the first and third MOSFETs are commonly formed by the first polycrystalline silicon layer of the first conductivity type, and the gate electrodes of the first and third MOSFETs are formed in common.
A gate electrode of the SFET is commonly formed by a second polycrystalline silicon layer of the first conductivity type, sources of the first and second MOSFETs are connected to a first potential, and the third and fourth MOSFETs are connected.
Of the drain of the first MOSFET and a portion of one main surface of the second polycrystalline silicon layer directly in the complementary MOS static RAM memory cell connected to the second potential. The connected portion, the portion directly above the connected portion, where a portion of the other main surface of the second polycrystalline silicon layer and a portion of the drain of the third MOSFET are in contact, and the second portion Polycrystalline silicon layer and the third MOSF
A first connection region composed of a portion in which a first conductive material for conducting mutual conduction of the drains of the ET is formed;
A portion where a part of the drain of the second MOSFET is directly connected to a portion of one main surface of the first polycrystalline silicon layer, and the first polycrystalline silicon is provided immediately above the connected portion. In order to electrically connect a part of the other main surface of the layer and a part of the drain of the fourth MOSFET in contact with each other, the first polycrystalline silicon layer and the drain of the fourth MOSFET. 2. A memory cell for complementary MOS static RAM, comprising: a second connection region composed of a portion in which the second conductive material is formed. 2. The first conductive material extends over the other part of the other main surface of the second polycrystalline silicon layer and the drain of the third MOSFET immediately above the connected portion. The second conductive material is formed over the other portion of the other main surface of the first polycrystalline silicon layer and the drain of the fourth MOSFET immediately above the connected portion. The memory cell for complementary MOS static RAM according to claim 1, wherein 3. The first conductive material is formed on another part of the other main surface of the second polycrystalline silicon layer immediately above the connected portion, and the first conductive material is formed on the other part of the other main surface of the second polycrystalline silicon layer. The drain is formed to extend on the first conductive material, and the second conductive material is formed on the other main surface of the first polycrystalline silicon immediately above the connected portion. 2. The memory for complementary MOS static RAM according to claim 1, wherein the drain of the fourth MOSFET is formed to extend over the second conductive material. cell.