JPH0750597A - Viterbi decoding circuit - Google Patents

Abstract

PURPOSE:To provide a viterbi decoder which can exclude the uncertainty of phase of a reproduced carrier wave out of the data that have undergone the soft decision with no calculating error and in the least hardware quantity even with the M-phase modulation (M=2<k>, k>integer of 2). CONSTITUTION:A branch metric circuit 17 includes a phase uncertainty excluding circuit 20 which excludes the uncertainty of phase of ((n+1)/2)pi out of a received symbol (n=0, 1, 2 and 3) when the lead-in phase of a reproduced carrier wave is not coincident with the phase of a transmitted carrier wave, a branch metric calculating circuit 11 which calculates the correlative value (branch metric) corresponding to the received symbol sent from the circuit 20 and the branch derived from each state, and a phase uncertainty excluding circuit 12 which excludes the uncertainty of phase of 1/4pi by replacing each branch metric after its calculation. Both circuits 20 and 12 are placed before and after the circuit 11. So that the hardware quantity of the circuit 12 can be extremely reduced compared with a conventional case where the phase uncertainty is excluded only after the circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding circuit,
In particular, the present invention relates to a Viterbi composite circuit used in a system for demodulating a phase-modulated modulated wave of eight or more phases by synchronous detection.

[0002]

2. Description of the Related Art For example, when a four-phase phase modulated (QPSK) modulated wave is demodulated by synchronous detection, 90 ° × n (n = 0, n = 0,
Phase uncertainties of 1, 2, 3) occur. Therefore, if the transmission data is (p, q), the receiving side will have (p, q), (/
There are four possible patterns: q, p), (/ p, / q), (q, / p) [where "/" represents inversion]. Demodulated data is (/ q, p), (/ p, /
In the case of patterns such as q) and (q, / p), the Viterbi decoder does not perform normal compounding, so the phase of the reproduced carrier wave is changed by 90 ° until normal decoding is performed, or Phase uncertainties are removed by logically operating the demodulated data (an operation that gives phase rotation to the demodulated data) before the branch metric calculation circuit of the Viterbi decoder.

Generally, the demodulated data (p, q) are quantized into about 8 values (3 to 4 bits) and input to a Viterbi decoder (soft decision) in order to obtain high error correction capability. However, the logical operation of the demodulated data is obtained by a simple arithmetic circuit such as inversion of each bit, and the error after quantization accompanying the phase uncertainty removal does not occur.

However, M phase modulation (MPSK) (P =
2 ^k , k> 2 integer), the decoded data is 360 ° /
Since phase indeterminacy of M × n (n = 0, 1, 2, ..., M-1) occurs, the phase indeterminacy is calculated from the demodulated data (soft decision data) after quantization before the branch metric calculation circuit. In order to remove the sex, soft decision data and sin (360 °
/ M × n) or cos (360 ° / M × n) must be multiplied. However, in order to execute this, an error occurs due to calculation accuracy, and in order to reduce this error, calculation accuracy is reduced. Need to increase.

The present inventor has proposed a circuit for avoiding this in Japanese Patent Application No. 4-1693. This calculates the branch metric assuming that the regenerated carrier is in phase with the transmitted carrier, and if the regenerated carrier is not in the correct pull-in phase, replace each branch metric so that the regenerated carrier matches the transmitted carrier phase. The phase uncertainty is removed by performing.

As an example, a case will be described with reference to the drawings in which the coding rate is ⅔ (the coding rate is represented by information bits ÷ code bits) to obtain 8-phase phase modulation (8PSK). FIG. 4 is a block diagram of this Viterbi decoding circuit.

A branch metric is calculated for the soft decision data 18 of two sequences (P channel and Q channel) demodulated by the demodulator and soft-decided into N bits. The branch metric data is input to the phase uncertainty removing circuit 12, but this phase uncertainty removing circuit 12a replaces the branch metric data on the assumption that the reproduced carrier wave is correctly reproduced with a phase difference of 0 from the reference phase on the transmitting side. It is sent to the ACS circuit 13 without performing it. The ACS circuit 13 adds the metric value of the surviving path up to the previous time read from the branch metric and the path metric memory 14, selects the most probable path, stores the metric value of the surviving path in the metric memory 14, and The code symbol corresponding to the path for the path is stored in the path memory 15.

The output 19 of the path memory 15 is the decoded data 1
It becomes 9. The synchronization determination circuit 16 is a circuit for comparing the soft-decision data 18 and the decoded data 19 with the encoded data again for a certain period of time, and confirming the code synchronization by the number of errors, and when the code synchronization is not established. Uses the fact that the Viterbi decoder does not decode correctly, so there are many errors and the number of errors decreases when code synchronization is established. When the number of errors is large, that is, when the code synchronization is not established, the synchronization determination circuit 16 sends a branch metric replacement signal to the phase uncertainty removal circuit 12a, and in response to this, the phase uncertainty removal circuit 12a. Replaces the branch metric equivalent to applying phase rotation to the soft decision data such as 45 °, 90 °, 135 °, and stops the replacement of the branch metric when the code synchronization is established.

FIG. 5 shows the branch metric circuit 17 shown in FIG.
Is a block diagram for explaining the configuration of the above, 31 to 38 are circuits for performing branch metric calculation of each codeword and soft decision data when the reproduction carrier has a phase difference of 0 from the reference phase on the transmission side, and are mainly added to the multiplier. Branch metric calculation circuit 11 of FIG.
49 to 56 are N-bit 8to1 selectors (N depends on the precision of the branch metric) for exchanging the branch metric to remove the phase indetermination, and correspond to the phase indeterminacy removing circuit 12a in FIG. Is.

When the coding rate of 2/3 is coded and the PQ orthogonal plane is assigned as shown in FIG. 3 to form 8PSK, the PQ corresponding to the codewords 000, 001, 010 ... The coordinates of the transmission data on the orthogonal plane are (Pn,
Qn) [n = 0,1,2, ..., 7, codeword 000,00
, 010 ..., 111] and the coordinates of the received data are (Rp, Rq), the branch metric when there is no phase uncertainty is the inner product of the transmitted data and the received data BMn = P _{n · R p · Q n · R} q [n = 0,1,2 ...,
7].

If the regenerated carrier undergoes a phase rotation of 45 ° (at this time, the received data has a phase rotation of -45 °), the true branch metric for the codeword 000 is the coordinate (P7, The inner product of Q7) and the received data should be given, and the branch metric bm0 for the post-code 000 after removing the phase uncertainty is the branch metric BM7 (38) when calculated assuming that there is no phase uncertainty. In this way, when the reproduced carrier wave is deviated from the reference phase on the transmission side, the branch metrics are replaced by selectors 49 to 5
6 is performed.

Phase shift of reproduced carrier wave and selector 49-
The selection of 56 is shown in Table 1 below. This table 1
, Bmn [n = 0,1,2 ... 7] represents a branch metric after phase correction, and BMn [n = 0,1,2 ...,
7] is a branch metric calculated assuming that the reproduced carrier wave has no deviation from the reference phase on the transmission side.

[0013]

[Table 1]

[0014]

As described above, the removal of the phase uncertainty in the conventional Viterbi decoding circuit has been described in the case of M-phase modulation (MPSK). For example, 8PS
In the case of K, if the branch metric is represented by N bits, eight N-bit 8to1 selectors are required to replace the branch metrics corresponding to the eight states and remove the phase uncertainty. Become. If a 1-bit 8 to 1 selector is configured with a CMOS gate array, about 20 gates are required. Therefore, if N = 7 bits, the entire phase uncertainty removing circuit has a circuit size of 20 gates × 7 bits × 8 pieces = 1120 gates. . As described above, the conventional method requires a large amount of hardware and has a problem that power consumption increases.

An object of the present invention is to provide M phase modulation (MPS).
To provide a Viterbi decoding circuit capable of removing the phase uncertainty from the data after soft decision with a minimum hardware amount without causing an error even in a multi-phase modulation method such as K). is there.

[0016]

According to the present invention, a branch metric circuit for taking a correlation value (branch metric) between a received symbol and a symbol corresponding to a branch derived from each state, and the branch metric and the previous time Selector circuit that adds the metric of the surviving path and selects the most likely path that joins in a certain state, metric memory that stores the metric of the surviving path calculated by this selector circuit, and memorize the surviving path In the Viterbi decoding circuit that includes a path memory that performs a code synchronization, and a synchronization determination circuit that establishes code synchronization, the branch metric circuit extracts from the received symbol if the lead-in phase of the reproduced carrier does not match the phase of the transmitted carrier ((( n + 1) / 2) π (n = 0, 1, 2, 3)
A first phase uncertainty removing circuit for removing the phase uncertainty of
A branch metric calculation circuit that calculates a branch metric of a correlation value between the received symbol output from the first phase uncertainty removing circuit and a symbol corresponding to a branch derived from each state, and a branch metric calculation circuit that calculates the branch metric of each branch metric after this branch metric calculation. A second phase uncertainty removing circuit for removing the phase uncertainty of 1 / 4π by performing replacement is provided.

In the present invention, in the case of 8PSK, for example, in order to remove the phase uncertainty of ((n + 1) / 2) π (n = 1,2,3), the branch metric calculation like QPSK is performed. Rotate the received symbols before doing ((n
+1) / 2) π (n = 0,1,2,3) is used to perform the branch metric calculation on the received symbol from which the phase uncertainty has been removed. This is dealt with by replacing the branch metric.

[0018]

1 is a block diagram of a Viterbi decoder according to an embodiment of the present invention. In the present embodiment, coding is performed at a coding rate of 2/3 (the coding rate is information bits / code bits),
The case where 8-phase phase modulation (8PSK) is used is shown.

The two series (P channel and Q channel) soft decision data 18 demodulated by the demodulator and soft-decided into N bits are input to the first phase uncertainty removing circuit 20, but are initially reproduced carrier waves. Is 0 from the reference phase on the transmission side
Then, the soft decision data is sent to the branch metric calculation circuit 11 without being replaced. The branch metric calculation circuit 11 calculates a correlation value (branch metric) for each symbol of each code sequence. The branch merit data is input to the second phase uncertainty removing circuit 12, but the phase uncertainty removing circuit 12 does not replace the branch metric data like the phase uncertainty removing circuit 20, and the ACS circuit 1 does not.
Send to 3.

The ACS circuit 13 adds the branch metric and the metric value of the surviving path up to the previous time read from the path metric memory 14, selects the most probable path, and sets the metric value of the surviving path to the metric memory 1.
4 and the code symbol corresponding to the path for the survivor path is stored in the path memory 15. The output 19 of the path memory 15 is the decoded data.

The synchronization decision circuit 16 is a circuit for comparing the soft-decision data 18 and the decoded data 19 with the encoded data again for a fixed time, and confirming the code synchronization by the number of errors, and the code synchronization is established. If not, the number of errors is large because it is not correctly decoded by the Viterbi decoder, and the number of errors is small when code synchronization is established. When the number of errors is large, that is, when the code synchronization is not established, the synchronization determination circuit 16 sends a soft-decision data replacement signal to the phase indetermination removal circuit 20, and in response to this, the phase indetermination removal circuit. 20 is 90 for soft decision data
The operation is performed so as to give the phase rotation of 180 °, 180 ° and 270 °, and the code synchronization is established again.

When the code synchronization is not established, the phase uncertainty removing circuit 20 applies the phase rotation of 45 ° to the branch metric and the phase uncertainty removing circuit 20 adds 0 ° to the soft decision data. The operation is performed so as to give the phase rotations of 90 °, 180 ° and 270 °. That is, 45 ° 135 °,
Phase synchronization of 225 ° and 315 ° is applied to establish code synchronization. When the code synchronization is established, the exchange of the branch metric is stopped. The order of applying phase rotation to the soft decision data is 0 °, 90 °, 180 °, 270 °, 45 °, 1
Although 35 °, 225 °, and 315 ° are set, there is no problem in another order.

FIG. 2 is a block diagram showing the configuration of the branch metric circuit 17 of FIG. 1, which corresponds to the phase uncertainty removing circuit 20, and the EXOR circuits 21 and 22 are L for arbitrarily inverting the sign of the soft decision data. EXOR of bits (L is the quantization number of soft decision data), selectors 23 and 24 are L-bit 2 to 1 sectors for exchanging Pch data and Qch data. The calculation circuits 31 to 38 are circuits that perform branch metric calculation of each codeword and soft decision data when the reproduction carrier has a phase difference of 0 from the reference phase on the transmission side, and are mainly composed of a multiplier and an adder. Corresponding to the metric calculation circuit 11, the selectors 39 to 46 are N-bit 2to selectors (N depends on the precision of the branch metric) for exchanging the branch metrics and removing the phase indetermination. It corresponds to the circuit 12.

When the coding rate is ⅔ and the PQ orthogonal plane is assigned as shown in FIG. 3 to obtain 8PSK, P-corresponding to the codewords 000, 001, 010 ... 111. _Let the coordinates of the transmitted data on the Q orthogonal plane be (P _n ,
Q _n ) [n = 0, 1, 2, ..., 7 with codeword 000,00
1, 010, ..., 111] and the coordinates of the received data are (Rp, Rq), the branch metric when there is no phase indetermination is the inner product of the transmitted data and the received data BMn = Pn -Rp + Qn-Rq [n = 0, 1, 2, ...,
7].

Assuming that the reproduced carrier wave has undergone a phase rotation of 225 ° (at this time, the received data has a phase rotation of −225 °), the received data (soft decision data) is first subjected to Pch by the phase indeterminacy removing circuit 20. The sign of both Qch is inverted, the phase of 180 ° is corrected, and the branch metric calculation circuit 11 calculates the branch metric. Since this result still contains the phase error of 45 °, the true branch metric for the codeword 000 should be given the branch metric of the coordinates (P7, Q7) for the codeword 111, and the phase uncertainty removing circuit 12 Is a branch metric BM7 (3
By selecting 8), the correct branch metric is obtained.

Here, the quantization bit of the soft decision data is L
= 4 bits, the branch metric is N = 7 bits, and the CMO
If the Viterbi decoding circuit is composed of the S gate array, the 1-bit 2to1 selector has about 4 gates, the 1-bit 8to1 selector has about 20 gates, and the EOR has about 3 gates. 20 gates ×
7 bits × 8 = 1120 gates, in the embodiment of the present invention, (3 gates × 4 bits × 2) + (4 gates × 4 bits × 2) + (4 gates × 7 bits × 8) = 280 gates The hardware amount is 1/4 compared to the conventional circuit.
Reduced to.

[0027]

As described above, the present invention provides ((n +
The phase uncertainty of 1) / 2) π (n = 0,1,2,3) is due to bit inversion of received data and Pch before branch metric calculation.
Since the / Qch data is corrected by replacement and the phase uncertainty of 1 / 4π is removed by replacing the branch metric after the branch metric calculation, the amount of hardware is significantly reduced compared to the conventional circuit. At the same time, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a Viterbi decoding circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a branch metric circuit in FIG.

FIG. 3 is a diagram showing symbol points for codewords in 8PSK.

FIG. 4 is a block diagram of an example of a conventional Viterbi decoder.

5 is a block diagram of an example of a branch metric circuit in FIG.

[Explanation of symbols]

 11 Branch metric calculation circuit 12, 20 Phase uncertain removal circuit 13 ACS circuit 14 Path metric memory 15 Path memory 16 Synchronization determination circuit 17 Branch metric circuit 18 Soft decision data 19 Decoded data 31-38 Branch metric calculation circuit 39-46 2to1 selector 47 Soft decision data 48 Selector control signal 21,22 EXOR 23,24 2to1 selector 49-568 8to1 selector

Claims (3)

[Claims] 1. A branch metric circuit for taking a correlation value (branch metric) of a received symbol and a symbol corresponding to a branch derived from each state, and the branch metric and a metric of a surviving path up to the previous time are added. Selector circuit that selects the most probable path that joins the state, metric memory that stores the metric of the surviving path calculated by this selector circuit, path memory that stores the surviving path, and establishment of code synchronization In the Viterbi decoding circuit including a synchronization determination circuit, the branch metric circuit extracts ((n + 1) / 2) π (n) from the received symbol when the lead-in phase of the reproduced carrier does not match the phase of the transmitted carrier.
= 0, 1, 2, 3) first phase uncertainty removing circuit for removing phase uncertainty, and a symbol corresponding to a received symbol output from the first phase uncertainty removing circuit and a branch derived from each state A branch metric calculation circuit for calculating a branch metric of a correlation value with, and a second phase uncertainty removal circuit for removing a phase uncertainty of ¼π by replacing each branch metric after this branch metric calculation. A Viterbi decoding circuit comprising: 2. An exclusive OR circuit of the quantized number bits of which the first phase uncertainty removing circuit arbitrarily inverts the sign of the soft decision input data of 2 channels, and an output of this exclusive OR circuit. 3. The Viterbi decoding circuit according to claim 1, further comprising a selector for switching the two channels. 3. The Viterbi decoding circuit according to claim 1, wherein the second phase uncertainty removing circuit comprises an N-bit selector which replaces the branch metrics from each output of the branch metric calculating circuit and removes the phase uncertainty. .