JPH08288967A - Transmission system, its transmitter-receiver and trellis decoder - Google Patents

Abstract

PURPOSE: To improve the transmission efficiency and to reduce the quantity of hardware by employing a punctured code resulting from thinning part of convolution codes so as to adopt a speed conversion type hardware. CONSTITUTION: A de-punctured circuit 21 processes input demodulation data by a prescribed pattern. The processed data are subject to branch metric calculation in a BMU 22 and Viterbi decoding bits are generated by a Viterbi decoder 23 from the resulting data. Then non-coded its in coded bits y0 , y1 obtained via a convolution coder 24 and a puncture circuit 25 are decoded by a non-coded bit decoder circuit 13. In the case of decoding, the non-coded bits are delayed by a delay means 12 till the bits y0 , y1 are decoded. In order to conduct external error correction, the bit rates are arranged by a speed conversion circuit 3, which provides an output of a trellis decoding symbol.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding and modulation system using a convolutional code, and more specifically, to a transmission system having a high transmission efficiency (frequency utilization efficiency) and a small circuit configuration. The transmission / reception device and the trellis decoder.

[0002]

2. Description of the Related Art A coded modulation system is a system for improving transmission characteristics by arranging coded bits and non-coded bits in a well-balanced manner.

The coded bits are easily coded for error correction (for example, block coding, convolutional coding, etc.) so that an inter-code distance can be easily obtained. Therefore, in the symbols that are relatively close to each other on the modulation constellation, the coded bits of them may be different. On the other hand, for non-coded bits, the effect of coding is not included, so that the distance is determined only on the constellation.

Therefore, the basic signal arrangement in the coded modulation method is to arrange the coded bits so that the same distance (maximum distance) can be obtained for the same symbol (subset symbol). That is, by arranging so as to maximize the distance, it is possible to equivalently increase the intersymbol distance and to realize a transmission method with good transmission characteristics.

The coded modulation method as described above is premised on multi-valued modulation. On the other hand, in order to prevent the transmission band from expanding due to encoding, it becomes necessary to raise the modulation level, and the non-encoded transmission characteristics deteriorate. However, the degree of improvement due to the above-mentioned encoding is sufficient to compensate for the deterioration of the transmission characteristics, and this becomes the encoding gain. Therefore, the coding modulation method can obtain the coding gain relatively easily even when using the multilevel modulation under the band limitation.

Encoding using convolutional coding is generally used as trellis coded modulation (hereinafter simply referred to as TCM).
Sometimes abbreviated. TCM: Trellis-Coded Modula
tion).

The trellis coded modulation method proposed by Ungerboeck (for example, reference [1] G. Ungerboeck, “Channel Co.
ding with Multilevel / Phase Signals ”, IEEE Trans.I
nform.Theory, Vol.IT-28, pp.55-67, Jan.1982.) is a characteristic of how to effectively allocate the coded bits and the non-coded bits to modulation symbols (Fig. 13). See). The basis of this allocation is a technology called "set-partitioning". For example, in TCM, convolutional coding is used for coding, but its configuration is determined so as to maximize the inter-code distance (Euclidean distance) including this allocation, and is also called “Ungerboeck Code”.

On the other hand, AJViterbi has attempted to use a convolutional code, which has been designed to maximize the inter-code distance (Hamming distance) as a binary code and has been put into practical use, up to that point. (Eg, [2] AJViterbi, JKWolf, E.Zehavi, R.Padovani,
“A Pragmatic Approach to Trellis-Coded Modulatio
n ”, IEEE Communications Magazine, Vol.27, pp.11-19,
See Jul.1989.). This is called a "Pragmatic Code" in the sense of a practical code.

The general form of TCM encoding is shown in FIG.
With reference to FIG. 13, it is assumed that the input information symbol m0 bit is expanded to a coded symbol n0 bit and assigned to a modulation symbol. At this time, the overall coding rate R = m0 / n
It becomes 0. Further, convolutional coding with a coding rate r = m / n is used for code expansion (however, the coding rate r of the convolutional coding). Here, the information bits to be encoded are m0 bi
It is mbit of t, and the coded bit is nbit. Therefore, the uncoded bits that are not coded are (m
0-m) = (n0-n) bit. The Viterbi decoding method is used for decoding m bits of the information symbols.

Signal space (signal space) in TCM
The basic rule of (mapping) is to make the Euclidean distance du between modulation symbols having common coded bits but different only non-coded bits as large as possible. A set of modulation symbols having common coded bits is called a subset.

For example, assume that a strong convolutional code is used for encoding and that the decoding error rate of the encoded bits becomes "0" in a range exceeding a certain C / N. Then, since the characteristic of the transmission error is determined only by the Euclidean distance du, the optimal signal arrangement can be obtained. The coded symbols are converted into the arrangement data Ie / Qe corresponding to the respective arrangements on the I / Q axes and modulated by the signal arrangement distributor so as to have this arrangement.

FIG. 14 shows an example of the coding configuration and signal arrangement of the "Pragmatic Code". Although PSK is used as the modulation method in the above-mentioned document [2], FIG.
It is applied to M (hereinafter, this is 16QAM-T
CM or simply 16TCM). This is referred to in [3] GJPottie, DPTaylor, “Multilevel Codes Bas
ed on Partitioning, Appendix I ”, IEEE Trans. on I
nform. Theory, Vol. 35, No. 1, pp. 96-97, Jan. 1989.

First, the convolutional coding has a coding rate r = 1.
The case of using the / 2 is shown. Also, the overall coding rate is R = 3/4, and 3 bit information can be transmitted per modulation symbol. Furthermore, since the number of uncoded bits is 2 bits, each subset is composed of 4 modulation symbols.

In general, there are 2 ⁿ subsets with respect to the number n of coded bits, and the number of modulation symbols constituting each subset is the number of uncoded bits (n0-n).
For 2 ^(n0-n) . Similarly, the symbols are arranged so that the distance between the modulation symbols forming each subset is maximized.
In the case of the signal arrangement shown in FIG. 14, the Euclidean distance du =
It is 2 dc, and the approximate error rate improvement is 6 dB for uncoded 16QAM. Therefore, the coding gain is defined by the degree of improvement from the non-coded 8PSK of 3 bits / symbol, and is about 4 dB.

Next, a decoding method in the case of the above 16TCM will be described.

FIG. 15 shows the structure of the decoder. Arrangement data I corresponding to the arrangement of demodulated received symbols on the I / Q axis
With d / Qd as input, trellis decoded symbols (x3 x2
x1) is output. As shown in FIG. 14, in the determination of the arrangement on each axis, the received symbol is soft-determined, for example, q = 5. On the other hand, in 16QAM hard decision, q = 3 is sufficient, so subtraction 2 bits, I / Q
In total, the soft decision is 4 bits in total.

From the information of this soft decision, signal arrangement decoding means (hereinafter abbreviated as BMU (branch metric unit)) calculates four branch metrics for Viterbi decoding, and using them, the Viterbi decoder outputs information. Get the bit (x1). At this time, the normal Viterbi decoder has B
MUs are included, but are separate here.

The principle of trellis decoding is as follows.

First, as shown in FIG. 16, hard decision is performed for each subset to detect candidates of decoded symbols, that is, representative symbols. That is, since the lower 2 bits of the trellis coded symbol (y3 y2 y1 y0) cannot be determined until Viterbi decoding, (y1 y0)
= (00) to (11) are detected in advance (xxy1y0). Here, x is 0 or 1.

For example, in FIG. 16, the received symbol
On the other hand, for the subset ◯ of (y1 y0) = (00), the symbol of (1100) similarly becomes (010
1), (1010), and (0011) are the representative symbols of each subset. The detection of the representative symbol is the top 2
Only bits are required (lower 2 bits can be determined after Viterbi decoding). Therefore, the number of output bits of the representative symbol is 2
× 4 = 8 bits.

The branch metric required for Viterbi decoding is determined based on the distance (Euclidean distance) between each representative symbol and the received symbol. As shown in FIG. 16, the branch metrics .lamda.0, .lamda.1, .lamda.2, .lamda.3 corresponding to (y1 y0) = (00) to (11) are respectively calculated as Bs bi.
Express with t. For example, Bs = 4 (Japanese Patent Application No. 5-2
According to 75660, Bs = 3). Using these, the errors corresponding to Ns possible transmission sequences (paths), which are determined by the convolutional coding configuration, are accumulated as a path metric, and the path is selected based on this, and Ms
It is stored in the path memory of the column. The most past bit of the most probable path (maximum likelihood path) of the stored Ns paths is output as a Viterbi decoded bit.

In this way, the information bit (x1) is reproduced while being error-corrected, and the coded bit (y1 y0) can be reproduced by convolutional coding. Normally, a value of 4 to 6 times the constraint length is selected as the number of path memory stages Ms, and when the number of states Ns = 64, Ms = 30.
-40. That is, in the Viterbi decoding of this example, 30 to 40 received symbols are used for one (x1) decoding.

Decoded by the circuit shown in FIG. 15 (y1 y0
) Includes the effect of error correction, which is used to decode the uncoded bits (y3 y2) = (x3 x2).
Since each detected representative symbol is delayed by the time required for Viterbi decoding, it is input to the Ms stage shift register. Then, (y3 y2) corresponding to the decoded and reproduced (y1 y0) is selected, and the upper 2 bits of the trellis decoded symbol are determined.

For example, in the example of FIG. 16 described above, the outputs of the Ms stage shift register are (11), (01), (10),
If (y1 y0) = (00) when (00), then (y
3 y2) = (x3 x2) = (11). Therefore, the corresponding modulation symbol in FIG. 16 is (1100). That is, 16QA in the example shown in FIG. 16 (or FIG. 14).
The hard decision of M is (1010), but the lower 2 bits
From the relationship of the reception sequence before and after, about (110
This means that 0) is correct and the error is corrected.

The same applies when the modulation method is 32QAM. Since the number of bits of the coded symbol in FIG. 13 is n0 = 5, the number of bits q of the soft-decision demodulated data Id / Qd on each I / Q axis on the receiving side is, for example, q = 6 (or more improved performance). In order to make it, q = 7). 32
FIG. 17 shows an example of signal arrangement in QAM.

When the number of coded bits in the case shown in FIG. 13 is n = 2 (r = 1/2), the number of non-coded bits is n0-n = 3. Therefore, the number of bits output from the representative symbol detection circuit is (n0-n) * ²ⁿ = 3.
It becomes × 4.

[0027]

However, in the above-mentioned conventional example, when the coding rate is r = m / n, R =
(N0-n + m) / n0, which is often used r =
In the case of (n-1) / n, (n = m + 1), R = (n0-
It was limited to 1) / n0. The frequency utilization efficiency β is determined by the coding rate R and the modulation level 2 ⁿ⁰ , and generally β
= Rn0 [bps / Hz].

Therefore, a proposal to increase the R by further increasing the frequency utilization efficiency has been proposed in Reference [4] H. Tanaka,
TKMatsushima, “An Application of Trellis Coded M
odulation to Digital Microwave Radio and Its Perfo
rmance ”, IEEE Communications Society, ICC '93, Ma
y, 1993. According to the document [4], for example, when the number of encoded bits is n and the number of input bits (input unit) of the convolutional encoder is m, the coding rate of the convolutional encoder is set to r> m / n. R> (n0-n + m) / n
It has been shown that it can be zero.

For example, when n = 2 and m = 1, r = 3/4
> M / n. If n0 = 5, R = 9/10> (n
It is possible to set 0-n + m) / n0 = 4/5. n0
= 5, β = R · n0 = 4/5 × 5 = 4 [bps / H
z] (capable of transmitting 4 bps information per 1 Hz) is r = 3/4, so β = 9/10 × 5 = 4.5
It becomes [bps / Hz], and the frequency utilization efficiency improves by about 11%. That is, more information can be transmitted in a limited frequency band. FIG. 5 shows the configuration of the encoder in this system when m = 1. Information bit to be encoded x1
Needs to have a higher input bit rate than the other information bits x2 to xm0, so that the speed needs to be adjusted by the speed converter (for example, see Japanese Patent Laid-Open No. 6-14075).

By the way, since the circuit configuration of the trellis decoder corresponding to the transmission method for improving the transmission efficiency (frequency utilization efficiency) is not shown, the transmission apparatus can be configured but the reception apparatus cannot be configured. There is a problem that this transmission method cannot be realized.

In view of the above problems, the first object of the present invention is to cope with the method excellent in the transmission efficiency, and particularly to the efficient trellis decoding when the punctured code is used as the convolutional code. To provide a method of constructing a container.

The second object of the present invention is to provide a phase uncertainty (for example, in the case of PAM modulation, two Q's are generated in the demodulated data on the receiving side when the reference symbol for equalization is not separately transmitted.
When AM modulation is used, four phase uncertainties occur in each demodulated data), and a trellis decoder, a transmission method and a transmission / reception device that enable correct decoding are provided.

A third object of the present invention is that in the case of the QAM, there are four phase uncertainties, and it takes time to obtain a correct phase. Therefore, a trellis decoder and a transmission system in which the degree of phase uncertainty is reduced. And to provide a transceiver.

[0034]

In order to solve the above problems, the present invention has the following constitution. That is, according to the first aspect of the present invention, the information symbol consisting of a predetermined number of bits is subjected to rate conversion on the transmitting side and is composed of non-encoded (n0 -2) bits and encoded input 1 bit (n0 -1). ), One bit of the encoded input is convolutionally encoded, and then the convolutionally encoded bits are subjected to thinning processing in accordance with a predetermined puncturing pattern to be two bits of punctured encoding, and the non-encoding is performed. (N0 -2) bits of encoding and 2 bits of the punctured encoding are combined into n0 bits to obtain 2 ⁿ⁰ encoded multi-level modulation, which is demodulated on the receiving side and obtained by soft decision. Based on the demodulated data
A Viterbi decoding unit that outputs a Viterbi decoded bit and a reproduced punctured coded bit, and a non-decoding unit that decodes the non-encoded (n0 -2) bit using the punctured coded bit reproduced by the Viterbi decoding unit. A coded bit decoding unit; and a speed conversion circuit for speed-converting the Viterbi-decoded bits and the decoded uncoded (n0 -2) bits to output a trellis-decoded symbol composed of a predetermined number of bits. A trellis decoder having, wherein the Viterbi decoding unit corresponds to a depuncture circuit that performs depuncture processing on the demodulated data according to the puncture pattern, a branch metric calculation unit that calculates a branch metric, and one bit of the encoded input. A Viterbi decoder that outputs the Viterbi decoded bits, and re-convolutionally encodes the Viterbi decoded bits A convolutional encoder, and a puncture circuit that performs a thinning process according to the puncture pattern and outputs the reproduced punctured coded bits, wherein the non-coded bit decoding unit modulates the demodulated data. A region determining unit that determines which region of the constellation the region belongs to and outputs the region information, and a delay unit that delays the region information until the Viterbi decoding unit outputs the reproduced punctured coded bits, From the delayed region information and the reproduced punctured coded bits, the uncoded (n0 −
2) A non-coded bit decoder for decoding bits, and a trellis decoder.

Further, in the invention described in claim 2, the transmission side performs information rate conversion on an information symbol consisting of a predetermined number of bits and consists of non-encoded (n0 -2) bits and one encoded input bit (n0). -1) As a set of bits, 1 bit of the coded input is convolutionally coded, and then the convolutionally coded bits are decimated according to a predetermined puncture pattern to be 2 bits of punctured code, The non-coded (n0 -2) bits and the punctured coded 2 bits are paired with n0 bits, and the 2 ⁿ⁰ coded multi-level modulation is demodulated on the receiving side to make a soft decision. A Viterbi decoding unit that outputs a Viterbi decoded bit and a reproduced punctured coded bit based on the obtained demodulated data, and the non-coded using the punctured coded bit reproduced by the Viterbi decoding unit. A non-encoding bit decoding unit for decoding (n0 -2) bits of encoding, and a predetermined number of bits by speed-converting the Viterbi decoded bits and the decoded (n0 -2) bits of non-encoding. A trellis decoder having a speed conversion circuit that outputs a trellis decoded symbol, wherein the Viterbi decoding unit performs depuncture processing on the demodulated data according to the puncture pattern, and a branch metric operation that calculates a branch metric. Means, a Viterbi decoder that outputs the Viterbi-decoded bits corresponding to one bit of the encoded input, a convolutional encoder that re-convolutionally encodes the Viterbi-decoded bits, and decimation processing according to the puncture pattern. And a puncture circuit for outputting the reproduced punctured coded bits. The non-coded bit decoding unit includes representative symbol detecting means for detecting upper (n0 -2) bits of representative symbols of the four subsets of the demodulated data defined by coded modulation, and the Viterbi decoding. Delay means for delaying the upper (n0 -2) bits of the four representative symbols until a section outputs the regenerated punctured coded bits, and the delayed 4 according to the regenerated punctured coded bits. One of the upper (n0-2) bits of one representative symbol is selected and decoded to obtain an uncoded (n0-
2) A trellis decoder including: a selector circuit that outputs bits.

The invention according to claim 3 is the trellis decoder according to claim 1 or 2, further comprising an amplitude limiting circuit for limiting the amplitude of the demodulated data.

According to a fourth aspect of the present invention, in the trellis decoder according to any of the first to third aspects, the branch metric calculation means is a Euclidean distance calculation means, a non-linear processing means, and a bit truncation. And means.

The invention according to claim 5 is the trellis decoder according to any one of claims 1 to 4, further comprising error rate detecting means for detecting an error rate from the demodulated data and the Viterbi decoded bits. , And a phase uncertainty removing means for removing the phase uncertainty from the demodulated data.

According to a sixth aspect of the present invention, in the trellis decoder according to the fifth aspect, the error rate detecting means is
The maximum likelihood path metric of the Viterbi decoding is used for detection.

The invention according to claim 7 is the trellis decoder according to claim 5 or 6, wherein the error rate detection means controls the timing of the depuncture.

The invention according to claim 8 is the trellis decoder according to any one of claims 5 to 7, wherein the phase uncertainty removing means is a phase inverting circuit for inverting the phase of the demodulated data. , A data exchange circuit for exchanging demodulated data.

The invention according to claim 9 is the trellis decoder according to any one of claims 5 to 8, wherein the Viterbi decoded bits or the trellis decoded symbols are periodically multiplexed on the transmitting side. The frame synchronization circuit further comprises a frame synchronization circuit for detecting a frame synchronization code and performing a synchronization protection process to establish frame synchronization. The frame synchronization circuit detects a frame synchronization loss and outputs a frame synchronization signal, The phase uncertainty removing means is operated by a synchronization signal.

Further, in the invention described in claim 10, the information symbol consisting of a predetermined number of bits is subjected to rate conversion at the transmitting side and is composed of (n0 -2) bits which are uncoded and 1 bit which is coded input (n0). -1) bit and 1 of the encoded input
After 1 bit obtained by differentially encoding the bits is further convolutionally encoded, the convolutionally encoded bits are subjected to thinning processing in accordance with a predetermined puncture pattern to obtain 2 bits of punctured encoding, and the non-encoding is performed. Of (n0
2) QAM demodulation on the receiving side of 2 ⁿ⁰ value amplitude-phase modulated (QAM) with a 180 ° phase-invariant signal arrangement by combining the bit and the 2 bits of the punctured coding with the n 0 bit. Then, the demodulated data obtained by soft decision is subjected to depuncture processing according to the predetermined puncture pattern, the branch metric is calculated, and the Viterbi decoded bits obtained by Viterbi decoding are differentially decoded, and thinned according to the puncture pattern. The non-coded bits are decoded using the punctured coded bits obtained by performing the processing, and the speed conversion is performed by combining the Viterbi decoded bits and the decoded non-coded (n0 -2) bits. Then, when outputting a trellis-decoded symbol consisting of a predetermined number of bits, 90 ° or 27 based on the detected error rate.
This is a transmission method characterized by performing phase uncertainty removal of 0 °.

In the eleventh aspect of the present invention, an information symbol having a predetermined number of bits is subjected to rate conversion and is composed of non-encoded (n0 -2) bits and one encoded input bit (n0 -1). A speed conversion circuit that outputs a set of bits, a differential encoding circuit that differentially encodes one bit of the encoding input, a convolutional encoding circuit, and a punctured mode by performing thinning processing according to a predetermined puncture pattern. A punctured coding circuit for coding 2 bits, the non-coded (n0 -2) bits and the punctured coding 2
A trellis encoder including a signal constellation distributor for performing a constellation of 180 ° phase invariant by combining bits and n0 bits, and a QA for performing amplitude / phase modulation (QAM) of 2 ⁿ⁰ values.
An M modulator, and a transmitter.

The invention described in claim 12 is the same as claim 11.
A receiving device for receiving, demodulating and decoding a signal transmitted from the transmitting device according to claim 5, wherein the QAM demodulator, the trellis decoder according to any one of claims 5 to 9, and the trellis. A differential decoding circuit that differentially decodes the Viterbi decoded bits obtained from the decoder, and performs phase uncertainty removal of 90 ° or 270 ° based on the detected error rate. It is a receiving device that does.

[0046]

In order to solve the first problem, the trellis decoder according to any one of claims 1 to 4 performs depuncture processing on demodulated data according to a predetermined puncture pattern by a depuncture circuit and thins out the demodulated data. Complement the convolutionally encoded bit position. Then, based on the depunctured demodulated data, a branch metric is calculated and Viterbi-decoded to generate a Viterbi-decoded bit.
The Viterbi-decoded bits are again subjected to convolutional coding and punctured coding to reproduce the punctured coded bits. Then, the non-coded bits are decoded based on the punctured coded bits. In this way, the encoded bits that have been punctured (decimated) according to the puncture pattern are transmitted, and the receiving side performs the decoding following the depuncture processing, so that the coding rate is greater than m0 / n0. The trellis decoder in the above transmission method can be effectively realized.

According to another aspect of the trellis decoder of the present invention, the region determination means determines which region of the modulation constellation the demodulated data belongs to, thereby reducing the number of bits of the representative symbol of the subset that is a candidate for decoding. The number of storage bits in the delay means can be reduced and the circuit scale can be greatly reduced.

In the trellis decoder according to the second aspect, since the representative symbol detecting means detects and outputs only the non-coded bits of each of the decoding candidates, it can be expressed with a smaller number of bits and the reproduced puncture. Since the representative symbol delayed by the Chad coded bit is selected by the selector, the signal arrangement can be changed by changing the representative symbol detection circuit, so that a more flexible configuration can be taken for the signal arrangement.

With respect to the second problem, the trellis decoder according to any one of claims 5 to 9 estimates the error rate by the error rate detection means when the demodulated data has phase indeterminacy. However, by providing the phase uncertainty removing means for converting the phase of the demodulated data when the value exceeds the predetermined value, the phase of the demodulated data can be correctly controlled and the decoding process can be made normal.

With respect to the third problem, claim 10 is
This is a transmission method that reduces the number of phase indeterminations from 4 to 2 when using QAM as the modulation format. Claim 11 is the transmitting device, and claim 12 is the receiving device.

Since the phase invariant mapping of 180 ° is used as the signal arrangement, the phase shift of the demodulated data of 180 ° can be correctly decoded. 90 ° or 270 °
With respect to the phase shift of, the error detection means and the phase uncertainty removal means can correctly decode by performing phase conversion of at least one of 90 ° and 270 °.

[0052]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, trellis coding will be described with reference to FIGS. FIG. 5 shows the case where m0 = 4 and n0 = 5.
The modulation format corresponds to 32QAM. The input information symbols are sequentially input in units of 8 bits, for example. After the speed conversion processing by the speed conversion circuit 101, the convolutional coding circuit 103 performs convolutional coding (rm = 1/2) and the puncture circuit 104 performs puncture processing (rp = m).
trellis coded symbols (y4 y3
y2 y1 y0) is generated, and this 5-bit unit symbol data string is sequentially input to the signal arrangement distributor 105, converted into modulation data Ie and Qe, and input to a 32QAM modulator (not shown).

Here, since the respective bit rates of y4 to y0 are the same rate (Rs0), the relation with each bit rate Rs1 of the convolutionally encoded symbol (c1 c0) is given by the equation (1).

[0055]

[Equation 1] Here, rp = mp / np is the number of bits of the puncture circuit output after the thinning process (puncture process) when the number of input bits per given time of the puncture circuit 104 is mp bits in total of c1 and c0. , Np bits per the predetermined time. The coding rate of convolutional coding, which is a mother code, is rm = 1 /
2, the coding rate of the punctured encoder is r
= Mp / 2np.

Next, with reference to FIG. 6, an example of the puncture process of mp = 4 and np = 3 will be described in more detail. x
1 time series input x1 ⁽⁰⁾ , x1 ⁽¹⁾ , x1 ⁽²⁾ , x1
⁽³⁾ , ..., Convolutional coding sequence (c1 ⁽⁰⁾
c0 ⁽⁰⁾ ), (c1 ⁽¹⁾ c0 ⁽¹⁾ ), (c1 ⁽²⁾ c
0 ⁽²⁾ ), (c1 ⁽³⁾ c0 ⁽³⁾ ), ... Here, (0) to (3) are time indexes indicating the time.
Of these, c0 ⁽¹⁾ and c0 ⁽³⁾ are deleted according to the puncture pattern shown in the following equation (2), so that (y1 y0
) Is (c1 ⁽⁰⁾ c0 ⁽⁰⁾ ), (c0 ⁽²⁾ c1
⁽¹⁾ ), (c1 ⁽³⁾ c1 ⁽²⁾ ), ...

[0057]

[Equation 2] As described above, in the puncture coding of FIG. 6, since 6-bit (y1 y0) is obtained by inputting 4-bit x1, the coding rate of puncture coding is r = 4/6 = 2/3. By the way, of the trellis coded symbols, uncoded y4 y
3 y2 are each equal to x4 x3 x2, and y1 y0
Since it is the same rate as 6bit (y1 y0), (y4
y3 y2) = (x4 x3 x2) is 3 × 3 = 9 bits. That is, x1 is 4 bits, (x4 x3 x2) is 9 bits
With respect to the input of 13 bits in total, a total of 15 bits are output with 6 bits of (y1 y0) and 9 bits of (y4 y3 y2).
Therefore, the coding rate is R = 13/15. Note that x
X1, x3 and x2 are 4 bits while inputting 3 bits each
You need to enter bit. That is, the bit rate of x1 needs to be 4/3 times as high as the bit rate of x4, x3, and x2. Therefore, the speed conversion circuit of FIG. 5 performs speed conversion corresponding to two types of rates.

When the above relations are summarized by the expression, the bit rate Rs2 of x1 is equal to the bit rate of c1 or c0, so that the following expression (3) is obtained.

[0059]

(Equation 3) From the above equation, trellis coded symbols (y4 y3 y2
5 bits of y1 y0) are generated 5 × Rs0 bits per second, while x1 to x4 before encoding are

## EQU4 ## (3.times.Rs0 + 1.times.Rs2) bits = (3.times.Rs0 + mp / np.times.Rs0) bits (4) Output from the speed conversion circuit. Therefore, the bit rate of the input information symbol is (3 × Rs0 + mp / np × Rs
0) [bps]. Therefore, the coding rate R of the trellis encoder of FIG.

(Equation 5) Equation (5) is obtained. For example, r = 2/3 (rp = mp / n
In the case of p = 4/3), R = 13/15.

As described above, when the coding rate of the ordinary trellis coded modulation method uses 32QAM, it is 4 /
However, by adopting the configuration of FIG. 5, the coding rate higher than 5 can be realized. As a generalization, the number of constituent bits of the trellis coded symbol is n.
If 0,

(Equation 6) It becomes formula (6).

The trellis decoder according to the present invention which performs error correction decoding from the demodulated data Id and Qd, which are subjected to QAM demodulation on the receiving side for QAM demodulation of the signal thus code-modulated and transmitted, The structure of one embodiment is shown in FIG.

In the figure, the trellis decoder of the first embodiment comprises an uncoded bit decoding unit 1, a Viterbi decoding unit 2, and
And the speed conversion circuit 3. The non-encoded bit decoding unit 1 includes a region determination unit 11, a delay unit 12, and
It is composed of an uncoded bit decoder circuit 13. The Viterbi decoding unit 2 includes a depuncture circuit 21, a branch metric calculation unit 22 (hereinafter abbreviated as BMU), a Viterbi decoder 23, a convolutional encoding circuit 24, and a puncture circuit 25.

The non-coded bit decoding unit 1 has a configuration in which the non-coded bit candidates are made to correspond to the region on the constellation of the received demodulation symbol by the region judging means 11, and the applicant of the present application has a Japanese Patent Application No. 5-275599. Are described in detail in. In the case of 32QAM, the number of determination areas is 25 in (A) to (Y) in FIG. 17, and thus can be represented by a minimum of 5 bits (As = 5). The area determination result is delayed by the delay means 12 until the coded bit (y1 y0) is reproduced and decoded, and the non-coded bit (y4 y3 y2) = (is used by using the coded bit (y1 y0) which is reproduced and decoded. x4 x3 x2)
Is decoded by the non-coding bit decoder circuit 13.

In the signal arrangement of FIG. 17, when the determined areas are the four corner areas (A), (E), (U), and (Y), they correspond to the reproduced and decoded (y1 y0). There are cases where the symbol to be used does not exist. For example, there is no symbol corresponding to (y1 y0) = (11) in the upper right corner (Y). In this case, the symbol nearby (for example (11
111) is used instead, and (y4 y3 y2) =
(X4 x3 x2) = (111).

Although it becomes a little complicated, more strictly speaking, the area (Y) is divided into two areas (y1) and (y2) for determination, and the received demodulation symbol is in the area (y1). Sometimes I take the (11111) symbol (x4 x3
x2) = (111). When it is in the area of (y2), the symbol of (10011) is taken and (x4 x3 x2
) = (100). In this case, the areas (A), (E), and (U) are similarly divided into (a1) and (a2), (e1) and (e2), and (u1) and (u2). The number of judgment areas is 29. Similarly, the number of bits of the area determination information is 5 (As = 5).

However, when the number of area judgments is 25, as shown in the above-mentioned Japanese Patent Application No. 5-275599, only a part of the upper side of the demodulation symbol (specifically, the upper 4 bits of Id and Qd, respectively) is used. However, if the number of region determinations is 29, it is necessary to use more bits than this, and the size of the region determination means becomes large. Therefore, in view of the circuit scale, if there is a demodulation symbol in the area (Y) as shown above, one of the (11111) symbol or the (10011) symbol is forcibly taken (x4 x3 x2) = (111) or (10
0) is preferable.

Decoding of the Viterbi decoded bit x1 and the reproduced and decoded coded bit (y1 y0) is performed by the Viterbi decoding unit 23 of FIG.

The depuncture circuit 2 will be described with reference to FIGS. 7 and 8.
A depuncture process in No. 1 and a branch metric calculation method in the BMU 22 will be described. Modulation is QPS
In the case of Viterbi decoding in the case of K, the arrangement of the coded bits and the positional relationship of the received demodulation symbols were fixed, but in the case of multi-level QAM, the received demodulation symbols are (A) to (Y).
The positional relationship changes depending on which one of them belongs. Except for this change in the positional relationship, the depuncture process and the branch metric calculation method in this embodiment are the same as in the case of QPSK.

In the example of encoding on the transmission side in FIG. 6, the input is 4bi.
In t periods, the output was 3 symbol periods. In the decoding on the receiving side, conversely, the input demodulated data has a 3-symbol cycle, and the Viterbi decoding has a 4-bit cycle, that is, the branch metric is generated in 4 cycles for 1 cycle.

FIG. 7 and FIG. 8 show specific examples thereof. It is assumed that the received demodulated data from time (0) to (2) is for one cycle. It is assumed that the received demodulated data at time (0) is soft-decided in the area (Q) of FIG. 17 as shown in FIG. In the I-axis direction at this time, the distance from the symbol y0 = '0' is Ri0 ⁽⁰⁾ and the distance from the symbol y0 = '1' is Ri1 for the lower bits of the signal arrangement of the encoded bits (y1 y0).
⁽⁰⁾ More specifically, the symbol of y0 = "0" is "○", and the distance from the symbol of "○" in the I-axis direction is Ri0 ⁽⁰⁾ . The symbol of y0 = '1' is '□', and the distance from '□' in the I-axis direction is Ri1 ⁽⁰⁾ . Similarly, also in the Q-axis direction, y1 = for the upper bits of the signal arrangement of the coded bits (y1 y0).
The distance from the symbol of "0" is Rq0 ⁽⁰⁾ , y1 = "1"
Let Rq1 ^{(0 )} be the distance from symbol 1 of. More specifically, the symbol of y1 = "0" is "○", and the distance from the symbol of "○" in the Q-axis direction is Rq0 ⁽⁰⁾ . The symbol of y1 = '1'is'Δ', and the distance from the symbol of'Δ' in the Q-axis direction is Rq1 ⁽⁰⁾ .

The physical meaning of these distances is that the coded bits (y1 ⁽⁰⁾ y0 ^{(0 )} ) of the transmission side = (c1 ⁽⁰⁾ c
0 ⁽⁰⁾ ) means the judgment index (metric) for each bit. That is, the index with c0 ⁽⁰⁾ = 0 is Ri0 ⁽⁰⁾ , and the index with c0 ⁽⁰⁾ = 1 is Ri1 ⁽⁰⁾ . The index for which c1 ⁽⁰⁾ = 0 is Rq0 ⁽⁰⁾ , and c1 ⁽⁰⁾ =
The index that is 1 is Rq1 ⁽⁰⁾ . The branch metric used for Viterbi decoding is (c1 ⁽⁰⁾ c
0 ⁽⁰⁾ ) = (a b)

## EQU7 ## λab ⁽⁰⁾ = {Rqa ⁽⁰⁾ } ² + {Rib ⁽⁰⁾ } ² (a = 0,1, b = 0,1) (7) Equation (7) is obtained. This branch metric is accumulated for a plurality of symbols to make a path metric, and a correct sequence is selected. In this branch metric, the path metric is the cumulative error of each received demodulated data, and the maximum likelihood path metric = the minimum path metric. On the contrary, if the distances Rqa and Rib are reversed, the maximum likelihood path metric can be the maximum path metric.

Similarly for the reception demodulated data at the times (1) and (2), the indices Ri0 ⁽¹⁾ , Ri1 ⁽¹⁾ ,
Rq0 ⁽¹⁾ , Rq1 ⁽¹⁾ , Ri0 ⁽²⁾ , Ri1 ⁽²⁾ , Rq0 ⁽²⁾ ,
Rq1 ⁽²⁾ can be calculated according to FIG. At this time, depending on the area to which the received demodulated data belongs, "○",
Since the positional relationship of "□", "△", and "◎" changes, the method of taking each index also changes accordingly. From these, branch metrics for times (1) to (3) are generated, but since the information of all coded bits is not sent by the puncturing process on the transmission side, the index for deleted bits is fixed. The value Rf of is inserted and calculated. The value to insert is 0 or 1 / of the maximum value of each index.
2 is often used.

About time (1) (c1 ⁽¹⁾ c0 ⁽¹⁾ )
In the calculation of the index = (ab), c0 ⁽¹⁾ is deleted on the transmitting side, and only y0 ⁽¹⁾ = c1 ⁽¹⁾ is sent, so the index for c0 ⁽¹⁾ is a fixed value Rf. Substitute

## EQU8 ## λab ⁽¹⁾ = {Ria ⁽¹⁾ } ² + Rf, (a = 0,1, b = 0,1) (8) Obtained by the equation (8).

About time (2) (c1 ⁽²⁾ c0 ⁽²⁾ )
The calculation of the index (branch metric) where = (ab) is such that each bit is y1 ⁽¹⁾ = c0 ⁽²⁾ , y0 ^(2).
= C1 ⁽²⁾ is sent over two times, so the time of each index is also used over two times. That is,

## EQU9 ## λab ⁽²⁾ = {Ria ⁽²⁾ } ² + {Rqb ⁽¹⁾ } ² (a = 0,1, b = 0,1) ... (9).

For time (3) (c1 ⁽³⁾ c0 ⁽³⁾ ) =
The branch metric calculation of (ab) is c0
^{Since (3)} has been deleted on the sending side, similarly using Rf,

## EQU10 ## λab ⁽³⁾ = {Rqa ⁽²⁾ } ² + Rf (a = 0,1, b = 0,1) ... (10) Equation (10) is used.

As described above, since the set of branch metrics for four times is generated by using the three received demodulated data, the Viterbi decoded bit x1 can be decoded for four bits in the meantime. 4 bits of this Viterbi decoded bit are convolutionally coded again, and punctured processing is performed to generate 3 sets of coded bits (y1 y0) that are reproduced and decoded, and 3 sets of non-coded bits (x4 x3 x2) are generated. can do.
During this time, x1 is generated in 4 bits, so only x1 has a high rate. In order to output these and perform outside error correction (for example, Reed-Solomon decoding), it is necessary to arrange the bit rates in units of 8 bits. This is also performed by the speed conversion circuit 3 in FIG.

The depuncture processing circuit 21 of FIG. 1 performs the processing of generating the indexes Rib and Rqa for each bit from the demodulated data Id and Qd and inserting Rf. In addition, BMU2 calculates these values and outputs the branch metric.
It is 2.

In this embodiment, the puncture coding rate is r = 2.
/ 3 (overall coding rate R = 13/15), r =
3/4 (R = 9/10) and r = 4/5 (R = 13/2
5) etc. can be easily implemented. C / N (= Es / N0, Es: energy per symbol, N0: noise spectrum density on one side) at each coding rate vs. B
The ER (bit error rate) characteristic is shown by the thick solid line in FIG. This is a BER obtained by performing trellis decoding by actually using an error corresponding to C / N in a computer simulation. For reference, r = 1/2 (R = 4/5) in the conventional method
The characteristics are also shown with a thin solid line. There is a trade-off as the C / N service limit worsens as the coding rate increases (as the transmission rate increases). The normalized Eb / N0 characteristics with the energy (Eb) per bit of information are also shown in FIG.

Next, a second embodiment of the trellis decoder according to the present invention will be described with reference to FIG. In FIG. 2, the trellis decoder of the present embodiment is characterized in that the non-encoded bit decoding unit 4 comprises a representative symbol detection circuit 41, a delay means 42 and an non-encoded bit selector circuit 43. . This structure is described in detail in the description of the conventional example of Japanese Patent Application No. 05-275599. Other components, that is, the Viterbi decoding unit 2 and the speed conversion circuit 3,
This is the same as the first embodiment shown in FIG. Also 16QAM
The case of using is similar to that shown in FIG. 15 and has been described above.

The non-coded bit decoding unit 4 in FIG. 2 leaves the representative symbols of each subset that are candidates for decoding as they are, and the corresponding reproduced and decoded coded bits (y1 y0)
One symbol is selected from the combination of and. Therefore, in the non-encoded bit decoding unit 4, since the signal arrangement is changed only in the representative symbol detection circuit 41, the degree of freedom is higher. On the other hand, FIG. 1 of the first embodiment
In the above configuration, it is necessary to change both the area determination means 11 and the non-coded bit decoder circuit 13.

Reproduction-decoded coded bits (y1 y0)
Requires the Viterbi decoding unit 2 shown in the first embodiment.
The trellis decoder composed of these and the speed conversion circuit 3 is excellent in the coding rate as in the first embodiment.

Next, a third embodiment of the trellis decoder according to the present invention will be described with reference to FIG. The difference from the first embodiment is that an amplitude limiting circuit 5 for limiting the amplitude of demodulated data is provided. In this way, by the amplitude limiting circuit 5, as shown in FIG.
The applicant of the present application has made clear that even if amplitude limitation is applied to the demodulated data within the range shown by the double-dashed line in Fig. 7, the characteristics hardly deteriorate (Japanese Patent Application No. 5-275599 and Japanese Patent Application No. 5-5799). -275560). This amplitude limitation simplifies the area determination unit 11 and the BMU 22 in the subsequent stage.

Further, as the configuration of the BMU 22, not only the Euclidean distance calculating means but also the non-linear processing means and the bit truncation means are provided, so that the B circuit having a smaller circuit scale can be obtained.
MU can be configured (Japanese Patent Application No. 5-275660)
No.).

Although the amplitude limiting circuit 5 is applied to the configuration of the first embodiment in FIG. 3, the same effect can be obtained by applying the amplitude limiting circuit 5 to the second embodiment or the embodiments described below. Obtainable.

Next, a fourth embodiment of the trellis decoder according to the present invention will be described with reference to FIG. In FIG. 4, the trellis decoder according to the present embodiment includes an amplitude limiting circuit 5, a phase uncertainty removing unit 6, an uncoded bit decoding unit 1, a Viterbi decoding unit 2, a speed conversion circuit 3, and an error. Rate detection means 7,
The frame synchronizing circuit 8 is provided to remove the phase uncertainty of the demodulated data and decode the demodulated data with the correct phase. The phase uncertainty removing unit 6 includes a phase inverting unit 61 and a data exchange circuit 66. The phase inversion means 61 is
An inverting circuit 62 for inverting the Id side data of the amplitude-limited demodulated data, a selector 63 for switching between the inverted data and the non-inverted data according to an instruction from the error rate detecting means 7, and a similar Iq side data Inverting circuit 64,
And a selector 65. The data exchange circuit 66 is composed of selectors 67 and 68 which exchange the outputs of the phase inversion circuit with each other according to an instruction from the error rate detection means 7.

When the reference symbol for equalization is not transmitted, when the modulation is QAM, four uncertainties occur in the phase of demodulated data. At this time, the error rate is detected by monitoring the maximum likelihood path metric of Viterbi decoding, or by comparing the hard-decision bit and the coded bit that has been reproduced and decoded, and when the error rate exceeds a preset value. The phase of the demodulated data is judged to be out of phase and the phase of the demodulated data is shifted to detect the correct phase. In FIG. 4, the phase uncertainty removing means 6 comprises a phase inversion circuit 61 and a data exchange circuit 66. These operations and other configuration examples are described in detail in Japanese Patent Application No. 6-227878.

Further, there is a case where the phase uncertainty of 180 ° cannot be eliminated only by monitoring the maximum likelihood path metric of Viterbi decoding. In this case, for example, when the frame synchronization code is multiplexed, the phase ambiguity is removed by monitoring the out-of-frame synchronization.

When the modulation is PAM, only the 180 ° uncertainty removal is necessary, and therefore the phase inversion means alone can be used.

The depuncture timing is unknown on the receiving side unless a signal indicating this (frame synchronization, etc.) is sent specially. This is because when the error rate is larger than a predetermined value, the error rate detection means determines that the depuncture timing is not correct and shifts the timing until the error rate becomes smaller than a predetermined value. By repeating, you can get the correct depuncture timing. The configuration for acquiring the depuncture timing is also effective for the following embodiments.

Next, as a fifth embodiment, an embodiment of a transmission system and a transmission / reception device for reducing the phase uncertainty of demodulated data when the modulation is QAM will be described with reference to FIGS. 11 and 12.

The modulation is 32 QA as in the previous embodiments.
It is M.

In the convolutional coding circuit 103 of the present example shown in FIG. 11, when the input x'1 is inverted, each bit c of the output is
1, c0 and puncture circuit outputs y1, y0 are also inverted. In this case, convolutional coding is performed after x1 is differentially coded by the differential coding circuit 106.

FIG. 12 shows the configuration of a trellis decoder compatible with this differential encoding. The trellis decoder shown in FIG. 12 includes an amplitude limiting circuit 5, a phase uncertainty removing unit 6 ′, an uncoded bit decoding unit 1, a Viterbi decoding unit 2, a speed conversion circuit 3, and an error rate detection unit 7. And a differential decoding circuit 9. The phase uncertainty removing means 6'of this embodiment comprises a phase inverting means 61 on the Id side and a data exchange circuit 66,
There is no phase inversion means on the Iq side.

The operation is similar to the example shown in Japanese Patent Application No. 6-227878, and the Viterbi decoding output x ″ 1 is decoded as the inverted data of x′1 when the demodulated data is shifted by 180 °. Yes (at this time the error rate cannot be detected)
Recovers the correct x1 by differentially decoding x "2.
At this time, (c'1 c'0) is also (c1 c0) on the transmitting side.
), Respectively, and (y'1 y '
0) is also the inverted version of (y1 y0) on the transmitting side. However, the signal arrangement of non-encoded bits is the same as the arrangement of non-inverted (y1 y0) as shown in FIG.
y0) is correctly decoded with the same value regardless of whether it is inverted or non-inverted.

When the demodulated data is deviated by 90 ° or 270 °, the error rate detecting means 7 can determine that the error rate is large. Therefore, it is necessary to shift the demodulated data by 90 ° or 270 °. In the embodiment shown in FIG. 12, only the Id side is inverted and converted, so that it is shifted by 90 °. If 27
Even if it is deviated by 0 °, it can be correctly decoded by the operation of shifting it by 90 °. In this case, as a result of shifting 90 degrees,
This is because the original phase deviates by 180 °, but if it deviates by 180 ° as described above, correct decoding can be performed.

As described above, the number of indeterminate phases can be reduced from 4 to 2. Since the average number of trials of phase determination is halved, the pull-in time at the time of channel switching is shortened.

[0097]

As described above, according to the present invention, a trellis decoder having excellent transmission efficiency (frequency utilization efficiency) can be effectively constructed with a relatively small amount of hardware. There is. Further, there is an effect that it is possible to remove the phase uncertainty that occurs on the receiving side when the reference symbol for equalization is not separately transmitted. Further, when the modulation is QAM, there is an effect that it is possible to provide a transmission system and a transmission / reception device that reduce the number of phase uncertainties and shorten the pull-in time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a trellis decoder according to the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the trellis decoder according to the present invention.

FIG. 3 is a block diagram showing the configuration of a third embodiment of a trellis decoder according to the present invention.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of the trellis decoder according to the present invention.

FIG. 5 is a configuration of a trellis encoder with an increased coding rate (n
FIG. 3 is a block diagram showing 0 = 5 and the number of encoded bits n = 2).

FIG. 6 is a diagram illustrating a configuration example of a rate conversion type 32QAM-TCM trellis encoder.

FIG. 7 is a diagram illustrating a relationship between a coded bit on a transmission side and a demodulation symbol.

FIG. 8 is a diagram illustrating generation of dummy symbols and branch metrics.

9 is a graph showing a bit error rate characteristic (BER) vs. C / N (= Es / N0) computer simulation result of trellis decoding according to the present invention. FIG.

FIG. 10 is a BER in which the bit error rate characteristic of trellis decoding according to the present invention is normalized by the energy per information bit.
It is a graph of the computer simulation result with respect to Eb / N0.

FIG. 11 is a block diagram showing a configuration of an embodiment of a trellis encoder with differential encoding.

FIG. 12 is a block diagram showing a configuration of an embodiment of a trellis decoder with differential decoding.

FIG. 13 is a block diagram showing a basic configuration of a trellis encoder.

FIG. 14 is a block diagram showing a schematic configuration of a 16QAM-TCM encoder.

FIG. 15 is a basic configuration of a trellis decoder (16QAM-T
It is a block diagram showing (for CM).

FIG. 16 is a diagram showing hard decisions and branch metrics in each subset.

FIG. 17 is a diagram showing a signal arrangement in the IQ plane of 32QAM-TCM.

[Explanation of symbols]

1 Uncoded Bit Decoding Unit 2 Viterbi Decoding Unit 3
Speed conversion circuit 11 Region determination means 12 Delay means 13 Uncoded bit decoder circuit 21 Depuncture circuit 22 Branch metric operation means (BMU) 23 Viterbi decoder 24 Convolutional encoder
25 puncture circuit

Claims (12)

[Claims] 1. A set of (n0 -1) bits consisting of uncoded (n0 -2) bits and 1 bit of a coded input by subjecting an information symbol consisting of a predetermined number of bits to rate conversion on the transmission side. , 1 bit of the coded input is convolutionally coded, and then the convolutionally coded bits are decimated according to a predetermined puncturing pattern to be 2 bits of punctured coding, and the uncoded (n0 − 2) Based on the demodulated data obtained by demodulating 2 ⁿ⁰ encoded multi-level modulation of the bit and the 2 bits of the punctured code, which is a set of n 0 bits, on the receiving side and performing soft decision. A Viterbi decoding unit that outputs the Viterbi-decoded bits and the reproduced punctured coded bits, and the non-encoded (n0 -2) bits using the punctured coded bits reproduced by the Viterbi decoding unit. A non-encoding bit decoding unit for encoding, and a speed conversion circuit for converting the speed of the Viterbi decoded bits and the decoded non-encoded (n0 -2) bits to output a trellis decoded symbol having a predetermined number of bits. And a depuncture circuit that performs depuncture processing on the demodulated data according to the puncture pattern, a branch metric operation unit that calculates a branch metric, and a 1-th input of the encoding input. A Viterbi decoder that outputs the Viterbi-decoded bits corresponding to the bits, a convolutional encoder that reconvolutionally encodes the Viterbi-decoded bits, and a reconstructed punctured encoding that performs decimation processing according to the puncture pattern. A puncture circuit for outputting a bit, wherein the uncoded bit The decoding unit determines a region of the constellation of the modulation to which the demodulated data belongs and outputs region information, and the Viterbi decoding unit outputs the reproduced punctured encoded bits until the Viterbi decoding unit outputs the reproduced punctured coded bits. A delay unit for delaying region information; and a non-coded bit decoder for decoding the non-coded (n0 -2) bits from the delayed region information and the reproduced punctured coded bits. Trellis decoder characterized by the following. 2. A set of (n0 -1) bits consisting of an uncoded (n0 -2) bit and one bit of a coded input by rate-converting an information symbol having a predetermined number of bits on the transmitting side. , 1 bit of the coded input is convolutionally coded, and then the convolutionally coded bits are decimated according to a predetermined puncturing pattern to be 2 bits of punctured coding, and the uncoded (n0 − 2) Based on the demodulated data obtained by demodulating 2 ⁿ⁰ encoded multi-level modulation of the bit and the 2 bits of the punctured code, which is a set of n 0 bits, on the receiving side and performing soft decision. A Viterbi decoding unit that outputs the Viterbi-decoded bits and the reproduced punctured coded bits, and the non-encoded (n0 -2) bits using the punctured coded bits reproduced by the Viterbi decoding unit. A non-encoding bit decoding unit for encoding, and a speed conversion circuit for converting the speed of the Viterbi decoded bits and the decoded non-encoded (n0 -2) bits to output a trellis decoded symbol having a predetermined number of bits. And a depuncture circuit that performs depuncture processing on the demodulated data according to the puncture pattern, a branch metric operation unit that calculates a branch metric, and a 1-th input of the encoding input. A Viterbi decoder that outputs the Viterbi-decoded bits corresponding to the bits, a convolutional encoder that reconvolutionally encodes the Viterbi-decoded bits, and a reconstructed punctured encoding that performs decimation processing according to the puncture pattern. A puncture circuit for outputting a bit, wherein the uncoded bit The decoding unit includes representative symbol detecting means for detecting upper (n0 -2) bits of representative symbols of each of the four subsets of the demodulated data defined by coded modulation, and the punctured reproduced by the Viterbi decoding unit. Delay means for delaying the upper (n0 -2) bits of the four representative symbols until the encoded bits are output,
The higher order (n0 -2) of the delayed four representative symbols according to the reproduced punctured coded bits
Uncoded (n
0-2) A selector circuit which outputs as bits, and a trellis decoder. 3. The trellis decoder according to claim 1, further comprising an amplitude limiting circuit that limits the amplitude of the demodulated data. 4. The trellis decoder according to claim 1, wherein the branch metric calculation means includes Euclidean distance calculation means, non-linear processing means, and bit truncation means. . 5. An error rate detecting means for detecting an error rate from the demodulated data and the Viterbi decoded bits, and a phase uncertainty removing means for removing a phase uncertainty from the demodulated data,
The trellis decoder according to any one of claims 1 to 4, further comprising: 6. The trellis decoder according to claim 5, wherein the error rate detection means detects using a maximum likelihood path metric of the Viterbi decoding. 7. The trellis decoder according to claim 5, wherein the error rate detection means controls the timing of the depuncture. 8. The phase ambiguity removing means comprises a phase inverting circuit for inverting the phase of demodulated data and a data exchange circuit for exchanging demodulated data. Trellis decoder according to any one. 9. A frame synchronization circuit for establishing frame synchronization by detecting a frame synchronization code periodically multiplexed on the transmitting side from the Viterbi decoded bit or the trellis decoded symbol and performing synchronization protection processing. 9. The frame synchronization circuit according to claim 5, wherein the frame synchronization circuit detects a frame synchronization loss and outputs a frame synchronization signal, and the phase uncertainty removing means operates according to the frame synchronization signal. Trellis decoder according to any one. 10. The information symbol having a predetermined number of bits is subjected to rate conversion at the transmitting side to obtain (n0-1) bits consisting of non-encoded (n0 -2) bits and 1 bit of encoded input, After 1 bit obtained by differentially encoding 1 bit of the encoded input is further convolutionally encoded, the convolutionally encoded bits are subjected to thinning processing in accordance with a predetermined puncture pattern to obtain 2 bits of punctured encoding. , The non-coded (n0 -2) bits and the punctured coded 2 bits are set as a set of n0 bits, 18
A 2 ⁿ⁰ value amplitude-phase modulated (QAM) signal having a 0 ° phase-invariant signal arrangement is QAM demodulated on the receiving side, and the demodulated data obtained by soft decision is subjected to depuncture processing according to the predetermined puncture pattern. Then, the branch metric is calculated, the Viterbi decoded bits obtained by the Viterbi decoding are differentially decoded, and the non-coded bits are decoded using the punctured coded bits obtained by performing the thinning processing according to the puncture pattern. , The Viterbi-decoded bits and the decoded non-encoded (n0-2) bits are combined to perform speed conversion,
A transmission method characterized in that, when outputting a trellis decoded symbol having a predetermined number of bits, phase uncertainty removal of 90 ° or 270 ° is performed based on the detected error rate. 11. A speed for outputting a set of (n0 -1) bits consisting of uncoded (n0 -2) bits and 1 bit of a coded input by performing speed conversion on an information symbol having a predetermined number of bits. A conversion circuit, a differential encoding circuit that differentially encodes 1 bit of the encoded input, a convolutional encoding circuit, and a thinning process according to a predetermined puncture pattern to obtain 2 bits of punctured encoding. A punctured encoding circuit, and a signal arrangement distributor that performs a 180 ° phase invariant signal arrangement by combining the non-encoded (n0 -2) bits and the punctured encoded 2 bits into n0 bits. And a QAM modulator that performs amplitude-phase modulation (QAM) of 2 ⁿ⁰ values. 12. A receiving device for receiving, demodulating and decoding a signal transmitted from the transmitting device according to claim 11, wherein the receiving device is a QAM demodulator, and any one of claims 5 to 9 is provided. And a differential decoding circuit that differentially decodes the Viterbi-decoded bits obtained from the trellis decoder and outputs them to the speed conversion circuit. 90 ° or based on the detected error rate. A receiver characterized by performing a phase uncertainty removal of 270 °.