JP3926499B2 - Convolutional code soft decision decoding receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilevel modulation transmission system using a convolutional code, and more particularly to a convolutional code soft decision decoding reception apparatus using a soft decision decoding circuit for multilevel modulation convolutional code demodulation.
[0002]
[Prior art]
In a transmission system using a multilevel modulation method using a convolutional code, the occurrence of a code error accompanying transmission is probabilistically unavoidable, but on the other hand, there is a characteristic that a certain degree of code error can be corrected in the decoding process. For this reason, it is usual to provide a decoding circuit having a code correction function on the receiving side.
[0003]
By the way, the decoding circuit having this code correction function searches for an error part of the code on the assumption that an error occurs with an equal probability to all the demodulated codes, and corrects and decodes the code error. A so-called hard-decision decoding circuit and a so-called soft-decision decoding circuit that calculates reliability indicating the probability of the value of a demodulated code (demodulated code) and corrects and decodes the code error using this reliability is there.
[0004]
Here, in general, the latter has a higher error correction capability than the former, and the difference is several dB. In recent years, the latter is more frequently used.
In the description of the soft decision decoding circuit, the term “reliability” and the term representing the reciprocal thereof are used. These terms may be called “weight” and “metric”, respectively. The “soft decision” may also be called “soft decision”, but both are synonyms.
[0005]
As a prior art of this soft decision decoding circuit, for example, in the case of a BPSK receiver, a soft decision Viterbi decoding circuit (QUALCOMM: “Viterbi decoder family” that uses the magnitude of the amplitude of the received signal as reliability. There is a catalog of “ECC devices for satellite communications”.
Here, the BPSK method is a binary phase shift keying method.
[0006]
Further, as a conventional technique of a multi-level modulation type receiver having four or more values, for example, a 16QAM type receiver having a signal point arrangement (hereinafter, the arranged signal points are referred to as modulation signal points) as shown in FIG. Is the square of the Euclidean distance between the received signal point and the modulated signal point representing the position of the received signal in the signal space, as described in Hideki Imai, “Coding Theory” (P288, edited by the Institute of Electronics, Information and Communication Engineers). A soft-decision type Viterbi decoding circuit that uses a metric as a metric is known.
[0007]
The operation of the multi-level modulation transmission apparatus using the conventional soft decision decoding circuit will be described below using a 16QAM transmission apparatus. The 16QAM method is a 16-value quadrature amplitude modulation method.
First, FIG. 18 shows a circuit configuration of a 16QAM transmission device, and FIG. 19 shows a circuit configuration of a 16QAM reception device having a soft decision decoding circuit.
[0008]
In the transmission apparatus of FIG. 18, the information code supplied to this apparatus is first input to a convolutional encoding circuit 1 where it is converted into a 4-bit set of convolutional codes and output.
[0009]
As the convolutional coding circuit 1, the circuit described in FIG. 11.4 on page 252 of the general textbook, for example, “Coding theory” described above, has been expanded to a coding rate of 4/3. Circuit, or
John G. Proakis, “Digital Communications (Third Edition)”
MacGrawHill, P477 Fig.8-2-10
The circuit described in the above may be used.
[0010]
A set of 4-bit convolutional codes output from the convolutional encoding circuit 1 is input to the 16QAM modulation circuit 2 as a modulation code. Here, as described in a general textbook, first, as shown in FIG. A modulation signal point corresponding to a set of modulation bits of 4 bits is selected from 16 modulation signal points on the signal space, and then an I component value Itxda and a Q component value of the selected modulation signal point are selected. Qtxda is modulated by the 16QAM modulation method, and baseband modulation signals Itxda and Qtxda are output.
[0011]
Next, the modulation signals Itxda and Qtxda output from the 16QAM modulation circuit 2 are input to the DA conversion circuits 3i and 3q, where they are converted into analog signals Ia and Qa, and then input to the mixer 4, After being converted into a quadrature-modulated IF signal having an intermediate frequency fm by the calculation of the equation (1), the signal is supplied to the up-converter 5 where it is converted into an RF signal composed of a carrier having a higher predetermined frequency. 6 is transmitted.
Ia × cos (2π × fm × t) + Qa × sin (2π × fm × t) (1)
[0012]
Next, in the receiving apparatus of FIG. 19, first, the RF signal received by the receiving antenna 7 is converted into an IF signal of an intermediate frequency by the down converter 8 and input to the mixer 9. The mixer 9 performs quadrature demodulation on the baseband I component signal Iarx and the Q component signal Qarx using the orthogonality of the trigonometric function.
[0013]
The signals Iarx and Qarx output from the mixer 9 are converted into baseband digital received signals Ida and Qda by AD conversion circuits 10i and 10q, respectively, and input to a soft decision Viterbi decoding circuit 11 compatible with the 16QAM system.
[0014]
Here, the synchronous reproduction circuit 12 is a circuit that reproduces the modulation signal point position in the signal space from the received signal and generates a control signal for controlling the clock timing of the receiving apparatus. The operation procedure of the synchronous reproduction circuit 12 is well known and is not directly related to the understanding of the present invention.
[0015]
By the way, in the baseband received signal input to the soft decision Viterbi decoding circuit 11 compatible with the 16QAM system, the position (Ida, Qda) of the signal point (received signal point) is noise or waveform distortion mixed in the transmission system. As shown in FIG. 20, there may be a deviation from the correct modulation signal point position P.
[0016]
Therefore, the soft-decision Viterbi decoding circuit 11 compatible with the 16QAM system is used in the hard-decision Viterbi decoding circuit as described in general textbooks such as Hideki Imai “Code Theory”, Chapter 12 of the Institute of Electronics, Information and Communication Engineers. Instead of the Hamming distance, the square of the Euclidean distance between the reception signal point and the modulation signal point is used as a metric, and the path metric of each trellis is calculated.
[0017]
Here, the calculated path metric means that the smaller the value is, the higher the reliability is because each received signal point is near the modulation signal point.
Therefore, the 16QAM-compliant soft decision Viterbi decoding circuit 11 outputs the code of the path having the smallest path metric value as a decoded information code after correcting the code error.
[0018]
Thus, according to the prior art, even in a 16QAM receiver, which is a kind of receiver for multi-level modulation of four or more values, a soft-decision with higher error correction capability of codes than hard-decision convolutional code decoding. A receiving apparatus using convolutional code decoding can be configured.
[0019]
[Problems to be solved by the invention]
In the above prior art, it cannot be said that consideration has been given to further multi-leveling of a multi-level modulation soft decision decoding circuit for convolutional code demodulation, and there has been a problem of a significant increase in product price due to multi-leveling.
[0020]
That is, for practical use of such a circuit, the LSI is almost necessary, but here, the LSI for soft decision Viterbi decoding compatible with the BPSK system is already on the market and is available at a relatively low cost. Is possible.
[0021]
On the other hand, LSIs for soft decision Viterbi decoding that are compatible with multi-level modulation schemes with four or more levels are not yet commercially available. Therefore, at present, soft decision Viterbi decoding with multi-level modulation schemes with four or more levels is not available. In application, it is necessary to design and manufacture a new LSI.
[0022]
However, since the development of LSI requires a large cost, the product price increases remarkably compared with the improvement in transmission performance by multi-valued production in a product produced in a small quantity, which causes the above-mentioned problems.
[0023]
Further, in a normal radio apparatus mainly using hard decision, an interleaving process for changing the order of convolutionally encoded code sequences in bit units is added in order to reduce the influence of burst errors.
[0024]
On the other hand, in the case of a conventional soft-decision Viterbi decoding method corresponding to a multilevel modulation method of four or more values, in order to correct and decode a code error using the square of the Euclidean distance on the signal space as a metric, For example, if the order of the bits of a set of 4 bits representing one signal point in the 16QAM system is varied, the Euclidean distance cannot be defined and the code error cannot be corrected.
[0025]
Therefore, in a multi-level modulation transmission apparatus using interleave processing that replaces the order of code strings in bit units, the conventional soft-decision Viterbi decoding method corresponding to the multi-level modulation system cannot be used as it is. For this reason, the above-mentioned problem occurs.
[0026]
The object of the present invention is to make it possible to easily obtain a large improvement in transmission performance by further multi-leveling, without requiring development of a new LSI, even in a 4-level or higher level multi-level modulation receiver. It is an object of the present invention to provide an inexpensive receiving apparatus that enables soft-decision Viterbi decoding.
[0027]
Another object of the present invention is to provide a receiver capable of soft-decision Viterbi decoding even in a four-value or higher-value multi-level modulation transmission apparatus using interleave processing for changing the order of code strings in bit units. Is to provide.
[0028]
[Means for Solving the Problems]
The above object is to input a baseband received signal that has been subjected to multilevel modulation, and set it on a complex plane that is a signal space in order to transmit a set of n-bit codes on the transmitting side. ⁿ The modulation signal point closest to the signal point (reception signal point) represented by the value of the received signal is selected from the signal points (modulation signal points), and n bits are allocated to the selected modulation signal point In a receiving apparatus including a multilevel modulation signal demodulating circuit that calculates a set of codes and outputs them as demodulated codes,
The baseband received signal and a set of n-bit demodulated codes output from the multilevel modulated signal demodulation circuit are input, and a modulation signal point (demodulated signal point) corresponding to the n-bit set of demodulated codes Thus, the amount of deviation of the received signal point with respect to the at least one bit of the n-bit set of demodulated codes is calculated, so that the larger the calculated amount of deviation, the more likely the value of the bit is. Is assigned a reliability Gbit = G1 representing a low value, and a reliability Gbit = G2 representing that the smaller the deviation amount is, the higher the probability of the value of the one bit is. The remaining bits of the demodulated code are assigned a reliability Gbit ≧ G2 indicating that the probability of the value of the bit is equal to the reliability of the reliability G2 or higher than the reliability of the reliability G2. Degree of reliability On calculating the bit, it provided the soft decision reliability calculator circuit that outputs the reliability Gbit as the demodulated bit reliability signal,
The multi-level modulation signal demodulating circuit is configured by a soft decision convolutional code decoding circuit compatible with the BPSK modulation method, which performs soft decision based on the demodulated bit reliability signal output from the soft decision reliability calculation circuit. Is achieved in this way.
[0029]
Similarly, the object is to input a set of n-bit demodulated codes and the baseband received signal, calculate a shift amount of the received signal point with respect to the demodulated signal point, and output a shift amount signal as a shift amount signal; ,
When the deviation amount signal is input, and the magnitude of the deviation amount represented by the deviation amount signal is 0, the reliability Gd = Gdmax indicating that the probability of the demodulation signal point is the highest is calculated, and the deviation amount is calculated. When the magnitude of the quantity is greater than 0, the reliability Gd <Gdmax, which indicates that the probability of the demodulation signal point is lower as the magnitude of the deviation is larger, is calculated, and the calculated reliability Gd is A demodulation signal point reliability calculation circuit that outputs a demodulation signal point reliability signal representing the certainty of the selected demodulation signal point;
The n-bit set of demodulated codes and the deviation amount signal are input, and a second adjacent signal point that is a modulation signal point closest to the reception signal point after the demodulation signal point is calculated, and the calculated second The bit values of the same digit in the n-bit set of codes assigned to the adjacent signal points and the demodulated code of the n-bit set of codes are compared with each other. A value representing a group is output as a low-reliability bit position signal, and a value representing that the bit is a notA group is output as a low-reliability bit position signal to bits having the same value. A low-reliability bit position calculation circuit;
The low-reliability bit position signal and the demodulated signal point reliability signal are input, and the bit of the digit indicating that the low-reliability bit position signal belongs to the group A in the n-bit set of demodulated codes, A reliability Gbit ≦ Gd that is equal to the reliability Gd represented by the demodulated signal point reliability signal or smaller than the reliability Gd by a predetermined amount is calculated and assigned, and the low reliability bit position signal is not group A The bit G of the digit indicating that it belongs to is calculated by assigning the reliability Gdmax representing the highest probability or a reliability Gbit ≦ Gdmax (Gd ≦ Gbit) which is smaller by a certain amount determined by the magnitude of the reliability Gd. A demodulating bit reliability calculation circuit that outputs a reliability Gbit representing the probability of each digit bit and outputs it as a demodulating bit reliability signal;
Achieved even if the soft decision reliability calculation circuit is configured by the deviation amount calculation circuit, the demodulated signal point reliability calculation circuit, the low reliability bit position calculation circuit, and the demodulation bit reliability calculation circuit. Is done.
[0030]
Further, the object is to input a set of n-bit demodulated codes and the received signal of the baseband, and to provide a first component of a deviation amount of the received signal point with respect to the demodulated signal point, a deviation amount ΔI in the I axis direction. And the second component Q-axis deviation ΔQ, or the first component radial deviation ΔR and the second component angular deviation Δθ are calculated and shifted. A deviation amount calculation circuit that outputs as a quantity signal;
When the shift amount signal is input and the shift amount of the first component or the shift amount of the second component represented by the shift amount signal is 0, the first component or the first component of the demodulated signal point The first component reliability G1d = Gdmax or the second component reliability G2d = Gdmax, which indicates that the probability of the two components is the highest, is calculated. When it is larger, the reliability of the first component G1d <Gdmax, which represents that the probability of the component of the demodulated signal point is lower as the deviation amount of the component is larger, or the reliability of the second component A demodulation signal point reliability calculation circuit that calculates G2d <Gdmax and outputs these reliability values G1d and G2d as a demodulation signal point reliability signal indicating the probability of the selected demodulation signal point;
The n-bit set of demodulated code and the shift amount signal are input, and the adjacent modulation signal point of the first component in the direction of the polarity code of the shift amount of the first component with respect to the demodulated signal point is calculated. In addition, the value of the bit of the same digit of the n-bit 1-set code assigned to the calculated adjacent modulation signal point of the first component and the n-bit 1-set code of the demodulated code is compared, and the value is For bits of different digits, a value indicating that the bits are of group A is output as a low-reliability bit position signal of the first component, and for bits of digits having the same value, the bit is A value representing the notA group is output as a low-reliability bit position signal of the first component, and the second component in the direction of the polarity code of the shift amount of the second component with respect to the demodulated signal point The adjacent modulation signal point of the component is calculated and the calculated second component The bit values of the same digit of the n-bit 1-set code assigned to the adjacent modulation signal points and the n-bit 1-set code of the demodulated code are compared. A value indicating that the bit is in the group A is output as a low-reliability bit position signal of the second component, and the bit having the same value indicates that the bit is in the notA group. The value is output as a low reliability bit position signal of the second component, and the low reliability bit position signal of the first component and the low reliability bit position signal of the second component are used as the low reliability bit position signal. A low-reliability bit position calculation circuit for output;
The low-reliability bit position signal and the demodulated signal point reliability signal are input, and in the n bits of one set of demodulated codes, the low-reliability bit position signal is converted to a digit bit indicating that it belongs to the A group. Is either the reliability G1d or G2d represented by the demodulated signal point reliability signal of the same component, or any one of the reliability Gbit ≦ G1d or Gbit ≦ G2d smaller than the reliability G1d or G2d by a predetermined amount. And the bit of the digit indicating that the low reliability bit position signal belongs to the notA group is determined by the reliability Gdmax indicating the highest probability, or the reliability G1d or G2d. Any one of a small degree of reliability Gbit ≦ Gdmax (G1d ≦ Gbit or G2d ≦ Gbit) is assigned, and each is represented as a reliability Gbit representing the probability of each digit bit. And a demodulation bit confidence calculation circuit for outputting a reliability signal provided,
Achieved even if the soft decision reliability calculation circuit is configured by the deviation amount calculation circuit, the demodulated signal point reliability calculation circuit, the low reliability bit position calculation circuit, and the demodulation bit reliability calculation circuit. Is done.
[0031]
As a result, a receiving apparatus is already commercially available as an LSI by multi-value modulation soft decision decoding that can decode a good information code with high code error correction capability, and is easily available and inexpensive, a soft decision Viterbi decoding circuit compatible with the BPSK method Can be configured using
[0032]
In addition, since the code error is corrected based on the reliability assigned to each bit of the demodulated code, even in a multi-level modulation transmission device that performs interleaving processing that changes the order of the code string in bit units, the code error correction capability is high. A multi-value modulation type soft decision decoding receiving apparatus capable of demodulating a good information code can be configured.
[0033]
Further, according to the present invention, the demodulated signal point and the second adjacent signal point that is most likely to be erroneous are calculated and compared, and the value of the bit in the same digit of the code assigned to the second adjacent signal point and the demodulated code is different. Is set to a low value only for the bits of the digits that are likely to be erroneous, and the reliability of the bits of the digits whose values do not change is maintained high.
[0034]
Therefore, compared with the method in which the reliability value of the demodulated signal point is uniformly assigned to all bits of the set of demodulated codes of n bits based on the first means, the code error correction capability of the soft decision convolutional code decoding Can be improved, and good code error correction can be performed.
[0035]
Furthermore, according to the present invention, the two components of the deviation amount, namely, the first component deviation amount ΔI in the I-axis direction and the second component deviation amount ΔQ in the Q-axis direction or the first component are used. A certain amount of deviation ΔR in the radial direction and an angular deviation amount Δθ, which is the second component, are calculated, the bit of the most error-prone digit is calculated for each component, and the reliability of the bit of the most error-prone digit is calculated. Only the low value is maintained, and the reliability of the bit of the digit whose value does not change is kept high.
[0036]
Therefore, as a code to be assigned to the modulation signal point, for example, as shown in FIG. 17, a multi-value using a special code assignment method in which the code of the modulation signal point adjacent in the direction of each component changes only by 1-bit code. In the transmission apparatus of the modulation method, even when the reception signal point is greatly shifted in the oblique direction and the demodulation signal point is likely to be mistaken for the modulation signal point adjacent in the oblique direction, it is possible to accurately calculate the bit of the error-prone digit, Only the reliability of the bit of the digit that is most likely to be erroneous can be set to a low value, and the reliability of the bit of the digit whose value does not change can be kept high.
[0037]
Therefore, even when the received signal point is greatly deviated in the oblique direction, the reliability of the bit of the digit that is likely to be erroneous in the code can be accurately lowered, so that the code error correction capability of the soft decision convolutional code decoding is further improved and further improved. Code error correction can be obtained.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a convolutional code soft decision decoding receiver according to the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 shows a receiving apparatus according to a first embodiment of the present invention, which is an embodiment in which the present invention is implemented using a 16QAM demodulating circuit 16 as a multi-level modulation signal demodulating circuit. The number of bits n of the demodulated code is 4.
And this embodiment is used in combination with the transmission apparatus shown in FIG. 2, for example.
[0039]
In FIG. 1, the receiving antenna 7, the down converter 8, the mixer 9, the AD conversion circuits 10i and 10q, and the synchronous reproduction circuit 12 are the same as the prior art circuit described in FIG.
[0040]
First, the transmission device of FIG. 2 will be described. The information code supplied to this device is first input to the convolutional coding circuit 13, where convolution is performed by the method described in the above general textbook. Converted to a sign.
[0041]
As the convolutional encoding circuit 13, the same circuit as the convolutional encoding circuit 1 compatible with the multi-level modulation method described as the prior art in FIG. 18 may be used. For example, the above-mentioned QUALCOMM catalog: “Viterbi The circuit described in “Decoder Family Satellite Communication ECC Device” may be used.
[0042]
The convolutional code output from the convolutional encoding circuit 13 is input to the interleaving circuit 14, and as described above, the order of the code strings is changed bit by bit in order to reduce the influence of the burst error. After being input to the S / P conversion circuit 15 and separated into a set of 4 bits of modulation code, it is converted into 16QAM modulation signals Itxda and Qtxda by the 16QAM modulation circuit 2 having the same configuration as the prior art of FIG. Is output.
[0043]
The 16QAM modulation circuit 2 and subsequent circuits are the same as the prior art of FIG. 18, and the baseband modulation signals Itxda and Qtxda output from the 16QAM modulation circuit 2 are connected to the DA conversion circuits 3i and 3q, the mixer 4 and the upconverter 5, respectively. Then, it is transmitted from the antenna 6 after being converted into an RF signal.
[0044]
Next, the receiving apparatus in FIG. 1 will be described.
The RF signal received by the receiving antenna 7 is input to the AD conversion circuits 10i and 10q via the down converter 8 and the mixer 9, and is converted into digital baseband received signals Ida and Qda.
Therefore, the configuration so far is the same as the receiving apparatus in the prior art of FIG. 19, but the configuration after this is greatly different.
[0045]
First, the received signals Ida and Qda output from the AD conversion circuits 10i and 10q are branched into two systems, one is input to the 16QAM demodulation circuit 16, and the other is input to the soft decision reliability calculation circuit 17.
[0046]
First, in the 16QAM demodulation circuit 16, a modulation signal point S (demodulation signal point) closest to the reception signal point (Ida, Qda) is selected from the 16 modulation signal points shown in FIG. 20, and the selected demodulation signal is selected. A set of 4 bits of codes [1111] assigned to the points is output as a demodulated code.
Here, the binary value is expressed by enclosing it in parentheses [].
[0047]
Therefore, in addition to the other branched received signals Ida and Qda, the soft decision reliability calculation circuit 17 is also supplied with a set of 4 bits demodulated by the 16QAM demodulation circuit 16, and thereby the BPSK. The reliability for use in the convolutional code soft decision decoding circuit 29 corresponding to the system is calculated.
Here, the BPSK-compatible convolutional code soft decision decoding circuit 29 corresponds to a soft decision Viterbi decoding circuit, as will be described later.
[0048]
FIG. 3 shows the circuit configuration of the soft decision reliability calculation circuit 17. In this figure, first, the shift amount calculation circuit 19 calculates the shift amount between the demodulated signal point and the received signal point represented by the demodulated code. Next, the demodulated signal point reliability calculation circuit 20 surrounded by a broken line functions to calculate the reliability of the demodulated signal point selected by the 16QAM demodulator circuit 16, and further includes a demodulated bit. The reliability calculation circuit 21 functions to calculate the reliability of the bits of each digit of the set of 4-bit demodulated codes demodulated by the 16QAM demodulation circuit 16.
[0049]
The 4-bit set of demodulated codes input to the soft decision reliability calculation circuit 17 and the baseband received signals Ida and Qda are first input to the shift amount calculation circuit 19, and these 4-bit set of demodulated codes. And the baseband received signal, the shift amount of the position of the received signal point with respect to the position of the demodulated signal point represented by the demodulated code is calculated, and the shift amount signals ΔI and ΔQ are output.
[0050]
FIG. 4 shows an example of the circuit configuration of the deviation amount calculation circuit 19. A set of 4-bit demodulated codes input here is input to a 16QAM modulation circuit 22, and the demodulated signal is modulated by 16QAM modulation. The coordinate values (Ida ′, Qda ′) of the points are calculated and output.
Here, the values (Ida, Qda) of the received baseband signals simultaneously input represent the coordinate values of the received signal points.
[0051]
Therefore, the subtraction circuits 23i and 23q perform the following operation, that is,
ΔI = Ida−Ida ′
ΔQ = Qda-Qda '
By executing this calculation, the deviation amount of the received signal point from the demodulated signal point is calculated, and the values ΔI and ΔQ obtained by the calculation are output as deviation amount signals.
[0052]
Thus, the deviation amount signals ΔI and ΔQ output from the deviation amount calculation circuit 19 are input to the absolute value calculation circuit 24 in the demodulated signal point reliability calculation circuit 20, and the next calculation, that is,
| Z | = [ΔI ² + ΔQ ² ] ^1/2 /(0.5×dP)
The absolute value | Z | of the standardized Euclidean distance is calculated and output by the above calculation.
Here, dP is the distance between the modulation signal points as shown in FIG.
[0053]
However, in practice, any value that increases or decreases together with the absolute value | Z | described above may be used. Instead of the calculation of the numerator in the above formula, for example, the sum of the absolute value of ΔI and the absolute value of ΔQ is used as the numerator calculation Alternatively, the square of the Euclidean distance may be used as a numerator operation.
[0054]
Thus, the absolute value | Z | calculated by the absolute value calculation circuit 24 represents the distance from the modulation signal point to the reception signal point. Therefore, the smaller this value, the more the demodulated signal point selected by the 16QAM demodulation circuit 16. Indicates that it becomes more likely.
[0055]
As a result, the increasing / decreasing direction of the absolute value | Z | is opposite to the direction of increasing or decreasing the reliability.
Therefore, the absolute value | Z | calculated by the absolute value calculation circuit 24 is further input to the subtraction circuit 25 and converted into a value (1− | Z |) obtained by subtracting the absolute value | Z | This is output.
[0056]
As a result, the value (1- | Z |) output from the subtraction circuit 25 becomes larger as the received signal point is closer to the demodulated signal point and the probability of the selected demodulated signal point is greater. The value can be changed in accordance with the direction of high or low reliability.
[0057]
The rounding circuit 26 rounds the value 1- | Z | calculated by the subtracting circuit 25 to the number of bits with the required accuracy as the reliability, and outputs it as the reliability of the demodulated signal point. The sign of the upper 2 bits of the value 1- | Z | that it has is rounded by being extracted and output as a reliability with a predetermined accuracy.
[0058]
Alternatively, a 2-bit code [11] is assigned to the highest value of 1- | Z |, and smaller values [10], [01], [00] are assigned sequentially as the value of 1- | Z | The reliability of the necessary 2-bit value may be calculated and output as the reliability of the demodulated signal point.
Here, as described above, the binary value is expressed by enclosing it in parentheses [].
[0059]
The reliability output from the rounding circuit 26 is input to the demodulated bit reliability calculation circuit 21, and the reliability of each digit of the 4-bit set of demodulated codes demodulated by the 16QAM demodulation circuit 16 is calculated.
Specifically:
[0060]
That is, since the demodulation code is considered to have the same reliability as the demodulation signal point reliability, the same reliability, that is, the reliability of the demodulation signal point is given to all bits of the 4-bit set of demodulation codes. It is assigned and output as a demodulated bit reliability signal.
As a result, the soft decision reliability calculation circuit 17 outputs a 2-bit demodulated bit reliability signal.
[0061]
Returning to FIG. 1, the demodulated code output from the 16QAM demodulator circuit 16 is also input to the P / S converter circuit 27, where it is returned to a continuous code bit string.
Then, one bit of the continuous code bit sequence and a set of 2-bit demodulated bit reliability signals output from the soft decision reliability calculation circuit 17 as codes representing the reliability of the values of the bits are obtained. Are combined into a set of 3 bits and input to the deinterleave circuit 28.
[0062]
Then, the inverse interleave circuit 28 returns the code sequence to the same order as the original convolutional code in the reverse procedure of the interleave circuit 14 in the transmission apparatus of FIG. This is input to a soft decision convolutional code decoding circuit 29 comprising a decision Viterbi decoding circuit.
[0063]
Therefore, the soft decision convolutional code decoding circuit 29 corrects the code error of the demodulated code using the reliability input together with the code of each bit of the demodulated code, and outputs the corrected and decoded code as the information code.
[0064]
Therefore, according to this embodiment, by using the soft decision reliability calculation circuit 17, a BPSK modulation compatible soft decision Viterbi decoding circuit made of a commercially available LSI can be easily used for four or more values. A 16QAM modulation type receiver, which is a kind of multi-value modulation type receiver, can be configured.
[0065]
As a result, it is possible to easily provide a low-cost convolutional code decoding type receiver having a higher code error correction capability than a receiver using a hard-decision type Viterbi decoding circuit at low cost.
[0066]
In the receiving apparatus according to this embodiment, since the reliability is calculated and assigned to each bit of the demodulated demodulated code, one set of 3 bits composed of 1 bit of the demodulated code and 2 bits of reliability. The soft decision convolutional code decoding circuit 29 can correct the code error of the demodulated code accurately even if the code is replaced in an arbitrary order.
[0067]
Therefore, according to this embodiment, unlike the prior art described with reference to FIG. 19, for example, a four-value or more multi-level modulation scheme to which an interleave process for changing the order of convolutionally encoded code sequences in bit units is added. Even in the receiving apparatus, convolutional code decoding by the soft decision method can be easily realized.
[0068]
Next, a second embodiment of the present invention will be described.
In the second embodiment, the reliability of each bit of the demodulated code can be calculated with higher accuracy than in the first embodiment, and the circuit configuration seen in the block of the entire receiving apparatus is as follows. 1 is the same as the first embodiment shown in FIG. 1 except for the circuit configuration and operation of the soft decision reliability calculation circuit 17.
[0069]
FIG. 5 shows a soft decision reliability calculation circuit 17 ′ according to the second embodiment. In order to distinguish it from the soft decision reliability calculation circuit 17 according to the first embodiment shown in FIG. 17 'is attached.
First, the shift amount calculation circuit 19 is a circuit that calculates the shift amount of the received signal point with respect to the demodulated signal point represented by the demodulated code, and has the same configuration as the shift amount calculation circuit 19 shown in FIG. .
[0070]
Next, the demodulated signal point reliability calculation circuit 32 is a circuit that calculates the reliability of the demodulated signal point based on the magnitude of the shift amount calculated by the shift amount calculation circuit 19.
The low-reliability bit position calculation circuit 33 is a circuit that calculates the bit position of the digit that is most likely to be erroneous when an error occurs in the demodulated code.
[0071]
Then, the demodulated bit reliability calculation circuit 34 includes the reliability of the demodulated signal point calculated by the demodulated signal point reliability calculation circuit 32, the bit position data of the error-prone digits calculated by the low reliability bit position calculation circuit 33, and This is a circuit for calculating the reliability of each bit of the demodulated code.
[0072]
Next, the operation will be described. The 4-bit set of demodulated codes and the baseband received signals Ida and Qda supplied to the soft decision reliability calculation circuit 17 ′ are first input to the deviation amount calculation circuit 19. The
In the shift amount calculation circuit 19, the position of the received signal point with respect to the position of the demodulated signal point represented by the demodulated code from the input 4-bit demodulated code and the baseband received signal, as in the first embodiment. Deviation amounts ΔI and ΔQ are calculated and supplied to the demodulation signal point reliability calculation circuit 32 and the low reliability bit position calculation circuit 33 in common as deviation amount signals.
[0073]
First, the demodulation signal point reliability calculation circuit 32 will be described.
The demodulated signal point reliability calculation circuit 32 calculates the reliability of the demodulated signal point from the magnitudes of the input deviation amount signals ΔI and ΔQ, and outputs a demodulated signal point reliability signal representing the probability of the demodulated signal point. Is done.
[0074]
FIG. 6 shows an example of the circuit configuration of the demodulated signal point reliability calculation circuit 32. The shift amount signals ΔI and ΔQ supplied to this circuit are first input to the absolute value calculation circuits 37i and 37q, where the shift signal Absolute values | ΔI | and | ΔQ | of the quantities are calculated.
Next, the absolute values | ΔI | and | ΔQ | of these deviation amounts are input to the MAX circuit 38, where the maximum values | ΔPmax | = max (| ΔI |, | ΔQ |) are calculated.
At this time, max () means taking the maximum value among the values in parentheses.
[0075]
The calculated maximum value | ΔPmax | is input to the normalization calculation circuit 39, and the next calculation, that is,
Garx = 1− | ΔPmax | / (0.5 × dP)
To implement.
In the above equation, dP is the distance between the modulation signal points shown in FIG.
Here, when | ΔPmax | = | ΔIda |, the value Garx calculated by the above equation represents the distance from the middle line N between the modulation signal points in FIG. 20 to the reception signal point.
[0076]
When the reception signal point is close to the modulation signal point and the probability of the demodulated code is high, the value Garx is 1, and the reception signal point is close to the middle line N between the modulation signal points. When there is a high possibility that the demodulation code is incorrect, the value Garx becomes zero.
[0077]
By the way, this calculation is performed with, for example, 10 significant digits, and the resolution is too high.
Therefore, the calculated 10-bit value Garx is input to the rounding circuit 41 and is rounded to, for example, a 2-bit value in the same manner as the value (1- | Z |) in the first embodiment shown in FIG. , Output as the reliability Gd of the demodulated signal point.
[0078]
Therefore, when the number of bits of the value Gd is 2 bits, the reliability of four-level values that change stepwise from [11] to [00] is obtained. In this case, the maximum reliability value is obtained. Gmax becomes [11], and the value Gd output from the rounding circuit 41 is supplied to the demodulated bit reliability calculation circuit 34 in FIG. 5 as a demodulated signal point reliability signal indicating the certainty of the selected demodulated signal point. Is done.
[0079]
Next, the low reliability bit position calculation circuit 33 will be described.
As is apparent from FIG. 5, the low reliability bit position calculation circuit 33 is also supplied with a 4-bit demodulated code together with the deviation amount signals ΔI and ΔQ, thereby calculating the low reliability bit position. The circuit 33 calculates the position of the bit of the digit most likely to be errored when an error occurs in the demodulated code from the deviation amount signal and the demodulated code, and outputs it as a low reliability bit position signal.
[0080]
FIG. 7 shows an example of the circuit configuration of the low reliability bit position calculation circuit 33. The deviation amount signals ΔI and ΔQ supplied to this circuit are input to the absolute value calculation circuits 37i and 37q. The values | ΔI | and | ΔQ | are calculated.
Note that the absolute value calculation circuits 37i and 37q in FIG. 7 are circuits that perform the same operation as the absolute value calculation circuits 37i and 37q in FIG. 6, and therefore can be shared. As a result, the configuration is simplified. can do.
[0081]
The calculated absolute values | ΔI | and | ΔQ | are supplied to the comparison circuit 44, where the magnitudes of these absolute values | ΔI | and | ΔQ | are compared.
For example, when | ΔI | ≧ | ΔQ |, the axis code value 1 is output from the comparison circuit 44, and when | ΔI | <| ΔQ |, the axis code value 0 is output from the comparison circuit 44. It is configured. The 1 or 0 axis code value output from the comparison circuit 44 is supplied to the switch 43 as a switch switching signal.
[0082]
Further, these deviation amount signals ΔI and ΔQ are also input to the polarity calculation circuits 42i and 42q, and a polarity code indicating the positive / negative of each value of these signals ΔI and ΔQ, for example, 0 for positive polarity and negative polarity In this case, a polarity code of 1 is input to each contact of the switch 43.
[0083]
Thus, the switch 43 selects and outputs the polarity code of ΔI supplied from the polarity calculation circuit 42 i when the input axis code value is 1, and when the input axis code value is 0, The polarity code of ΔQ supplied from the polarity calculation circuit 42q is selected and output.
[0084]
At this time, the axis code value output from the comparison circuit 44 is based on whether the second adjacent signal point, which is the modulation signal point next to the reception signal point next to the demodulation signal point, is adjacent on the I axis or the Q axis. Indicates whether it is adjacent to the top.
The polarity code output from the switch 43 indicates whether the second adjacent signal point is a modulation signal point located on the positive side of the demodulation signal point or a signal point located on the negative side.
[0085]
Therefore, the sum of the 1-bit axis code output from the comparison circuit 44, the 1-bit polarity code output from the switch 43, and the 4-bit set of demodulated codes input from the 16QAM demodulation circuit 16 (FIG. 1). A set of 6-bit codes is input to the memory 45 as an address code.
[0086]
The memory 45 stores the codes of 16 modulation signal points shown in FIG. 20 in advance, so that the memory 45 corresponds to the second adjacent signal point in the direction specified by the axis code and the polarity code. The code of the second adjacent signal point of one set of 4 bits to be read, for example, the code [1011] in FIG. 20, is read and output.
Thus, the 4-bit 1-set second adjacent signal point code output from the memory 45 is input to the code comparison circuit 47 together with the 4-bit 1-set demodulated code.
[0087]
Then, the code comparison circuit 47 compares the same bit of the 4 bits 1 set of the second adjacent signal point code and the 4 bits 1 set of the demodulation code, and the bits of the digits having different values. Outputs a value representing that the bit belongs to the group A as a low reliability bit position signal, and the bit having the same value is grouped as a low reliability bit position signal. A value indicating that it belongs to notA is output.
[0088]
Specifically, for example, an EXOR (exclusive value) of bit values of the same digit of a code [1011] of a set of 4 bits of the second adjacent signal point code and a code [1111] of a set of 4 bits of a demodulated code is used. (OR) and the operation value [0100] is output as a set of 4 bits of low reliability bit position signals.
[0089]
In this ExOR operation, the operation value of the bits of the same digit in the 4 bits of 1 set of the second adjacent signal point code and the 4 bits of 1 set of the demodulated code is 0, and the bits of different digits are The calculated value is 1, and therefore, the bits having a value of 1 in the set of 4 bits in the low-reliability bit position signal indicate that the code value has many errors and the reliability is low. .
[0090]
As a result, the low-reliability bit position calculation circuit 33 outputs a set of 4-bit low-reliability bit position signals output from the code comparison circuit 47 as a signal representing a digit bit that is likely to cause an error in the demodulated code. As shown in FIG. 5, the low reliability bit position signal is used together with the demodulated signal point reliability signal output from the demodulated signal point reliability calculation circuit 32 as shown in FIG. 34 is input.
[0091]
Therefore, in the demodulated bit reliability calculation circuit 34, the bit represented by the demodulated signal point reliability signal is used for a digit bit indicating that the low reliability bit position signal belongs to the group A, that is, a bit having a value of 1. The degree Gd is directly assigned as the reliability of the bit of that digit Gbit = Gd, and this bit is used for the bit of the digit indicating that the low reliability bit position signal belongs to the notA group, that is, the bit whose value is 0. The reliability Gmax = [11] representing the highest probability of the value of is assigned as the bit reliability Gbit = [11] of this digit.
[0092]
Then, the demodulated bit reliability calculation circuit 34 calculates the reliability Gbit representing the accuracy of the bit of each digit calculated and assigned as described above from the soft decision reliability calculation circuit 17 ′ as a demodulation bit reliability signal. It outputs.
The circuit configuration of the demodulated bit reliability calculation circuit 34 can be configured with a simple switch circuit, and thus detailed description thereof is omitted.
[0093]
In the above description, the reliability Gd is assigned as it is to the bits of the digits belonging to the A group. However, the reliability of the bits of the digits belonging to the A group is the reliability of the bits of the digits belonging to the not A group. A reliability Gbit (Gbit ≦ Gd) smaller than the reliability Gd in advance by a certain amount may be set in advance and assigned so as to be always lower than the degree.
[0094]
Here, when the reliability Gd is extremely lowered, the received signal point is greatly shifted beyond the second adjacent signal point, and as a result, there is a high possibility that the digit bits belonging to the notA group will be erroneous. .
Therefore, when the reliability Gd becomes smaller than a preset value, the reliability Gbit (Gd ≦ Gbit ≦ Gdmax) smaller than the reliability Gmax by a certain amount as the reliability assigned to the bits of the digits belonging to the notA group. ) May be assigned.
[0095]
Returning to FIG. 1, the demodulated bit reliability signal output from the soft decision reliability calculation circuit 17 ′ corresponds to the demodulated code output from the P / S conversion circuit 27, as schematically shown in FIG. A set of digit bits and a pair are input to the deinterleave circuit 28, subjected to order change processing, and then input to a soft decision convolutional code decoding circuit 29 including a soft decision Viterbi decoding circuit compatible with the BPSK modulation method. .
[0096]
In the soft decision convolutional code decoding circuit 29, the code error of the demodulated code is corrected using the reliability input together with the code of each bit of the demodulated code, and the corrected demodulated code is output as an information code.
[0097]
In the demodulated bit reliability signal obtained from the soft decision reliability calculation circuit 17 ′ in the second embodiment, the reception signal point is close to one of the 16 modulation signal points shown in FIG. When the probability of the demodulated code is high, the reliability value of all the digits of the 4-bit set of codes is the value [11] representing the highest reliability.
[0098]
On the other hand, when the received signal point is near the middle line of the two signal points, for example, as shown in FIG. 20, and the probability of the demodulation code is the lowest, the code of the second adjacent signal point is The reliability of the bits of the digits having different bit values is a value [00] indicating that the reliability is the lowest.
[0099]
Even in this case, even if the code of the second adjacent signal point and the bit value are the same, even if the code of the second adjacent signal point is erroneously set as the demodulated code and demodulated, the value is incorrect. The reliability of the bits having no digits is maintained at the highest reliability value [11].
[0100]
Therefore, even if the received signal point is greatly deviated due to noise or the like, there is no possibility that the reliability of the bit of the digit that can hardly be mistaken will be lowered unnecessarily. Therefore, it is the same for all bits of the demodulated code. From the first embodiment in which the reliability of the demodulated signal points is uniformly assigned, the code error correction capability of the soft decision convolutional code decoding can be sufficiently exhibited, and good code error correction can be achieved. Can be executed.
[0101]
As a result, according to the second embodiment, not only the same effects as those of the first embodiment described above can be obtained, but also the code error correction capability is higher than that of the first embodiment and a good code error is achieved. A correction result can be obtained.
[0102]
That is, in the soft decision reliability calculation circuit 17 ′ according to the second embodiment, even when the position of the reception signal point is shifted and the code of the erroneous modulation signal point is demodulated, 4 is made to correspond to the modulation signal point. A low reliability is assigned only to a bit of a digit that has a high possibility of erroneous value within a set of bits.
[0103]
For this reason, a low reliability is assigned to a code that has a low possibility of error, and the error correction capability will not be tampered with, and a good information code with a low code error rate can be decoded.
[0104]
Next, a third embodiment of the present invention will be described.
The third embodiment provides a receiver having a higher code error correction capability than the second embodiment described above, and the circuit configuration of the entire receiver as viewed from the block is the first shown in FIG. The only difference is the circuit configuration and operation of the soft decision reliability calculation circuit 17.
[0105]
However, in this third embodiment, as shown in FIG. 17, the arrangement of a set of 4 bits assigned to each modulation signal point is 1 bit each time the modulation signal point moves horizontally one row. It is necessary to have a code arrangement in which only the code of another 1 bit changes every time the modulation signal point moves one column vertically.
[0106]
FIG. 9 shows a soft decision reliability calculation circuit in the third embodiment. The soft decision reliability calculation circuit 17 in the first embodiment shown in FIG. 1 and the second example shown in FIG. In order to distinguish from the soft decision reliability calculation circuit 17 ′ in the embodiment, a reference numeral 17 ″ is added as a soft decision reliability calculation circuit 17 ″.
[0107]
Therefore, the circuit configuration seen in the block of the entire receiving apparatus of the third embodiment is replaced with the soft decision reliability calculation circuit 17 in the first embodiment shown in FIG. Here, the shift amount calculation circuit 19 is a circuit that calculates the shift amount of the received signal point with respect to the demodulated signal point represented by the demodulated code. The shift amount calculation circuit 19 shown in FIG. The circuit has the same configuration as
[0108]
Next, the demodulated signal point reliability calculation circuit 50 calculates the shift amount of the I component, which is the first component calculated by the shift amount calculation circuit 19, or the magnitude of the shift amount in the Q direction, which is the second component. This is a circuit for calculating the reliability of the demodulated signal point.
The low-reliability bit position calculation circuit 51 is a circuit that calculates the bit position of the digit that is most likely to be erroneous when an error occurs in the demodulated code.
[0109]
Then, the demodulated bit reliability calculation circuit 52 includes the reliability of the demodulated signal points calculated by the demodulated signal point reliability calculation circuit 50, the bit position data of the error-prone digits calculated by the low reliability bit position calculation circuit 51, and This is a circuit for calculating the reliability of each bit of the demodulated code.
[0110]
Next, the operation of the soft decision reliability calculation circuit 17 ″ in the third embodiment will be described.
First, as described with reference to FIG. 3, the deviation amount calculation circuit 19 calculates deviation amount signals ΔI and ΔQ, which are input to the demodulated signal point reliability calculation circuit 50 and the low reliability bit position calculation circuit 51. .
[0111]
First, the demodulation signal point reliability calculation circuit 50 will be described.
FIG. 10 shows an example of the circuit configuration of the demodulated signal point reliability calculation circuit 50. The deviation amount signals ΔI and ΔQ supplied thereto are input to the absolute value calculation circuits 53i and 53q, respectively. First, the absolute value calculation circuit 53i. Then, the absolute value | ΔI | is calculated.
[0112]
The absolute value | ΔI | output from the absolute value calculation circuit 53i is input to the normalization calculation circuit 54i, and the value GIarx is calculated by the next calculation.
GIarx = (0.5 × dP− | ΔI |) / (0.5 × dP)
Here, dP is the distance between the modulation signal points in FIG.
[0113]
The value GIarx calculated in this way is 1 when the received signal point is close to the modulation signal point and the probability of the demodulated code is high, and the received signal point is the midline N between the modulation signal points in the I-axis direction. It is 0 when there is a high possibility that the demodulation code is erroneous. Since the value GIarx calculated at this time is, for example, 10 significant digits, it is input to the rounding circuit 55i and is rounded to a 2-bit value, for example, as in the second embodiment described above, and the I component of the demodulated signal point Reliability G1d is calculated and output as an I component reliability signal.
[0114]
The same applies to the other shift amount signal ΔQ. After the absolute value | ΔQ | is obtained by the absolute value calculation circuit 53q, the value GQarx is calculated by the normalization operation circuit 54q by the following calculation.
GQarx = (0.5 × dP− | ΔQ |) / (0.5 × dP)
Here, dP is the distance between the modulation signal points in FIG.
[0115]
The value GQarx calculated here is also 1 when the reception signal point is near the modulation signal point and the probability of the demodulated code is high, and the reception signal point is the midline N between the modulation signal points in the I-axis direction. It is 0 when there is a high possibility that the demodulation code is erroneous.
Similarly, the signal is rounded to a 2-bit value, for example, by the rounding circuit 55q, and the Q component reliability G2d of the demodulated signal point is calculated, and this is output as the Q component reliability signal.
[0116]
Next, the low reliability bit position calculation circuit 51 will be described.
This low-reliability bit position calculation circuit 51 is a circuit that calculates the position of the bit of the digit that is most likely to be erroneous for each component when an error occurs in the demodulated code. A code is also input.
[0117]
FIG. 11 is a circuit configuration example of the low reliability bit position calculation circuit 51. Of the shift amount signals ΔI and ΔQ input to this circuit, first, one shift amount signal ΔI is the polarity calculation circuit of FIG. 42 is input to a polarity calculation circuit 42i having the same circuit configuration as 42, and a polarity code representing the sign of the value of the deviation amount signal ΔI is calculated.
[0118]
The calculated polarity code is input to the memory 56i as an address code together with a set of 4-bit demodulated codes that are separately input in parallel, and is stored in advance in the memory 56i. A code of a 4-bit set of adjacent signal points in the I direction corresponding to adjacent signal points in the direction specified by the polarity code of the I component is read out.
[0119]
For example, when the demodulation code is [1111], the I-direction adjacent signal point code at this time is [1011] as shown in FIG. 20, and this is read from the memory 56i.
[0120]
A 4-bit set of I-direction adjacent signal point codes output from the memory 56i is input to a code comparison circuit 47i having the same circuit configuration as the code comparison circuit 47 of FIG. The bit values of the same digit of the 4-bit 1-set code of the I-direction adjacent signal point code and the 4-bit 1-set code of the demodulated code are compared.
[0121]
A value indicating that the bit belongs to the group A is output as a low-reliability bit position signal for the bits having different values, and the bit having the notA group is provided for the bits having the same value. A value indicating that the signal belongs to the I direction is output as an I direction low reliability bit position signal. For example, in the case of FIG. 20, the I direction low reliability bit position signal is [0100].
[0122]
Similarly, the other deviation amount signal ΔQ is input to the polarity calculation circuit 42q, and a polarity code representing the sign of the value is calculated. The calculated polarity code and a separately input 4-bit demodulated code are input to the memory 56q as an address code, and a 4-bit 1-set Q-direction adjacent signal point code is read from the memory 56q.
[0123]
Next, this Q-direction adjacent signal point code is input to the code comparison circuit 47q, and a Q-direction low reliability bit position signal indicating whether each digit of the demodulated code is a group A bit or a notA group bit is calculated. Is output. For example, in the case of FIG. 20, the Q direction adjacent signal point code is [1110], and the Q direction low reliability bit position signal is [0001].
[0124]
Each set of 4-bit low-reliability bit position signals and I-direction low-reliability bit position signals calculated by the code comparison circuits 47i and 47q are bits of digits that are likely to cause errors in the demodulated code. The signal representing the position is output from the low reliability bit position calculation circuit 51 of FIG.
[0125]
Thus, the I-direction low reliability bit position signal and the Q-direction low reliability bit position signal output from the low reliability bit position calculation circuit 51 have the reliability G1d and reliability output from the demodulated signal point reliability calculation circuit 50. The demodulated bit reliability calculation circuit 52 is supplied together with the degree G2d.
[0126]
In the demodulated bit reliability calculation circuit 52, the I-direction low-reliability bit position signal or the Q-direction low-reliability bit position signal represents a digit bit indicating that it belongs to the A group, that is, a bit whose value is 1 The reliability G1d represented by the I component reliability signal in Table 0 or the reliability G2d represented by the Q component reliability signal is assigned as the bit reliability Gbit (Gbit = G1d: Gbit = G2d).
[0127]
On the other hand, when both the I-direction low reliability bit position signal and the Q-direction low reliability bit position signal belong to the notA group, that is, when both values are 0-digit bits, the value of this bit The reliability Gmax = [11] representing the highest probability is assigned as the reliability Gbit = [11] of the bit of this digit.
[0128]
Then, the reliability Gbit representing the probability of each digit assigned in this way is output as a demodulated bit reliability signal.
FIG. 12 shows an example of the circuit configuration of the demodulated bit reliability calculation circuit 52. As can be seen from FIG. 12, it can be configured with a simple switch circuit.
First, the switch 57 assigns the reliability G2d to the bit indicating that the Q direction low reliability bit position signal is the group A, and assigns the reliability Gmax = [11] to the other bits of the notA group.
[0129]
Next, the switch 58 outputs the bit value indicating that the I direction low reliability bit position signal is the group A with the reliability G1d.
The demodulated bit reliability signal output from the demodulated bit reliability calculation circuit 52 is used as the output of the soft decision reliability calculation circuit 17 ″ shown in FIG.
[0130]
In the above description, the reliability G1d or G2d is assigned to the digit bits belonging to the group A as they are. However, as in the first embodiment, the reliability is smaller than the reliability G1d or G2d by a certain amount. Needless to say, the degree Gbit (≦ G1d) or the reliability Gbit (≦ G2d) may be set in advance and assigned.
[0131]
Thereafter, as shown in FIG. 1, the demodulated bit reliability signal output from the soft decision reliability calculation circuit 17 ″ is the same as the demodulated code output from the P / S conversion circuit 27 as in the first embodiment. As shown in FIG. 21, a set of bits corresponding to each digit is input to the deinterleave circuit 28, and after the order is changed, a soft decision Viterbi decoding circuit compatible with the BPSK modulation method is formed. It is input to the determination convolutional code decoding circuit 29.
[0132]
As a result, the soft decision convolutional code decoding circuit 29 corrects the code error of the demodulated code using the reliability input together with the code of each bit of the demodulated code, and outputs the corrected demodulated code as an information code. Will be.
[0133]
Therefore, according to the third embodiment, it is possible to configure a receiving apparatus using the 16QAM demodulating circuit 16 as the multilevel modulation signal demodulating circuit using the existing soft decision Viterbi decoding circuit compatible with the BPSK modulation method. As a result, even in a 4-level or higher-level multi-level modulation receiving device using interleave processing that changes the order of code strings in bit units, transmission performance by further multi-leveling is not required without the development of a new LSI. Therefore, it is possible to obtain an inexpensive receiving apparatus based on soft-decision Viterbi decoding, in which a large improvement in the above can be easily obtained.
[0134]
Here, in the case of the second embodiment already described, when the shift of the received signal point is limited to the I-axis direction or the Q-axis direction, the bit of the low-reliability digit can be calculated accurately. it can.
However, although the probability is low, as shown in FIG. 13, the received signal point may be greatly shifted in the oblique direction. In this case, not only the second adjacent signal point in the I-axis direction or the Q-axis direction, The possibility that the modulation signal point X in the oblique direction is mistaken for the second adjacent signal point cannot be ignored.
[0135]
That is, in the second embodiment, in such a case, the modulation signal point that is forcibly closest is selected from the two adjacent signal points in the I-axis direction and the Q-axis direction, and the bit of the low-reliability digit is selected. Therefore, an error occurs in the calculated bit position of the low-reliability digit, and as a result, the code error correction capability may be somewhat deteriorated.
[0136]
On the other hand, in the third embodiment, as shown in FIGS. 17 and 13, the code of one set of 4 bits assigned to each modulation signal point changes independently in the I-axis direction and the Q-axis direction. Therefore, there is no possibility of deterioration as described above.
That is, the code [1111] of the demodulated signal point S and the code [1011] of the second adjacent signal point in the I-axis direction shown in FIG. It is a bit.
[0137]
However, the code [1010] of the modulation signal point X diagonally upper right of the demodulated signal point is also a bit of a low-reliability digit, with the bit value of the third digit from the right being different from the code value of the demodulated signal point. .
Similarly, the code [1110] of the second adjacent signal point in the Q-axis direction is a bit of a low-reliability digit, with the first digit value from the right being different from the code value of the demodulated signal point S. .
[0138]
However, the sign of the modulation signal point X diagonally upper right of the demodulated signal point is also a bit of a low-reliability digit, unlike the code value of the demodulated signal point in the first digit from the right. In addition, the sign of the modulation signal point X and the sign of the demodulation signal point S on the upper right are the same in the values of the bits in the other digits.
[0139]
Therefore, as in the third embodiment, if the bit position of the low-reliability digit is calculated independently in the I-axis direction and the Q-axis direction and the reliability is assigned to the bit of each digit of the demodulated code, Even when the received signal point is greatly displaced in the oblique direction, the bit position of the low-reliability digit can be correctly calculated and the correct reliability is assigned, so that the code error correction capability becomes higher than that of the second embodiment, A good code error correction result can be obtained.
[0140]
Therefore, by using the soft decision reliability calculation circuit 17 ″ according to the third embodiment, the same effect as that of the second embodiment can be obtained, and a good code error correction result with higher code error correction capability can be obtained. Can be obtained.
[0141]
That is, according to the third embodiment, the bit position of the low-reliability digit is correct not only when the reception signal point is shifted in the vertical direction or the horizontal direction but also when it is greatly shifted in the diagonal direction. Only the bits of the digits that are calculated and have a high possibility of erroneous values are reliably assigned a low reliability.
[0142]
As a result, a low reliability is assigned to a code with a low possibility of error, and the error correction capability is unnecessarily lowered, or a high reliability is mistakenly assigned to a bit of an error-prone digit and the error correction capability is unnecessarily lowered. Therefore, a good information code with a low code error rate can be decoded.
[0143]
In the above embodiment, the case where the present invention is applied to the 16QAM modulation system has been described. However, the present invention can be applied to reception apparatuses of other modulation systems such as 32QAM, 64QAM, 8PSK, and 16APSK. Needless to say.
Here, the PSK method is a phase displacement modulation method, and the APSK method is an amplitude phase displacement modulation method.
[0144]
Then, next, as a fourth embodiment of the present invention, as shown in FIG. 14, an embodiment in which the present invention is applied to a 16APSK modulation system in which the arrangement of modulation signal points is greatly different from that in FIG. Will be described with reference to FIG.
[0145]
The modulation signal points in the fourth embodiment are arranged on a double circle as shown in FIG. 14, and the difference from the 16QAM receiver according to the first to third embodiments is as follows. As is apparent from FIG. 15, the baseband received signals Ida and Qda output from the AD conversion circuits 10i and 10q are first converted into an amplitude value Rda and a phase value θda in the polar coordinate expression by the polar coordinate conversion circuit 62. It is in the point to process.
[0146]
The amplitude value Rda and the phase value θda converted into polar coordinates are branched into two systems, one of which is input to the 16APSK demodulation circuit 63 and the other is input to the soft decision reliability calculation circuit 64.
[0147]
First, in the 16APSK demodulation circuit 63, the modulation signal point closest to the amplitude value Rda and the phase value θda of the reception signal point is selected and selected from the 16 modulation signal points shown in FIG. A set of 4 bits assigned to the demodulated signal point is output as a demodulated code.
[0148]
On the other hand, the other branched amplitude value Rda and phase value θda are input to the soft decision reliability calculation circuit 64 together with a 4-bit set of demodulated codes demodulated by the 16APSK demodulation circuit 63.
FIG. 16 is a circuit configuration example of the soft decision reliability calculation circuit 64. First, the shift amount calculation circuit 65 calculates the shift amounts ΔR and Δθ of the received signal point from the demodulated signal point represented by the demodulated code. And a circuit that outputs the signal as a deviation amount signal.
[0149]
Next, the demodulated signal point reliability calculation circuit 66 calculates the deviation amount of the R component, which is the first component calculated by the deviation amount calculation circuit 65, or the magnitude of the deviation amount of the θ component, which is the second component. This is a circuit for calculating the reliability of the demodulated signal point.
The low-reliability bit position calculation circuit 67 is a circuit that calculates the bit position of the digit that is most likely to be erroneous when an error occurs in the demodulated code.
[0150]
Further, the demodulated bit reliability calculation circuit 68 converts the reliability of the demodulated signal point calculated by the demodulated signal point reliability calculation circuit 66 and the bit position data of the error-prone digit calculated by the low reliability bit position calculation circuit 67. This is a circuit for calculating the reliability of each bit of the demodulated code.
[0151]
In each of these circuits, signal processing substantially similar to that of the third embodiment is executed except that the input signal is replaced with the amplitude value Rda and the phase value θda from the received signals Ida and Qda. In this case, the first I component is the R component and the second Q component is the θ component.
[0152]
Returning to FIG. 15, the demodulated bit reliability signal calculated and output from the soft decision reliability calculation circuit 64 is the demodulated code output from the P / S conversion circuit 27 as in the first embodiment. A soft decision convolutional code decoding composed of a Viterbi decoding circuit of a soft decision method corresponding to the BPSK modulation method after being inputted to the deinterleave circuit 28 as a set with a bit corresponding to each digit of the Input to the circuit 29.
[0153]
Then, the soft decision convolutional code decoding circuit 29 corrects the code error of the demodulated code using the reliability input together with the code of each bit of the demodulated code, and outputs the corrected demodulated code as an information code. become.
Therefore, by using the soft decision reliability calculation circuit 64 according to the fourth embodiment, an effect equivalent to that of the above-described third embodiment can be obtained even in a 16APSK modulation transmission apparatus.
[0154]
By the way, in the second embodiment described above, the second adjacent signal point is calculated, and the bit of the low-reliability digit is calculated from the second adjacent signal point. In this case, if the received signal point greatly deviates, the calculated low reliability is calculated. The value of bits other than the degree bit is also likely to be erroneous.
[0155]
Therefore, when the deviation amount exceeds a certain amount, the code error correction capability can be further enhanced by lowering the reliability of all bits by a certain amount.
This is the same as in the third embodiment and the fourth embodiment described above. Similarly, when the deviation amount exceeds a certain amount, the reliability of all bits is also lowered by a certain amount, thereby further improving the code error correction capability. Can be increased.
[0156]
As described above, in the second embodiment, the second adjacent signal point is calculated and the bit of the low-reliability digit is calculated, but the I-axis direction and the Q-axis are independent of the direction of the shift amount. Compares the bit value of the code of the adjacent signal point adjacent to the direction and the bit value of the demodulated code, calculates the bit of the different value as the bit of the low reliability digit, and the bit of this low reliability digit The reliability of demodulated signal points may be assigned to.
[0157]
In this case, however, the sign error is also reduced because the bit of the digit with a different value from the sign of the adjacent signal point with the opposite direction of the shift direction is less likely to be mistaken, and therefore, the bit of the digit with less chance of error. Although there is a possibility that the correction capability may be reduced, the processing contents are simplified correspondingly, and there is an advantage that the circuit scale can be reduced.
[0158]
Also, in the soft decision reliability calculation circuit 17 ′ in the second embodiment, for example, the upper 2 bits are extracted from the calculated 10-bit value Garx and used as the reliability. An arbitrary threshold Th (for example, Th1 <Th2 <Th3) is set. When Garx <Th1, the reliability is set to [00], and when Th1 ≦ Garx <Th2, the reliability is [01], Th2 ≦ Garx. The reliability may be calculated by a method such as reliability [10] when <Th3, and [11] when Th3 ≦ Garx.
[0159]
Needless to say, this is the same in other embodiments.
In addition, when it is easier to calculate the deviation amount by a multi-level modulation signal demodulation circuit such as a 16QAM demodulation circuit, or other circuits, it goes without saying that the deviation amount calculation circuit may be shared. .
[0160]
On the other hand, as shown in FIG. 17, the modulation signal point and the code arrangement are distinguished in the Q component direction by the first and second bits of the code, and the I component direction is distinguished by the third and fourth bits of the code. When the digit of the bit corresponding to each component is separated, the calculation in the low reliability bit position calculation circuit is performed by comparing only the bits of the digit corresponding to each component. Needless to say, it is desirable. The same applies to the demodulated bit reliability calculation circuit.
[0161]
Further, in the above embodiments, the reliability has been described in which the value increases as the probability of the value such as the sign increases, but conversely, even if a parameter whose value decreases as the probability increases, the circuit can be used. Obviously, the same configuration can be achieved with only minor modifications.
[0162]
【The invention's effect】
According to the present invention, it is possible to easily apply Viterbi decoding by a soft decision method without developing a new LSI even in a reception device of a multilevel modulation method of four or more values, and has high error correction accuracy. A high-performance receiving apparatus can be provided inexpensively and easily.
[0163]
Similarly, according to the present invention, the Viterbi decoding by the soft decision method can be easily applied even to a transmission device of a four-value or more multi-level modulation method using an interleaving process in which the order of the code string is changed in bit units.
[0164]
Furthermore, according to the present invention, it is possible to calculate the bit position of an error-prone digit instead of lowering the reliability of all digits of the demodulated code, and to reduce only the reliability of the bit. The code error correction capability of the soft decision convolutional code decoding can be greatly improved. As a result, a highly reliable receiving apparatus having excellent code error correction characteristics can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing an example of a receiving apparatus to which a first embodiment of a convolutional code soft decision decoding circuit according to the present invention is applied.
FIG. 2 is a block circuit diagram showing an example of a transmission apparatus using a convolutional coding multi-level modulation method targeted by the present invention.
FIG. 3 is a block circuit diagram showing an example of a soft decision reliability calculation circuit according to the first embodiment of the present invention.
FIG. 4 is a block circuit diagram showing an example of a deviation amount calculation circuit in the first embodiment of the present invention.
FIG. 5 is a block circuit diagram showing an example of a soft decision reliability calculation circuit according to the second embodiment of the present invention.
FIG. 6 is a block circuit diagram showing an example of a demodulated signal point reliability calculation circuit in the second embodiment of the present invention.
FIG. 7 is a block circuit diagram showing an example of a low reliability bit position calculation circuit in the second embodiment of the present invention.
FIG. 8 is an explanatory diagram showing a relationship between bits of each digit of a demodulated code and reliability in the second embodiment of the present invention.
FIG. 9 is a block circuit diagram showing an example of a soft decision reliability calculation circuit according to a third embodiment of the present invention.
FIG. 10 is a block circuit diagram illustrating an example of a demodulated signal point reliability calculation circuit according to a third embodiment of the present invention.
FIG. 11 is a block circuit diagram showing an example of a low reliability bit position calculation circuit according to a third embodiment of the present invention.
FIG. 12 is a block circuit diagram showing an example of a demodulation bit reliability calculation circuit in the third embodiment of the present invention.
FIG. 13 is an explanatory diagram showing an example of a state where reception signal points are obliquely shifted.
FIG. 14 is an explanatory diagram illustrating an example of a 16APSK modulation scheme signal point and code arrangement state;
FIG. 15 is a block circuit diagram showing an example of a receiving apparatus to which a fourth embodiment of a soft decision decoding circuit for convolutional codes according to the present invention is applied.
FIG. 16 is a block circuit diagram showing an example of a soft decision reliability calculation circuit according to the fourth embodiment of the present invention.
FIG. 17 is an explanatory diagram illustrating an example of a 16QAM modulation scheme signal point and code arrangement state;
FIG. 18 is a block circuit diagram showing an example of a 16QAM modulation scheme transmission apparatus according to the prior art.
FIG. 19 is a block circuit diagram showing an example of a 16QAM modulation system receiver according to the prior art.
FIG. 20 is an explanatory diagram showing a state in which received signal points of the 16QAM modulation method are shifted.
FIG. 21 is an explanatory diagram showing a relationship between a bit of each digit of a demodulated code and reliability in the third embodiment of the present invention.
[Explanation of symbols]
1 Convolutional coding circuit
2 16QAM modulation circuit
3 DA conversion circuit
4, 9 mixer
5 Upconverter
6 Transmitting antenna
7 Receiving antenna
8 Down converter
10 AD converter circuit
11 Soft decision Viterbi decoding circuit
12 Synchronous playback circuit
13 Convolutional coding circuit
14 Interleave circuit
15 S / P conversion circuit
16 16QAM demodulation circuit
17, 17'17 "soft decision reliability calculation circuit
19 Deviation amount calculation circuit
20 Demodulation signal point reliability calculation circuit
21 Demodulation bit reliability calculation circuit
22 16QAM modulation circuit
24 Absolute value calculation circuit
25 Subtraction circuit
26 Rounding circuit
27 P / S conversion circuit
28 Inverse interleave circuit
29 Soft decision convolutional code decoding circuit
32 Demodulation signal point reliability calculation circuit
33 Low reliability bit position calculation circuit
34 Demodulation bit reliability calculation circuit
37 Absolute value calculation circuit
38 MAX circuit
39 Normalized arithmetic circuit
41 Rounding circuit
42 Polarity calculation circuit
43 switch
44 Comparison circuit
45 memory
47 Sign comparison circuit
50 Demodulation signal point reliability calculation circuit
51 Low reliability bit position calculation circuit
52 Demodulation bit reliability calculation circuit
53 Absolute value calculation circuit
54 Standardized arithmetic circuit
55 Rounding circuit
56 memory
57, 58 switch
62 Polar coordinate conversion circuit
63 16APSK demodulation circuit
64 Soft decision reliability calculation circuit
65 Deviation calculation circuit
66 Demodulation signal point reliability calculation circuit
67 Low reliability bit position calculation circuit
68 Demodulation bit reliability calculation circuit
N middle line
S Demodulation signal point position
X Diagonal upper right modulation signal point

Claims (3)

2 ⁿ signal points (modulation signal points) set on a complex plane that is a signal space to input a baseband received signal that has undergone multilevel modulation and transmit a set of n-bit codes on the transmission side The modulation signal point closest to the signal point (reception signal point) represented by the value of the received signal is selected from the above, and a set of n-bit codes assigned to the selected modulation signal point is calculated and demodulated In a receiving device including a multi-level modulation signal demodulating circuit that outputs as a code,
The baseband received signal and a set of n-bit demodulated codes output from the multilevel modulated signal demodulation circuit are input, and a modulation signal point (demodulated signal point) corresponding to the n-bit set of demodulated codes Thus, the amount of deviation of the received signal point with respect to the at least one bit of the n-bit set of demodulated codes is calculated, so that the larger the calculated amount of deviation, the more likely the value of the bit is. Is assigned a reliability Gbit = G1 representing a low value, and a reliability Gbit = G2 representing that the smaller the deviation amount is, the higher the probability of the value of the one bit is. The remaining bits of the demodulated code are assigned a reliability Gbit ≧ G2 indicating that the probability of the value of the bit is equal to the reliability of the reliability G2 or higher than the reliability of the reliability G2. Degree of reliability On calculating the bit, it provided the soft decision reliability calculator circuit that outputs the reliability Gbit as the demodulated bit reliability signal,
The multi-level modulation signal demodulating circuit is constituted by a soft decision convolutional code decoding circuit compatible with the BPSK modulation method, which performs soft decision based on a demodulated bit reliability signal output from the soft decision reliability calculation circuit. A convolutional code soft decision decoding receiver. In the invention of claim 1,
A shift amount calculation circuit that inputs the n-bit set of demodulated codes and the baseband received signal, calculates a shift amount of the received signal point with respect to the demodulated signal point, and outputs it as a shift amount signal;
When the deviation amount signal is input, and the magnitude of the deviation amount represented by the deviation amount signal is 0, the reliability Gd = Gdmax indicating that the probability of the demodulation signal point is the highest is calculated, and the deviation amount is calculated. When the magnitude of the quantity is greater than 0, the reliability Gd <Gdmax, which indicates that the probability of the demodulation signal point is lower as the magnitude of the deviation is larger, is calculated, and the calculated reliability Gd is A demodulation signal point reliability calculation circuit that outputs a demodulation signal point reliability signal representing the certainty of the selected demodulation signal point;
The n-bit set of demodulated codes and the deviation amount signal are input, and a second adjacent signal point that is a modulation signal point closest to the reception signal point after the demodulation signal point is calculated, and the calculated second The bit values of the same digit in the n-bit set of codes assigned to the adjacent signal points and the demodulated code of the n-bit set of codes are compared with each other. A value representing a group is output as a low-reliability bit position signal, and a value representing that the bit is a notA group is output as a low-reliability bit position signal to bits having the same value. A low-reliability bit position calculation circuit;
The low-reliability bit position signal and the demodulated signal point reliability signal are input, and the bit of the digit indicating that the low-reliability bit position signal belongs to the group A in the n-bit set of demodulated codes, A reliability Gbit ≦ Gd that is equal to the reliability Gd represented by the demodulated signal point reliability signal or smaller than the reliability Gd by a predetermined amount is calculated and assigned, and the low reliability bit position signal is not group A The bit G of the digit indicating that it belongs to is calculated by assigning the reliability Gdmax representing the highest probability or a reliability Gbit ≦ Gdmax (Gd ≦ Gbit) which is smaller by a certain amount determined by the magnitude of the reliability Gd. A demodulating bit reliability calculation circuit that outputs a reliability Gbit representing the probability of each digit bit and outputs it as a demodulating bit reliability signal;
The soft decision reliability calculation circuit is configured by the shift amount calculation circuit, the demodulated signal point reliability calculation circuit, the low reliability bit position calculation circuit, and the demodulation bit reliability calculation circuit. A convolutional code soft decision decoding receiver. In the invention of claim 1,
The n-bit set of demodulated codes and the baseband received signal are input, and the first component of the amount of deviation of the received signal point with respect to the demodulated signal point is a deviation amount ΔI in the I-axis direction and the second component The Q-axis direction deviation amount ΔQ, or the first component radial direction deviation amount ΔR and the second component angular direction deviation amount Δθ are calculated and output as a deviation amount signal. A deviation amount calculation circuit;
When the shift amount signal is input and the shift amount of the first component or the shift amount of the second component represented by the shift amount signal is 0, the first component or the first component of the demodulated signal point The first component reliability G1d = Gdmax or the second component reliability G2d = Gdmax, which indicates that the probability of the two components is the highest, is calculated. When it is larger, the reliability of the first component G1d <Gdmax, which represents that the probability of the component of the demodulated signal point is lower as the deviation amount of the component is larger, or the reliability of the second component A demodulation signal point reliability calculation circuit that calculates G2d <Gdmax and outputs these reliability values G1d and G2d as a demodulation signal point reliability signal indicating the probability of the selected demodulation signal point;
The n-bit set of demodulated code and the shift amount signal are input, and the adjacent modulation signal point of the first component in the direction of the polarity code of the shift amount of the first component with respect to the demodulated signal point is calculated. In addition, the value of the bit of the same digit of the n-bit 1-set code assigned to the calculated adjacent modulation signal point of the first component and the n-bit 1-set code of the demodulated code is compared, and the value is For bits of different digits, a value indicating that the bits are of group A is output as a low-reliability bit position signal of the first component, and for bits of digits having the same value, the bit is A value representing the notA group is output as a low-reliability bit position signal of the first component, and the second component in the direction of the polarity code of the shift amount of the second component with respect to the demodulated signal point The adjacent modulation signal point of the component is calculated and the calculated second component The bit values of the same digit of the n-bit 1-set code assigned to the adjacent modulation signal points and the n-bit 1-set code of the demodulated code are compared. A value indicating that the bit is in the group A is output as a low-reliability bit position signal of the second component, and the bit having the same value indicates that the bit is in the notA group. The value is output as a low reliability bit position signal of the second component, and the low reliability bit position signal of the first component and the low reliability bit position signal of the second component are used as the low reliability bit position signal. A low-reliability bit position calculation circuit for output;
The low-reliability bit position signal and the demodulated signal point reliability signal are input, and in the n bits of one set of demodulated codes, the low-reliability bit position signal is converted to a digit bit indicating that it belongs to the A group. Is either the reliability G1d or G2d represented by the demodulated signal point reliability signal of the same component, or any one of the reliability Gbit ≦ G1d or Gbit ≦ G2d smaller than the reliability G1d or G2d by a predetermined amount. And the bit of the digit indicating that the low reliability bit position signal belongs to the notA group is determined by the reliability Gdmax indicating the highest probability, or the reliability G1d or G2d. Any one of a small degree of reliability Gbit ≦ Gdmax (G1d ≦ Gbit or G2d ≦ Gbit) is assigned, and each is represented as a reliability Gbit representing the probability of each digit bit. And a demodulation bit confidence calculation circuit for outputting a reliability signal provided,
The soft decision reliability calculation circuit is configured by the shift amount calculation circuit, the demodulated signal point reliability calculation circuit, the low reliability bit position calculation circuit, and the demodulation bit reliability calculation circuit. A convolutional code soft decision decoding receiver.

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