JP3348303B2 - Viterbi decoding method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding method as a maximum likelihood decoding for decoding a convolutionally coded modulation signal and an apparatus therefor.

[0002]

2. Description of the Related Art For example, in a satellite communication system, S /
Since it is difficult to improve N compared to other communication systems,
The receiving side is required to perform high-performance detection and correction on the received information sequence, and the transmitting side encodes the digital information sequence, adds redundant bits, and transmits it. As encoding methods, for example, block encoding and convolutional encoding are known. In block coding, a digital information sequence is divided into blocks of m bits, a redundant component for error correction is added to this information component, and n-bit data (m <
n).

[0003] In convolutional coding, the information of a time slot obtained by dividing a past information sequence for each predetermined bit affects the current block (the number of time slots affected is referred to as a "constraint length"). ) A method of performing coding, which enables high error correction to be performed on the receiving side even if the constraint length is short, has high information efficiency, and is widely used in fields such as communication.

One of the methods for decoding a convolutional code is as follows.
A Viterbi decoding method is known. This Viterbi decoding method is a maximum likelihood decoding method for a convolutional code, and an error is generated by selecting a sequence closest to a received code sequence (this is referred to as a maximum likelihood path) from a code sequence that can be generated from an encoder on the transmission side. Make corrections. This method of selecting the maximum likelihood path does not compare and confirm all paths, but calculates the Euclidean distance between all the code strings that can be generated on the transmission side and the received code string, and determines the Euclidean distance that is the smallest (that is, the likelihood is small). The highest is selected, and after that, only the path (survival path) necessary for decoding is basically examined. If the length of the path is sufficiently long, the end of the surviving path (root) Join to the same value, no matter which surviving path
Looking back, it means that the same value has been decoded. Therefore, a path length that does not increase the decoding error rate can be checked, and data at a point in time traced back by that length can be used as decoded data. In addition, the Viterbi decoding method can obtain a particularly high error correction capability by being combined with a so-called soft decision demodulation method.

Attention has been paid to trellis-coded modulation that combines the above-described convolutional coding and multilevel modulation. In the trellis coded modulation, on the transmitting side, the transmission signal is convolutionally coded using a convolutional coding circuit, and a margin for added noise is increased, so that the Euclidean distance between the transmission signals is increased. Is assigned to a modulation signal point and transmitted. Then, on the receiving side, using a Viterbi decoding device,
From the signal sequence that can be a transmission signal, the maximum likelihood path that is the signal sequence that minimizes the Euclidean distance from the reception signal is selected and the reception signal is decoded.

FIG. 8 shows a configuration diagram of a convolutional encoding circuit. FIG. 9 is a diagram for explaining signal points in the 16QAM modulation method. As shown in FIG. 8, the convolutional encoding circuit 2
Serial / parallel converter 25, delay circuits 26, 27, 2
8 and exclusive OR calculators 29 and 30. The serial / parallel converter 25 parallelizes an input signal S1, which is serial data, for example, composed of 3 bits (x3, x2, x1), and converts x3 into signals y1, x2.
Are output as signals y2 and x3 as signal y3. Signals y1, y2, y output from serial / parallel converter 25
3 is output as it is to the signal assignment circuit (not shown) as y1, y2, y3 of the signal S2 indicating the output signal point.
The delay circuits 26, 27 and 28 convert the input signal into, for example,
The output is delayed by one clock cycle. Exclusive OR calculators 29 and 30 output signals from delay circuits 26 and 27,
Further, it receives the y1 signal and the y2 signal from the serial / parallel converter 25, respectively, and calculates an exclusive OR of these signals.

The calculation result of the exclusive OR calculator 30 is output to a signal allocation circuit (not shown) as y0 of a signal S2 indicating an output signal point. For example, convolutional encoding circuit 2
Inputs (1, 0, 1) as an input signal S1 and, for example, based on the state of the delay circuits 26, 27, 28, y
It calculates 0 = 0 and outputs a signal S2 indicating the output signal point (1, 0, 1, 0). At this time, the convolutional encoding circuit 2
The input signal S1 of 3 bits and 8 types is input, and the signal S indicating 16 types of output signal points according to the 8 types of states of the convolutional coding circuit 2 at that time (that is, the states of three delay circuits).
2 is output. At this time, the state transition of the convolutional coding circuit 2 and the relationship between the output signal points are shown in a trilles expression diagram described below.

FIG. 10 shows a trellis expression diagram of the convolutional coding circuit 2 described above. As shown in FIG. 10, the convolutional encoding circuit 2 outputs a signal S2 indicating an output signal point s0, for example, along the path 80a according to the content of the input signal S101 from the state A. The state transits to the state A. As shown in FIG. 10, in the trellis expression of the convolutional coding circuit 2 used for the 16QAM modulation method, there are cases where two parallel paths exist in the state transition. That is, in the same state of the convolutional encoding circuit 2, there are cases where different types of input signals S1 are input, different output signal points corresponding to the respective input signals S1 are output, and the state transits to the same state. For example, the convolutional coding circuit 2 also outputs the signal S2 indicating the output signal point s8 from the state A, for example, along the path 80a according to the content of the input signal S101, and transitions to the state A, for example. I do. As described above, the path 80a that causes the convolutional encoding circuit 2 to transition from the state A to the state A is the output signal point s
It is composed of a parallel path that outputs 0 and makes a transition, and a parallel path that outputs output signal point s8 and makes a transition.

[0009]

In the Viterbi decoding device, a Euclidean distance between a received signal and a modulated signal point that can be taken by a transmitted signal, that is, an output signal point is calculated, and the square of the Euclidean distance is used as a branch metric. Calculate the sum of the branch metric and the state metric that merge in the same state, control the path memory as the branch with the smallest sum as the surviving branch, and obtain the maximum likelihood path sequentially using the minimum value of the sum as the state metric .
Therefore, when a plurality of paths are parallel in the transition between the states (that is, when there are parallel paths), the Euclidean distance between the signal point output for each parallel path and the received signal is calculated, This calculation result is output to the ACS circuit as a branch metric BM, and A
In the CS circuit, it is necessary to determine which of the parallel paths is to be selected, which complicates the circuit and reduces the operation speed. The calculation of the Euclidean distance in the branch metric circuit is performed by hardware, and when processing is performed for a plurality of modulation schemes, it is necessary to create a circuit corresponding to each modulation scheme.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a Viterbi decoding method and apparatus capable of shortening the processing time and simplifying and reducing the circuit scale. And

[0011]

A Viterbi decoding apparatus according to a first aspect of the present invention is a Viterbi decoding apparatus which performs a branch metric operation on a modulated received signal to determine a maximum likelihood path, and calculates a branch metric. The circuit has means for determining a selected path from the parallel path based on a state of a received signal modulated by a modulation method in which a parallel path exists and a predetermined condition defined by the modulation method. The Viterbi decoding is performed based on the selected path, and the means for determining the selected path is configured to determine in advance a parallel path having the shortest distance as a selected path for a signal point corresponding to the received signal and each parallel path. The selection path is determined based on the programmed contents.

[0012] In the Viterbi decoding apparatus according to the first invention, preferably, the circuit for calculating the branch metric has means for determining the selected path corresponding to each of a plurality of sets of parallel paths. Means for determining the selected path simultaneously and in parallel.

[0013] In the Viterbi decoding apparatus according to the first invention, preferably, the means for determining the selected path is configured to determine the selected path corresponding to a plurality of predetermined modulation methods. The selected path is determined according to the modulation method used.

In the Viterbi decoding device according to the first invention, preferably, the distance is a Euclidean distance, and the circuit for calculating the branch metric stores, in advance, a Euclidean distance using the received signal as a parameter for a signal point. And converting means for outputting a Euclidean distance corresponding to the parameter.

[0015] In the Viterbi decoding device according to the first invention, preferably, the received signal is a convolutional coded signal.

In the Viterbi decoding apparatus according to the first invention, preferably, the convolutional coded signal is a trellis coded signal.

The Viterbi decoding method according to a second aspect of the present invention selects the parallel path based on a state of a received signal modulated by a modulation method having a parallel path and a predetermined condition defined by the modulation method. Selecting a path and performing Viterbi decoding based on the selected path, wherein the selection of the selected path is pre-programmed to select the parallel path having the shortest distance for the signal point corresponding to the received signal and each parallel path. Perform based on the content.

In the Viterbi decoding method according to the second aspect of the present invention, it is preferable that the selected path is determined simultaneously and in parallel for each set of parallel paths.

[0019]

[0020]

[0021]

According to the Viterbi decoding method of the present invention, for example, a parallel path having the shortest Euclidean distance is selected for a received signal and a signal point corresponding to each parallel path based on the contents programmed in advance corresponding to the modulation method. Determine as a path. Then, the Euclidean distance between the signal point corresponding to the selected path and the received signal is extracted, for example, from the Euclidean distance calculated in advance. Thereafter, Viterbi decoding is performed based on the selected path and its Euclidean distance.

[0022]

[Embodiment] A first embodiment will be described. FIG. 1 shows a diagram for explaining the transmission / reception system of the present embodiment. FIG. 2 shows a configuration diagram of the Viterbi decoding device of the present embodiment. As shown in FIG. 1, in the transmission / reception system of the present embodiment, the convolution encoding circuit 2 receives the transmission data S101, convolutionally encodes the transmission data S101, and outputs the encoded signal S2 to the signal allocation circuit 4. I do. The convolutional encoding circuit 2 is the same as the convolutional encoding circuit 2 described in the prior art.

The signal allocating circuit 4 converts the coded signal S2 inputted from the convolutional coder 2 into an Euclidean distance between transmission signals in order to increase a margin for added noise. Are assigned to the modulation signal points so as to increase, and the I signal S4a and the Q signal S4b are output to the 16QAM modulation circuit 7. I signal S4
a is, for example, a baseband signal having a 4-level amplitude on the I axis of 16QAM. The Q signal S4b is, for example, a baseband signal having a quaternary amplitude on the Q axis of 16QAM.

The 16QAM modulation circuit 7 includes a signal allocation circuit 4
The I signal S4a and Q signal S4b input from
The transmission signal S7a is transmitted to the receiving side after QAM modulation. 1
As shown in FIG. 1, the 6QAM modulation circuit 7 includes a local oscillation circuit 9, mixers 8a and 8b, a hybrid circuit 10, an addition circuit 11, and a band-pass filter (BPF) 12. In the 16QAM modulation circuit 7, the mixer 8a modulates the carrier S9 from the local oscillator 9 with the I signal S4a from the signal allocation circuit 4 in carrier suppression AM modulation, and the mixer 8ab changes the phase of the carrier S9 from the hybrid device 10 by π. The carrier signal S10 shifted by / 2 is combined with the signal S8b obtained by carrier-suppressed AM modulation by the Q signal S4b from the signal assignment circuit 4 by the adder 11, and the combined signal S11 is transmitted via the band-pass filter (BPF) 12. The signal is wirelessly transmitted to the 16 QAM demodulation circuit 14 on the receiving side as a signal S7a.

The 16QAM demodulation circuit 14 on the receiving side receives the received signal S7b from the transmitting side, performs 16QAM demodulation on the QAM-modulated received signal S7b, and obtains an I / O signal obtained by demodulation.
The signal S14a and the Q signal S14b are converted to a Viterbi decoding circuit 2
Output to 2. As shown in FIG. 1, the 16QAM demodulation circuit 14 includes mixers 15a and 15b, a carrier regenerator 16, a hybrid unit 17, low-pass filters 18a and 18b,
It comprises A / D converters 19a and 19b.

In the 16QAM demodulation circuit 14, the received signal S
7b is divided into two systems, and mixers 15a, 15
b. One of the received signals S7a divided into two systems is multiplied by the reproduced carrier S16 from the carrier regenerator 9 by the mixer 15a, demodulated to the baseband, and
The I signal S14a is output to the Viterbi decoding circuit 22 via the PFs 18a and 19a. The other of the received signal S7a divided into two systems is a mixer 1ba, which outputs the reproduced carrier S
Hybrid circuit 17 with phase shifted by π / 2
, And demodulated to the base band, and passed through the LPFs 18b and 19b to the Q signal S1.
4b is output to the Viterbi decoding circuit 22. 16QA
I output from the M demodulation circuit 14 to the Viterbi decoding circuit 22
Usually, noise generated between transmission and reception is added to the signal S14a and the Q signal S14b. Viterbi decoding circuit 22
Receives the I signal S14a and the Q signal S14b from the 16QAM demodulation circuit 14, performs error correction / decoding on these signals, and generates a decoded signal S22.

As shown in FIG. 2, the Viterbi decoding circuit 22 includes a branch metric circuit 30, an ACS circuit 32, a path memory circuit 34, and a parallel / serial conversion circuit 36.
It consists of. The branch metric circuit 30 outputs the I signal S88a input from the 16QAM demodulation circuit 88 described above.
And selection signal S301a to S399a indicating a selected path selected from parallel paths for modulation points to which transmission signals can be assigned based on Q signal S88b and
Then, the branch metrics BM 301 b to 399 b for the determined selected path are output to the ACS circuit 4.

FIG. 3 shows a configuration diagram of the branch metric circuit 30 of this embodiment. As shown in FIG. 3, the branch metric circuit 30 includes a ROM block 200 and a register block 300. The branch metric circuit 30 receives the received I signal S14a, the received Q signal S14b, and the modulation scheme designation signal S100 from the 16QAM demodulation circuit 14, Selected path signals S301a to S399a and BMs 301b to 399b
To the ACS circuit 32.

The ROM block 200 stores R data corresponding to the combination of parallel paths shown in the trellis expression diagram of FIG.
OM201 to ROM299. ROM201
Receives a reception I signal S14a, a reception Q signal S14b of the reception signal S14, and a modulation scheme designation signal S100, operates a program corresponding to a modulation scheme recorded in advance according to the modulation scheme, and operates a parallel path. A selection path S201a to be selected according to the input is determined, and the square of the Euclidean distance between the modulation signal point corresponding to the selection path and the reception signal S14 is shown using a conversion table recorded in advance as conversion means. The branch metric BM is extracted and output to the register 301 as the BM 201b. In the present embodiment, as described above, the modulation method is the 16QAM modulation method, and a program according to the 16QAM modulation method operates in the ROM 201, and the following processing is performed.

Hereinafter, the ROM 201 will be described with reference to FIG.
3 is a trellis expression diagram of the convolutional coding circuit 2 described above. The ROM 201 includes a parallel path 80a that outputs the modulation signal points s0 and s8 in FIG.
８０80d, the following process is performed to determine a selection path, and a branch metric BM is extracted for a modulation signal point corresponding to the determined selection path using a pre-recorded conversion table, and the selection paths 201a and BM20 are extracted.
1b is output to the register 301. The conversion table recorded in the ROM 201 is information in a table format in which the Euclidean distance is determined using the received signal and the modulation signal point as parameters.

The ROM 202 has a path 8 composed of parallel paths for outputting modulated signal points s1 and s9 in FIG.
For each of 2a to 82d, the following process is performed to determine the selected path S202a, and a branch metric BM for a modulation signal point corresponding to the determined selected path is extracted by using a pre-recorded conversion table. 202
a and the BM 202b are output to the register 302. The ROM 203 stores the modulated signal point s in FIG.
2. Output s10. Path 84a composed of parallel paths
As for the ROMs 201 and 202 described above, the following processing is performed to determine the selection paths S203a and BM 203b, and these are output to the register 303. ROM 204 to ROM 299 are also the ROM 2 described above.
Similarly to 01 to 203, processing is performed on a path formed by a combination of predetermined parallel paths.

FIGS. 4 (A), (B), and FIG.
ROM 201, 202, 2 in the modulation method, respectively
FIG. 3 is a diagram for explaining the concept of processing in FIG. RO
In M201, as shown in FIG. 4A, the IQ plane is divided by a boundary line n passing through the modulation points s4, s10, and s12.
With respect to the boundary line segment n, the s8 side is defined as a region II, and the s0 side is defined as a region I. At this time, the reception I signal S14a of the reception signal S14
And the reception coordinates (I,
When Q) exists in the region I, the following relationship holds geometrically. (Euclidean distance between reception coordinates and modulation point s8) ≧ (Euclidean distance between reception coordinates and modulation point s0) On the other hand, when reception coordinates (I, Q) exist in region II,
Geometrically (Euclidean distance between reception coordinates and modulation point s8) ≤ (Euclidean distance between reception coordinates and modulation point s0) Therefore, when reception signal S14 exists in region I,
The selection path S201a indicates the modulation point s0, and when in the area II, the selection path S201a indicates the modulation point s8.

In the ROM 202, as shown in FIG. 4B, when the reception coordinates (I, Q) exist in the area I, the following geometrically holds. (Euclidean distance between reception coordinates and modulation point s9) ≧ (Euclidean distance between reception coordinates and modulation point s1) On the other hand, when reception coordinates (I, Q) exist in region II,
Geometrically (Euclidean distance between reception coordinates and modulation point s9) ≤ (Euclidean distance between reception coordinates and modulation point s1) Therefore, when reception signal S14 exists in region I,
The selection path S202a indicates the modulation point s1, and when in the area II, the selection path S202a indicates the modulation point s9.

In the ROM 203, when the reception coordinates (I, Q) exist in the area I as shown in FIG. (Euclidean distance between reception coordinates and modulation point s10) ≧ (Euclidean distance between reception coordinates and modulation point s2) On the other hand, when reception coordinates (I, Q) exist in region II,
Geometrically (Euclidean distance between reception coordinates and modulation point s10) ≤ (Euclidean distance between reception coordinates and modulation point s2) Therefore, when reception signal S14 exists in region I,
The selection path S203a indicates the modulation point s2, and when in the area II, the selection path S203a indicates the modulation point s10.

A similar relationship holds for the ROMs 204 to 299 with respect to a path composed of a predetermined combination of parallel paths.

The ROM for the 16QAM modulation method will be described below.
The processing in 201 will be described. FIG. 6 shows a flowchart of the processing in the ROM 201. Step S1: The ROM 201 stores the 16QAM demodulation circuit 1
4 to the I signal S14a and the Q signal S of the reception signal S14.
Enter 14b. Step S2: The ROM 201 determines whether the reception coordinates (I, Q) indicated by the I signal S14a and the Q signal S14b input in step S1 exist in the area I on the IQ plane in FIG. Then, when it is determined that the image does not exist in the region I, the process of step S3 described below is executed, and when it is determined that the image does not exist in the region I, the process of step S6 described below is executed. Step S3: The ROM 201 determines a path that outputs the signal point s0 as a selected path. Step S4: The ROM 201 extracts the Euclidean distance between the reception coordinates (I, Q) recorded in the conversion table and the signal point s0 determined in step S3.

Step S6: On the other hand, the ROM 201 determines a path for outputting the signal point s8 as a selected path. Step S7: The ROM 201 extracts the Euclidean distance between the received coordinates (I, Q) recorded in the conversion table and the signal point s8 determined in step S6. Step S5: The ROM 201 stores the selected path determined in step S3 or step S6 and step S4.
Alternatively, the Euclidean distance extracted from the conversion table in step S7 is calculated by using the selected path S201a and the BM
The data is output to the register 301 as 201b.

The ROMs 202 and 203 are also shown in FIG.
(B) The same processing as that of the ROM 201 described above with reference to FIG. 5 is performed. The same applies to the ROMs 204 to 299. The processing in the ROMs 201 to 299 described above is performed in parallel, respectively, and the selection paths S201a to S201a
99a and BMs 201b to 299b are output to registers 301 to 399, respectively.

The registers 301 to 399 correspond to the above-described RO.
Selected paths S201a to S299a from M201 to M299,
And BMs 201b to 299b are inputted, and these are temporarily recorded, and the selected paths are respectively selected S301a to S399.
a and the BMs 301b to 399b are output to the ACS circuit 32.

In the ACS circuit 32, the selected paths S301a to S399a input from the branch metric circuit 30
And, based on the BMs 301b to 399b, the sum with each state metric is obtained, the branch with the minimum sum is selected as the maximum likelihood branch, the path memory circuit 34 is controlled, and this minimum sum is set as a new state metric. I do. Under the control of the ACS circuit 32, the path memory circuit 34 sequentially records the selected paths, stores a predetermined number of paths, obtains a maximum likelihood path sequence, and outputs the parallel data to the parallel-serial conversion circuit 8. I do. The parallel-serial conversion circuit 8 outputs the maximum likelihood path S from the path memory circuit 6.
34 is input as parallel data, converted into serial data, and output as the maximum likelihood path S22.

Further, the branch metric circuit 30
A program corresponding to the PSK modulation method and the like and a conversion table are recorded in the OMs 201 to 299 in addition to the program corresponding to the QAM modulation method, and the selected path and the branch are selected using the program and the conversion table corresponding to the contents of the modulation method designation signal S100. Determine the metric.

As described above, in the Viterbi decoding device 22 of the present embodiment, the branch metric circuit 30 determines the selected path based on the contents programmed in advance, and executes the ACS.
Output to the circuit 32. Therefore, in the ACS circuit 32,
It is not necessary to determine the selected path, and the processing time of the ACS circuit 32 can be reduced, and the circuit scale can be simplified and reduced. Further, the branch metric of the selected path is extracted from the conversion table having the Euclidean distance calculated in advance as information according to the coordinates indicated by the reception I signal S14a and the reception Q signal S14b. Therefore, when determining the selection path, the selection path can be determined without calculating and comparing the Euclidean distance for each parallel path, and the processing time of the branch metric circuit 30 can be reduced, and the circuit scale can be simplified and reduced. . In the branch metric circuit 30, the processing in the ROMs 201 to 299 is performed in parallel, so that the processing time can be significantly reduced. Further, the branch metric circuit 30 can perform processing according to various communication systems using the same circuit.

Next, a second embodiment will be described. The configurations of the transmission / reception system, the Viterbi decoding device, and the branch metric circuit of the present embodiment are basically the same as those of FIGS. 1, 2 and 3 of the above-described first embodiment.
The transmission signal is transmitted after 32QAM modulation.

In this case, there are four parallel paths in the trellis transition of the convolutional coding circuit 2, and the selected path signal has two bits. The ROM 201 of the branch metric circuit of this embodiment stores, for example, output signal points s0, s8, s
16 and s24, the selected path is determined for the four parallel paths that output the signal S2 and the branch metric BM
Is calculated. In the present embodiment, the modulation method is 32QAM
The modulation system designation signal S100 is 32Q
The AM modulation method is specified. At this time, as shown in FIG. 7A, a boundary line segment n is determined, and the IQ plane is set in the regions I to IV.
Is divided into four areas, and the reception coordinates (I, Q) of the reception signal
, The same processing as that of the ROM 201 of the above-described first embodiment is performed.

More specifically, the reception coordinates (I, Q) are in the region I
S0 is selected as the selection path, and the Euclidean distance between the reception coordinates and the modulation point s0 is set as the branch metric BM. Also, the reception coordinates (I, Q) are in the area II
S8 is selected as the selection path, and the Euclidean distance between the reception coordinates and the modulation point s8 is set as the branch metric BM. Also, the reception coordinates (I, Q) are in the area II
If it exists in I, select s16 as the selection path,
The Euclidean distance between the reception coordinates and the modulation point s16 is defined as a branch metric BM. Further, the reception coordinates (I, Q)
Exists in the region IV, s24 is selected as a selection path, and the Euclidean distance between the reception coordinates and the modulation point s24 is set as a branch metric BM.

The ROM 202 determines areas I to IV as shown in FIG. 7B, and outputs signal points s1 and s1, respectively.
For the four parallel paths that output the signal S2 indicating s9, s17, and s25, the selection path is determined and the branch metric BM is calculated in the same manner as in the ROM 201 described above.
The ROMs 203 to 299 are also the ROMs described above.
Signals S each indicating a predetermined output signal point similarly to 201
ROM2 described above for the four parallel paths that output
As in the case of 01, the selection path is determined and the branch metric BM is calculated.

As described above, the branch metric circuit of the Viterbi decoding apparatus according to the present embodiment can obtain the same effect as that of the branch metric circuit 30 according to the above-described first embodiment with respect to a received signal based on the 32QAM modulation method.

[0048]

According to the Viterbi decoding method and apparatus of the present invention, the handling of parallel paths can be simplified. Further, according to the present invention, the calculation processing of the Euclidean distance can be simplified. Further, according to the present invention, for each combination of parallel paths, the process of determining the selected path and the branch metric can be parallelized. As a result, according to the present invention, it is possible to increase the speed of the arithmetic processing, simplify and reduce the circuit scale. According to the present invention, Viterbi decoding corresponding to various modulation schemes can be performed using the same circuit configuration.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a transmission / reception system according to a first embodiment.

FIG. 2 is a configuration diagram of a Viterbi decoding device according to a first embodiment.

FIG. 3 is a configuration diagram of a branch metric circuit according to the first embodiment.

FIG. 4 is a diagram for explaining processing in a ROM according to the first embodiment;

FIG. 5 is a diagram for explaining processing in the ROM of the first embodiment.

FIG. 6 is a flowchart of a process in a ROM of the first embodiment.

FIG. 7 is a diagram for explaining processing in the ROM of the second embodiment.

FIG. 8 is a configuration diagram of a conventional convolutional encoding circuit.

FIG. 9 is a diagram for explaining signal points of the 16QAM modulation scheme.

FIG. 10 is a trellis expression diagram used for encoding in a convolutional encoding circuit.

[Explanation of symbols]

 2 Convolutional coding circuit 4 Signal allocation circuit 7 16 QAM modulation circuit 8a, 8b, 15a, 15b Mixer 9 Local oscillator 10, 17 Hybrid device 11 ..Adder 12 ... Band pass filter 16 ... Carrier regenerator 18a, 18b ... Low pass filter 19a, 19b ... A / D converter 22 ... Viterbi decoding device 30 ... Branch Metric circuit 32 ACS circuit 34 Path memory 36 Parallel-serial conversion circuit 200 ROM block 201-299 ROM 300 Register block 301-399 Register

Claims (8)

(57) [Claims] 1. A performs branch metric calculation on the received signal being modulated, in the Viterbi decoding <br/> apparatus for determining a maximum likelihood path, the circuit for calculating the branch metric, the modulation method of parallel paths exist state of the reception signal being modulated, and, on the basis of the condition defined by the predetermined said modulation method, comprising means for determining a selected path from the parallel path, and Viterbi decoding based on said selected path The means for determining the selected path comprises:
For the signal point corresponding to the path,
Pre-programmed to determine the
The based on the content, Viterbi decoding apparatus for determining a selected path. 2. The circuit for calculating the branch metric has means for determining the selected path corresponding to each of a plurality of sets of parallel paths, and the means for determining each selected path determines the selected path. 2. The Viterbi decoding device according to claim 1, wherein the decoding is performed simultaneously and in parallel. 3. The means for determining a selected path is configured to determine the selected path according to a plurality of predetermined modulation methods, and determines the selected path according to a specified modulation method. The Viterbi decoding device according to claim 1. 4. The circuit according to claim 1, wherein the distance is a Euclidean distance, and the circuit for calculating the branch metric stores a Euclidean distance using the received signal as a parameter for a signal point in advance and outputs a Euclidean distance corresponding to the parameter. The Viterbi decoding device according to claim 1, further comprising a conversion unit. 5. The Viterbi decoding device according to claim 1, wherein said received signal is a convolutional coded signal. 6. The Viterbi decoding apparatus according to claim 5, wherein said convolutional coded signal is a trellis coded signal. 7. A selected path is selected from the parallel paths based on a state of a received signal modulated by a modulation method having a parallel path and a predetermined condition defined by the modulation method. The Viterbi decoding is performed based on the content pre-programmed to select the parallel path having the shortest distance for the signal point corresponding to the received signal and each parallel path. Method. 8. The Viterbi decoding method according to claim 7, wherein a selected path is determined simultaneously and in parallel for each set of parallel paths.