JPH09307598A - Viterbi decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration in the case of conducting Viterbi decoding by obtaining a sum of 1st and 2nd multiples obtained from I and Q signals and setting an assumed signal point to both ends of a dynamic range of an A/D converter. SOLUTION: In the case that an A/D converter with a dynamic range expressed by a range between assumed signal points processes a digital signal in 4-bit, four signal points (Sii, Siq) to be assumed are required. An I signal obtained from an input terminal 201 is fed to a multiplier 203 and a Q signal obtained from an input terminal 202 is inverted by a bit inverter 204 and the inverted signal is fed to a multiplier 205, and the signals are respectively multiplied at each multiplier. Then the products from the multipliers 203, 205 are summed by an adder 206 and the result of sum is outputted from an output terminal 207 as Euclid distance data. Similarly the square Euclid distance for other three points is obtained by applying/eliminating the bit inversion circuit to/from the systems of the Q and I signals. Thus, the square Euclid distance is simply obtained by calculating the bit inversion operation only.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for performing branch metric calculation in the case of performing Viterbi decoding, and more particularly, a square Euclidean distance calculation between a received signal point representing a likelihood in branch metric calculation and an assumed signal point. Regarding how to do.

[0002]

2. Description of the Related Art In a communication path with a severe power limitation, an error correction code is generally used to obtain a coding gain to reduce the power. In such a system, it is common to perform convolutional coding on the transmitting side and Viterbi decoding on the receiving side. As a modulation method in this case, a trellis-coded modulation method in which the modulation method and the coding method are combined has attracted attention.

In this trellis coded modulation system,
Input data is convolutionally coded, and this convolutional code is assigned to modulation signal points so that the Euclidean distance is maximized. Then, on the receiving side, decoding is performed using the Viterbi algorithm.

As a concrete trellis modulation method, for example, coded QPSK, coded 8PSK, coded 16QA
M, coded 32QAM, coded 64QAM, etc. are known. FIG. 5 shows an example of the configuration of a transmitting device in the case of using coded 16QAM.

In the transmitter 10 of FIG. 5, the input digital data is convolutionally coded in the convolutional coding circuit 1 and output to the signal allocation circuit 2 as a parallel convolutional code. The signal allocation circuit 2 allocates the input parallel convolutional code to a predetermined signal point, generates an I signal and a Q signal corresponding to the signal point, and outputs the I signal and the Q signal to the 16QAM modulation circuit 9.

In the 16QAM modulation circuit 9, the I signal and the Q signal output from the signal allocation circuit 2 are input to the multipliers 3 and 4, respectively. The multiplier 3 outputs the carrier wave output from the local oscillation circuit 5 to 90 by the hybrid (HB) circuit 6.
The multiplied carrier wave is multiplied by the I signal, and the multiplier 4 multiplies the carrier wave output by the local oscillation circuit 5 by the Q signal.

The adder 7 adds the outputs of the multipliers 3 and 4 and outputs the result to a bandpass filter (BPF) 8. The bandpass filter 8 removes an unnecessary band component from the input signal and then outputs it to the transmission path.

FIG. 6 shows a configuration example of the convolutional coding circuit 1.
Represents. As shown in the figure, in this example, the
5 bit digital data (x_Five, X_Four,
x_Three, X _Two, X₁) Is 6-bit digital data
(Y_Five, Y_Four, Y_Three, Y_Two, Y₁, Y₀) Is encoded in
It has been made. Input 5-bit data
(X_Five, X _Four, X_Three, X_Two, X₁) Is output as is.
Digital data (y_Five, Y_Four, Y_Three, Y_Two, Y₁, Y₀)
Upper 5 bits of data (y_Five, Y_Four, Y_Three, Y_Two, Y
₁) Is said. Lower 1 bit y of output digital data₀
Is the lower 2 bits (x_Two, X₁)
Is generated from.

That is, x ₁ is added by the adder 14 to the output y ₀ held 3 clocks earlier in the register 11 and held in the register 12 at the next clock. The data held in the register 12 is added by the adder 15 to x ₂ supplied at the next clock, and the addition output is
It is held in the register 13 at the next clock. Register 1
The data held in 3 is output as y ₀ at the next clock and is held in the register 11.

FIG. 7 shows an example of the configuration of a receiving device that receives the signal output from the transmitting device 10 of FIG. 5 to the transmission path. In the receiving device 20, the signal input from the transmission path is separated into two signals, which are input to the multipliers 31 and 32 of the 16QAM demodulation circuit 30, respectively. Multiplier 3
Reference numeral 1 multiplies the reproduced carrier generated by the carrier reproducing circuit 33 by the carrier delayed by 90 degrees in the hybrid circuit 34 and the input signal. The multiplier 32 multiplies the reproduced carrier wave output from the carrier wave recovery circuit 33 by the signal input from the transmission path. As a result, the received signal is demodulated into a baseband signal.

A low-pass filter (LPF) 35 removes unnecessary high frequency components from the output of the multiplier 31 and outputs the analog / analog signal.
It is output to a digital converter (hereinafter referred to as A / D converter) 37. The A / D converter 37 converts the input signal into an A / D signal.
It is converted and output to the Viterbi decoder 39 as an I signal. Similarly, the output of the multiplier 32 is the output of the low-pass filter 36.
After removing unnecessary high-frequency components, the A / D converter 3
A / D conversion by 8 and Viterbi decoder 3 as Q signal
9 is output.

The I and Q signals output from the A / D converters 37 and 38 are supplied to the carrier wave reproducing circuit 33, which reproduces a carrier wave from the I and Q signals. Output.

The Viterbi decoder 39 corrects an error generated on the transmission path, decodes correct data, and outputs it to a circuit (not shown).

FIG. 8 shows a configuration example of the Viterbi decoder 39. The I and Q signals output from the A / D converters 37 and 38 of the 16QAM demodulation circuit 30 are input to the branch metric calculation circuit 51. The branch metric calculation circuit 51 obtains a squared Euclidean distance between a signal point of a modulation scheme assumed for each subset (a hypothetical signal point) and a received signal point specified by the I signal and the Q signal.
Such an operation is performed for each subset, and the minimum value of the squared Euclidean distances in each subset is obtained. This is used as a branch metric in the subset, and the subsequent arithmetic circuit (ACS (Add, Com
(pare, Select) circuit) 52.

The ACS circuit 52 calculates the maximum likelihood path from the input branch metrics of each subset. Based on the control from the ACS circuit 52, the path memory 53 stores the decoded path for a predetermined number of stages, and finally stores A
The content of the maximum likelihood pulse obtained by the CS circuit 52 is output.

Parallel / serial (P / S) conversion circuit 5
4 converts the parallel data obtained by the path memory 53 into serial data and outputs the serial data.

FIG. 9 shows a branch metric operation circuit 51.
2 shows a configuration example of a circuit that calculates a branch metric of one subset in FIG. As shown in FIG.
The signal and the Q signal are input to N squared Euclidean distance arithmetic circuits 61-1 to 61-N. When the convolutional encoding circuit 1 is configured as shown in FIG. 6, 16Q
In the case of AM, each subset includes two signal points (hypothetical signal points), so the number of N is set to 2.
In case of 32QAM or 64QAM, the number of N is 4
Or it is set to 8.

Each squared Euclidean distance calculation circuit 61-i
Computes the squared Euclidean distance between the corresponding hypothetical signal point and the received signal point determined by the I and Q signals,
It is output to the minimum value calculation circuit 62. Minimum value calculation circuit 62
Selects the smallest one from the input N squared Euclidean distances, and uses this as the branch metric,
Output to the ACS circuit 52.

FIG. 10 shows a configuration example of the squared Euclidean distance calculation circuit 61-1 shown in FIG. In this example, the subtractor 71 subtracts the I component Sii at the assumed signal point from the input I signal. Subtractor 71
Output (I-Sii) is divided into two data and input to the multiplier 73. That is, since two identical signals are input to the multiplier 73, the multiplier 73 eventually calculates the squared value (I-Sii) ² of the output (I-Sii) of the multiplier 71.

Similarly, the subtractor 72 outputs the difference (Q-Siq) between the Q signal and the Q component Siq at the assumed signal point. This output (Q-Siq) is divided into two data, and the multiplier 74
Is input to The multiplier 74 multiplies the input data by each other and outputs (Q-Siq) ² .

The adder 75 adds the outputs of the multipliers 73 and 74 and outputs this as the squared Euclidean distance.
That is, the output of the adder 75 is as follows.

[0022]

[Equation 1] (I-Sii) ² + (Q-Siq) ²

[0023]

In the conventional squared Euclidean distance calculation, the multipliers 73 and 74 are used to calculate the squared Euclidean distance as described above. As a result, the structure becomes complicated, the circuit scale becomes large, and the cost becomes high.

The present invention has been made in view of the above points, and it is possible to simplify the configuration for performing this type of Viterbi decoding, reduce the circuit scale, and reduce the cost.

[0025]

In order to solve this problem, the present invention supposes that the branch metric operation is the sum of absolute value operations by quantizing the multiplicand of the squaring circuit by 1 bit. By arranging the signal points to be operated at both ends of the dynamic range of the A / D converter, the absolute value operation can be performed only by the bit inversion operation.

By carrying out such processing, a multiplier is not required when the branch metric is obtained, and
The absolute value calculation can be realized only by the bit inversion operation, and the circuit scale can be reduced.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to the accompanying drawings.

First, FIG. 1 shows the overall configuration of a Viterbi decoder to which this example is applied. The structure will be described below. In this example, the signal is a Viterbi decoder that receives and processes a QPSK-modulated signal.
The received signal obtained in 1 is supplied to the quadrature demodulator 102,
The I component and the Q component, which are quadrature-modulated in the received signal, are separated. The I signal demodulated by the quadrature demodulator 102 is supplied to the A / D converter 103 to be a digital I signal. The Q signal demodulated by the quadrature demodulator 102 is supplied to the A / D converter 104 to be a digital Q signal. In both A / D converters 103 and 104, the assumed signal points are converted into digital signals with a dynamic range.

Then, the digital I signal and the digital Q signal output from the A / D converters 103 and 104 are supplied to the branch metric operation circuit 105, which outputs the digital I signal and Q signal. Received signal points R (I, Q) and N assumed signal points S
Calculate N likelihoods with i (Sii, Siq). Here, i = 0 to N−1, N changes depending on the code used. Then, the likelihood calculation result is output as a branch metric in each subset. Details of the branch metric calculation circuit 105 will be described later.

Then, the branch metric operation circuit 10
The branch metric calculated in 5 is supplied to the arithmetic circuit (hereinafter referred to as ACS circuit) 106 at the subsequent stage. This A
The CS circuit 106 calculates the maximum likelihood path from each input subset. The path memory 107 is ACS
Under the control of the circuit 106, the decoded paths are stored for a predetermined number of stages, and finally the contents of the maximum likelihood path obtained by the ACS circuit 106 are output.

If necessary, the output of the path memory 107 is converted from parallel data to serial data by a parallel / serial conversion circuit (not shown).

FIG. 2 shows a branch metric operation circuit 10.
5A and 5B, the digital I signal and the digital Q signal are denoted by 103a and 104a in the A / D converter 10 respectively.
3 and 104 show the terminals output from this terminal.
The digital I signal and the digital Q signal obtained at 3a and 104a are the squared Euclidean distance calculation circuit 105a,
105b, ..., 105n. In this case, the first
The squared Euclidean distance calculation circuit 105a calculates the squared Euclidean distance between the digital I signal and the digital Q signal and the first signal point, and the second squared Euclidean distance calculation circuit 105b calculates the digital I signal and the digital I signal. The squared Euclidean distance between the Q signal and the second signal point is calculated, and the squared Euclidean distance between each signal point is calculated in this order. Then, each squared Euclidean distance calculation circuit 105
.. 105n is supplied to the ACS circuit 106 as a branch metric output of the branch metric operation circuit 105.

FIG. 3 is a diagram showing the configuration of the squared Euclidean distance arithmetic circuits 105a, 105b, ... 105n of this example. Here, the assumed signal points are set as the dynamic range, and the A / D converters 103 and 104 are used. This is an example when a 4-bit digital signal is used. In the case of these 4 bits, 16 values from 0 to 15 are digitally converted,
The assumed signal points (Sii, Siq) are S0 (0, 0), S
1 (0,15), S2 (15,0), S3 (15,1)
It becomes 4 points of 5). In FIG. 3, the received signal point R
It shows a configuration for obtaining a squared Euclidean distance ED21 between a signal point S1 (0, 15) assumed to be (I, Q).

Describing the configuration, 201 is an input terminal for a digital I signal, and 202 is an input terminal for a digital Q signal. Digital I obtained at the input terminal 201
The signal is divided into two systems, and the divided signals of the respective systems are supplied to the multiplier 203 and multiplied. In this multiplication, the following equation is calculated.

[0035]

[Equation 2] Here, Sii is the I component of the assumed signal point.

The digital I signal obtained at the input terminal 202 is bit-inverted by the bit inversion circuit 204 and then
The signal is divided into two systems, and the signals of the respective divided systems are supplied to the multiplier 205 and multiplied. In this multiplication,
The following formula is calculated.

[0037]

(Equation 3) Here, Siq is the Q component of the assumed signal point. Also,
[￣] means bit inversion.

Then, the multiplication results of the multipliers 203 and 205 are added by the adder 206, and the addition result is output from the output terminal 207 as squared Euclidean distance data.

Here, the calculation of the squared Euclidean distance ED21 by the squared Euclidean distance arithmetic circuit of this example will be described. The signal point S1 (0,15) which is assumed to be the received signal point R (I, Q). ) And the squared Euclidean distance ED21 can be calculated by the following equation.

[0040]

Equation 4] ^{ED21 = (R-S1) 2} = (I-S1i) 2 + (Q-S1q) 2 = (I-0) 2 + (Q-15) 2 = (I- [0000]) 2 + (Q- [1111]) ² = I ² + ￣Q ² [0000] and [1111] are numerical values that represent 0 and 15 by a 4-bit binary number, respectively. In addition, Q is an inversion of each bit of Q.

Similarly, the squared Euclidean distance ED20 between the received signal point R (I, Q) and the assumed signal point S0 (0,0), and the squared Euclidean distance ED22 between the signal point S2 (15,0). , The squared Euclidean distance ED23 from the signal point S3 (15,15) is as follows.

[0042]

[Equation 5] ED20 = I ² + Q ² ED22 = ￣I ² + Q ² ED23 = ￣I ² + ￣Q ²

Therefore, the arithmetic circuit of the squared Euclidean distance ED20 can be constructed by removing the bit inverting circuit from the circuit of FIG. The arithmetic circuit of the squared Euclidean distance ED22 can be configured by moving the bit inversion circuit of the circuit of FIG. 3 to the I signal system (after the output terminal 201). Further, the arithmetic circuit of the squared Euclidean distance ED23 can be configured by providing the bit inversion circuit of the circuit of FIG. 3 in both the Q signal and I signal systems.

By calculating the squared Euclidean distance in this way, a subtracter is not required as compared with the conventional squared Euclidean distance calculation circuit (see FIG. 10), and the circuit structure can be simplified accordingly. Therefore, the configuration of the Viterbi decoder can be simplified.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the configuration of the squared Euclidean distance calculation circuit. The configuration around the squared Euclidean distance calculation circuit of this example (that is, the configurations of FIGS. 1 and 2).
Is the same as the configuration of the first embodiment described above, and the format of the received signal (that is, the signal obtained by receiving and demodulating the QPSK-modulated signal) is also the same as that of the first embodiment, and the A / D converter The same applies to the case where the assumed signal points are converted as a dynamic range when the signal is converted into a digital signal.

Explaining the configuration of the squared Euclidean distance arithmetic circuit shown in FIG. 4, 301 is an input terminal of a digital I signal, 302 is an input terminal of a digital Q signal, and each digital signal is a 4-bit A / D. Converter (Fig. 1
(Corresponding to the A / D converters 103 and 104 shown in FIG. 2).

The digital I signal obtained at the input terminal 301 is supplied to the adder 303. The digital Q signal obtained at the input terminal 302 is bit-inverted by the bit inversion circuit 304 and then supplied to the adder 303. Then, the adder 303 adds the digital I signal and the bit-inverted digital Q signal, and the addition result is output from the output terminal 305 as squared Euclidean distance data.

Here, the calculation of the squared Euclidean distance by the squared Euclidean distance arithmetic circuit of this example will be described. Here, the squared difference between the assumed received I signal and the I component of the assumed signal point is described. In calculating, the number of one bit input to the multiplier is set to 1, that is, I
The absolute value of the difference between the signal and the assumed signal point is used as the square calculation result. Specifically, instead of the operation of the [Formula 1] described in the conventional example, the operation of the following expression is performed.

[0049]

[Equation 6] | I-Sii | + | Q-Siq |

Explaining that the squared Euclidean distance is obtained by the calculation of this equation, as in the case of the first embodiment,
Signal point S1 (0, 1) which is assumed to be the reception signal point R (I, Q)
The calculation of the squared Euclidean distance ED21 with respect to (5) will be described below.
It was shown that S1i) ² becomes (I-0) ² . Also,
In the formula [5], it is shown that (Q-S1q) ² becomes (Q-0) ² . Here, since I and Q are positive numbers, the condition of the following equation is satisfied.

[0051]

[Equation 7] | I-Sii | = I | Q-Siq | = ￣Q

Therefore, in the second embodiment, although the multipliers 203 and 205 described in the first embodiment (FIG. 3) are omitted, similar calculation results can be obtained.

As described above, according to this example, the squared Euclidean distance can be calculated only by the bit inversion circuit and the adder, and the configuration can be further simplified as compared with the first example.

In each of the above-described embodiments, the process of receiving and demodulating a QPSK-modulated signal has been described, but it goes without saying that the present invention can be applied to the process of receiving a modulated signal of another system in which Viterbi decoding is performed.

[0055]

According to the Viterbi decoding method of the present invention, the squared Euclidean distance calculation can be realized by a simple calculation process, and good Viterbi decoding can be performed by the simple calculation process.

[Brief description of drawings]

FIG. 1 is a block diagram showing a Viterbi decoder according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a branch metric operation circuit used in the Viterbi decoder of the first embodiment.

FIG. 3 is a block diagram showing a squared Euclidean distance calculation circuit used in the Viterbi decoder of the first embodiment.

FIG. 4 is a block diagram showing a squared Euclidean distance arithmetic circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a transmission device.

6 is a block diagram showing a configuration example of a convolutional encoding circuit in FIG.

FIG. 7 is a block diagram illustrating a configuration example of a receiving device.

8 is a block diagram showing a configuration example of a Viterbi decoder shown in FIG. 7.

9 is a block diagram showing a configuration example of a branch metric arithmetic circuit of FIG.

10 is a block diagram showing a configuration example of the squared Euclidean distance calculation circuit of FIG.

[Explanation of symbols]

101 received signal input terminal, 102 quadrature demodulator, 10
3, 104 analog / digital converter (A / D converter), 105 branch metric arithmetic circuit, 105
105n 2 Euclidean distance arithmetic circuit, 106 arithmetic circuit (ACS circuit), 107 path memory, 201 digital I signal input terminal, 202
Digital Q signal input terminal, 203 multiplier, 204 bit inversion circuit, 205 multiplier, 206 adder, 20
7 Operation result output terminal, 301 Digital I signal input terminal, 302 Digital Q signal input terminal, 303 Adder, 304 bit inversion circuit, 305 Operation result output terminal

Claims (3)

[Claims] 1. An I / Q signal demodulated by an orthogonal demodulator is digitally converted by an analog / digital converter,
The converted digital I signal and Q signal are supplied to a squared Euclidean distance calculation circuit to calculate a squared Euclidean distance between a received signal point and a predetermined assumed signal point, and a branch metric is calculated from the minimum value of the squared Euclidean distance. In the Viterbi decoding method for obtaining the maximum likelihood path from the branch metric, the digital I signal for calculating the squared Euclidean distance is separated into one digital data and the other digital data, and the separated one The first multiplication value is obtained by multiplying the digital data and the other digital data, and the bit-inverted digital Q signal for calculating the squared Euclidean distance is separated into one digital data and the other digital data, and the separated. A second multiplication is performed by multiplying the one digital data and the other digital data. A Viterbi decoding method, wherein a value is obtained, an addition value of the first multiplication value and a second multiplication value is obtained, and the predetermined hypothetical signal points are arranged at both ends of a dynamic range of the analog / digital converter. . 2. An I / Q signal demodulated by the quadrature demodulator is digitally converted by an analog / digital converter,
The converted digital I signal and Q signal are supplied to a squared Euclidean distance calculation circuit to calculate a squared Euclidean distance between the received signal point and a predetermined assumed signal point, and a branch metric is calculated from the minimum value of the squared Euclidean distance. In the Viterbi decoding method for obtaining the maximum likelihood path from the branch metric while obtaining the maximum likelihood path, in calculating the squared Euclidean distance between the received signal point and a predetermined assumed signal point, the predetermined assumed signal point is converted into the analog / digital signal. A Viterbi decoding method, wherein the Viterbi decoding method is arranged at both ends of a dynamic range of a converter, and an absolute value of the digitally converted digital I signal and an inverted digital Q signal is obtained. 3. An I / Q signal demodulated by the quadrature demodulator is digitally converted by an analog / digital converter,
The converted digital I signal and Q signal are supplied to a squared Euclidean distance calculation circuit to calculate a squared Euclidean distance between a received signal point and a predetermined assumed signal point, and a branch metric is calculated from the minimum value of the squared Euclidean distance. In the Viterbi decoding method for obtaining the maximum likelihood path from the branch metric, the Viterbi decoding method for obtaining the squared Euclidean distance by adding the digitally converted digital I signal and the inverted digital Q signal .