JP2518355B2 - Coding modem circuit - Google Patents
Coding modem circuitInfo
- Publication number
- JP2518355B2 JP2518355B2 JP63154923A JP15492388A JP2518355B2 JP 2518355 B2 JP2518355 B2 JP 2518355B2 JP 63154923 A JP63154923 A JP 63154923A JP 15492388 A JP15492388 A JP 15492388A JP 2518355 B2 JP2518355 B2 JP 2518355B2
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- JP
- Japan
- Prior art keywords
- circuit
- signal
- bit
- code
- modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Error Detection And Correction (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は符号化変復調回路に関するものである。The present invention relates to a coding / modulation circuit.
（従来の技術） 従来、符号化変調方式ではｍビット（ｍ＝1,2,・・）
の入力は畳み込み符号回路によりｎビットの（ｎ＝1,2,
…）の冗長ビットが付加されて（ｍ＋ｎ）ビットに増加
し、符号速度を変えずに2n+mの多値数の変調方式を用い
ていた（G.Ungerboeck,“Trellis−Coded Modulation w
ith Redundant Signal Sets",IEEE Com.Mag.Feb.1987 p
p5−21）。この従来の符号化変調のブロック図を第３図
に示す。この図で、１は符号化回路、２は信号空間への
配置回路、３は変調回路、４は復調回路、５は復号回
路、６はクロック再生回路である。符号化変調方式は謝
り訂正と復変調技術を融合することにより信号空間上の
ユークリッド距離が最大になるようにシンボル単位で符
号化することにより、従来のハミング距離が最大になる
ように信号毎に符号化する謝り訂正よりも大きな符号化
利得を得ることができる。(Prior Art) Conventionally, m bits (m = 1, 2, ...) In the coded modulation method.
Input of n bits (n = 1,2,
...) redundant bits are added to increase the number to (m + n) bits, and a multilevel modulation method of 2 n + m is used without changing the code rate (G. Ungerboeck, “Trellis-Coded Modulation w
ith Redundant Signal Sets ", IEEE Com.Mag.Feb.1987 p
p5-21). A block diagram of this conventional coded modulation is shown in FIG. In this figure, 1 is an encoding circuit, 2 is an arrangement circuit in a signal space, 3 is a modulation circuit, 4 is a demodulation circuit, 5 is a decoding circuit, and 6 is a clock recovery circuit. The coded modulation method is a combination of apologetic correction and re-modulation technology, and by coding in symbol units so that the Euclidean distance in the signal space is maximized, the conventional Hamming distance is maximized for each signal. It is possible to obtain a larger coding gain than that of the apologetic correction for coding.
（発明が解決しようとする課題） しかし第４図の信号空間を示したｍ＝4,n＝１の例の
ように、16QAMから、符号化32QAMに多値数が増加し、信
号点間隔が約1/2になり所要C/Nの3dB程度の劣化につな
がり、符号化利得が大幅に減少していた。また、多値数
の増加にともない高精度のハードウェアが要求され実現
が困難になるという欠点もある。(Problems to be Solved by the Invention) However, as in the example of m = 4, n = 1 showing the signal space in FIG. 4, the multi-valued number increases from 16QAM to encoded 32QAM, and the signal point interval is It became about 1/2, which led to the deterioration of required C / N by about 3 dB, and the coding gain was significantly reduced. In addition, there is a drawback that high-precision hardware is required as the number of multivalues increases, which makes implementation difficult.
本発明の目的は、上述の多値数の増加にともなう符号
化利得の減少、ハードウェア実現の困難を解決し、大き
な符号化利得を得る符号化変復調回路を提供することに
ある。It is an object of the present invention to provide a coding modulation / demodulation circuit that solves the above-mentioned decrease in coding gain due to an increase in the number of multivalues, difficulty in hardware implementation, and obtains a large coding gain.
（課題を解決するための手段） 前記目的を達成するための本発明の特徴は、符号語間
の信号空間上でのユークリッド距離が最大になるように
シンボル単位で符号化する符号化変復調において、送信
側に、（ｍ＋ｎ）ビット系列（m,n＝1,2・・・・）で符
号速度1/Tの信号を入力とし、ｍビット系列で符号速度1
/T′（Ｔ′＝（m/（ｍ＋ｎ）・Ｔ）の高速化された信号
を出力とするスピード変換回路と、ｍビット系列の該ス
ピード変換回路の出力をクロック速度1/T′で符号化さ
れた（ｍ＋ｎ）ビット系列の信号を出力する符号回路
と、該符号回路の出力を符号語間の信号空間上でのユー
クリッド距離が最大となるように配置する回路を具備
し、受信側に、送信側からの（ｍ＋ｎ）ビット系列の信
号を入力してクロック速度1/T′で動作しｍビット系列
の復号信号を出力する復号回路と、該復号出力である符
号速度Ｔ′のｍビット信号系列を符号速度1/Tの（ｍ＋
ｎ）ビット信号系列へ変換するスピード変換回路を具備
する符号化変復調回路にある。(Means for Solving the Problem) A feature of the present invention for achieving the above-mentioned object is that in coding modulation / demodulation for coding in a symbol unit so that the Euclidean distance on a signal space between codewords becomes maximum, Input a signal of code rate 1 / T in (m + n) bit sequence (m, n = 1,2 ...) to the transmitting side, and code rate 1 in m bit sequence.
/ T '(T' = (m / (m + n) · T) speed conversion circuit that outputs a speeded up signal and the output of the m-bit series speed conversion circuit is coded at the clock speed 1 / T ' The receiving side is provided with a coding circuit that outputs a signal of a converted (m + n) bit sequence, and a circuit that arranges the output of the coding circuit so that the Euclidean distance between the code words in the signal space is maximized. , A decoding circuit which receives a signal of (m + n) bit sequence from the transmitting side and operates at a clock speed of 1 / T 'to output a decoded signal of m bit sequence, and m bits of a code speed T'which is the decoded output Signal sequence is code rate 1 / T (m +
n) An encoding modulation / demodulation circuit provided with a speed conversion circuit for converting into a bit signal sequence.
（作用） 本発明は、変復調器の多値数を増大せずに符号化変調
を行なうことで大きな符号化利得を得ることを特徴とす
る。符号化変調において、符号化を行なうことにより付
加される冗長ビットによる必要伝送速度の増加を、伝送
のクロック速度を上げることによって補う。従来技術で
はこれを多値数の増加によって補っていた。このとき信
号点間隔が狭まり所要C/N値が増大する。本発明による
と帯域幅が拡大するが、それによる所要C/N値の劣化は
ごくわずかであり、多値数を上げることによって劣化す
る量より小さく結果として大きな符号化利得を得るもの
である。(Operation) The present invention is characterized in that a large coding gain is obtained by performing the code modulation without increasing the multi-level number of the modulator / demodulator. In the coded modulation, the increase in the required transmission rate due to the redundant bit added by performing the coding is compensated by increasing the transmission clock rate. In the prior art, this was compensated for by increasing the number of multivalues. At this time, the signal point interval becomes narrow and the required C / N value increases. According to the present invention, the bandwidth is expanded, but the required C / N value is degraded only slightly, and a large coding gain is obtained as a result, which is smaller than the amount degraded by increasing the number of multiple values.
しかも、送信側のスピード変換回路が（ｍ＋ｎ）ビッ
トからｍビットへと入力より少ないパスとして符号化後
のパスが入力と同じになるように、また、受信側のスピ
ード変換回路がｍビットから（ｍ＋ｎ）ビットへと入力
より多いパスとして出力されるパスが復号前の入力と同
じになるように構成しているため、従来の一般的な符号
器及び複合器をそのまま使用できる。Moreover, the speed conversion circuit on the transmission side makes the path after encoding as the path smaller than the input from (m + n) bits to m bits, and the speed conversion circuit on the reception side changes from m bits ( Since the paths output to (m + n) bits as more paths than the inputs are the same as the inputs before decoding, conventional general encoders and compounders can be used as they are.
（実施例） 第１図は本発明の実施例であって１はスピード変換回
路、２は符号化回路、３は信号空間への配置回路、４は
変調回路、５は復調回路、６は符号回路、７はスピード
変換回路、8,9はスピード変換にともない必要になるク
ロック速度変換回路、10はクロック再生回路である。(Embodiment) FIG. 1 shows an embodiment of the present invention, in which 1 is a speed conversion circuit, 2 is an encoding circuit, 3 is an arrangement circuit in a signal space, 4 is a modulation circuit, 5 is a demodulation circuit, and 6 is a code. Reference numeral 7 is a speed conversion circuit, 8 and 9 are clock speed conversion circuits necessary for speed conversion, and 10 is a clock reproduction circuit.
例えばこの実施例において256QAMの変調回路を用いて
ｍ＝7,n＝１としたとき、同図中のＴとＴ′はＴ′＝7/8
Tの関係がある。符号器に畳み込み符号器、復号器にビ
タビ復号器を用いるときの例を考える。まず、送信側に
おいて８ビット/Tを７ビット/T′にスピード変換する
（Ｔ′＝m/（ｍ＋ｎ）・Ｔ）。この信号系列は畳み込み
符号回路により、冗長ビットが付加され８ビット/T′の
出力になる。この後256QAMの信号空間へユークリッド距
離の符号の関係を考慮したSet−Partitionとよばれる最
適配置回路を通り、変調される。尚、Set−Partitionは
文献「G.Ungerboeck,“Channel Coding with Multileve
l/Phase Signals",IEEE IT,Jan.1982 pp55−67」によ
る。受信側では、復調回路の出力をビタビ復号回路を通
し、７ビット/T′の信号系列を得る。これをスピード変
換回路を通し８ビット/Tの復調信号系列を得る。このよ
うにこの実施例では８ビット/Tの信号系列に符号化を施
しても256QAM変調を用いて伝送できる。また第１図の破
線で示す部分はスピード変換回路と符号化変調回路及
び、スピード変換回路と符号化変調回路であり、これら
はそれぞれ一体化が可能である。For example, in this embodiment, when a modulation circuit of 256QAM is used and m = 7 and n = 1, T and T'in the figure are T '= 7/8.
There is a T relationship. Consider an example in which a convolutional encoder is used as the encoder and a Viterbi decoder is used as the decoder. First, the transmission side performs speed conversion from 8 bits / T to 7 bits / T '(T' = m / (m + n) .T). A redundant bit is added to this signal sequence by a convolutional code circuit to produce an output of 8 bits / T '. After that, the signal is modulated into a 256QAM signal space through an optimal placement circuit called Set-Partition that takes into account the relationship of the Euclidean distance code. Note that Set-Partition is described in the document “G. Ungerboeck,“ Channel Coding with Multileve
l / Phase Signals ", IEEE IT, Jan. 1982 pp 55-67". On the receiving side, the output of the demodulation circuit is passed through the Viterbi decoding circuit to obtain a 7-bit / T 'signal sequence. This is passed through a speed conversion circuit to obtain a demodulated signal sequence of 8 bits / T. As described above, in this embodiment, even if the 8-bit / T signal sequence is encoded, it can be transmitted using 256QAM modulation. Further, the portion shown by the broken line in FIG. 1 is a speed conversion circuit and a coding modulation circuit, and a speed conversion circuit and a coding modulation circuit, and these can be integrated respectively.
（発明の効果） 以上説明したように本発明により変復調の多値数を増
大させずに符号化変復調が行なえるので、信号点間の距
離が減少しない。これはｎ＝１のとき3dBの利得に相当
し、帯域拡大による劣化を考えても従来の符号化変調よ
り大きな符号化利得を得ることができる。またハードウ
ェアの実現も容易になる。しかも、送信側のスピード変
換回路が（ｍ＋ｎ）ビットからｍビットへと入力より少
ないパスとして符号化後のパスが入力と同じになるよう
に、また、受信側のスピード変換回路がｍビットから
（ｍ＋ｎ）ビットへと入力より多いパスとして出力され
るパスが復号前の入力と同じになるように構成している
ため、従来の一般的な符号器及び復号器をそのまま使用
できる。(Effect of the Invention) As described above, according to the present invention, coding modulation / demodulation can be performed without increasing the number of modulation / demodulation values, so that the distance between signal points does not decrease. This corresponds to a gain of 3 dB when n = 1, and a coding gain larger than that of the conventional coded modulation can be obtained even when considering deterioration due to band expansion. Also, the hardware can be easily realized. In addition, the speed conversion circuit on the transmission side makes the path after encoding as the path from (m + n) bits to m bits less than the input, and the speed conversion circuit on the reception side changes from m bits ( Since the paths output to (m + n) bits as more paths than the inputs are the same as the inputs before decoding, conventional general encoders and decoders can be used as they are.
本発明の有効性を確認するために計算機シミュレーシ
ョンの結果を第２図に示す。これは実施例のシミュレー
ションの結果である。この図で符号化512QAMは従来の技
術によるものであり、本発明による符号化変調（符号化
256QAM）では従来のものより2.4dB大きな利得がある。
これは多値数が増大しないことによる3dBから帯域拡大
による劣化0.6dBを引いた値である。この0.6dBはクロッ
クが8/7倍になり帯域も8/7倍になることにより求まる劣
化量である。なお、第２図の実線は符号化をしないとき
の理論値である。又、従来の512QAMと本発明の256QAMと
は伝送容量が同じである。FIG. 2 shows the result of computer simulation for confirming the effectiveness of the present invention. This is the result of the simulation of the example. In this figure, the coded 512 QAM is based on the conventional technology, and the coded modulation (coding
256QAM) has 2.4dB larger gain than the conventional one.
This is a value obtained by subtracting 0.6 dB of deterioration due to band expansion from 3 dB when the number of multiple values does not increase. This 0.6 dB is the amount of deterioration obtained when the clock becomes 8/7 times and the band becomes 8/7 times. The solid line in FIG. 2 is the theoretical value when no coding is performed. Further, the conventional 512QAM and the 256QAM of the present invention have the same transmission capacity.
第１図は本発明の実施例の符号化変調のブロック図であ
り本発明の特徴を最もよく表している。第２図は本発明
による効果を表すビット誤り率を従来のビット誤り率と
共に示す図である。第３図は従来の符号化変調のブロッ
ク図、第４図は従来の符号化変調を施したときに信号点
の間隔が減少することを示した図で16QAMと32QAMの平均
電力は同じである。 1;スピード変換回路、 2;符号化回路、 3;信号空間への配置回路、 4;変調回路、 5;復調回路、 6;復号回路、 7;スピード変換回路、 8,9;クロック速度変換回路、 10;クロック再生回路。FIG. 1 is a block diagram of coded modulation according to an embodiment of the present invention, and best shows the features of the present invention. FIG. 2 is a diagram showing the bit error rate showing the effect of the present invention together with the conventional bit error rate. FIG. 3 is a block diagram of conventional coded modulation, and FIG. 4 is a diagram showing that the interval between signal points decreases when conventional coded modulation is performed. The average power of 16QAM and 32QAM is the same. . 1; Speed conversion circuit, 2; Encoding circuit, 3; Arrangement circuit in signal space, 4; Modulation circuit, 5; Demodulation circuit, 6; Decoding circuit, 7; Speed conversion circuit, 8, 9; Clock speed conversion circuit , 10; Clock recovery circuit.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−39239（ＪＰ，Ａ) 特開 昭63−39240（ＪＰ，Ａ) 特開 平２−113754（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-39239 (JP, A) JP-A-63-39240 (JP, A) JP-A-2-113754 (JP, A)
Claims (1)
離が最大になるようにシンボル単位で符号化する符号化
変復調回路において、 送信側に、（ｍ＋ｎ）ビット系列（m,n＝1,2,・・・
・）で符号速度1/Tの信号を入力とし、ｍビット系列で
符号速度1/T′（Ｔ′＝（m/（ｍ＋ｎ））・Ｔ）の高速
化された信号を出力とするスピード変換回路と、ｍビッ
ト系列の該スピード変換回路の出力をクロック速度1/
T′で符号化された（ｍ＋ｎ）ビット系列の信号を出力
する符号回路と、該符号回路の出力を符号語間の信号空
間上でのユークリッド距離が最大となるように設置する
回路を具備し、 受信側に、送信側からの（ｍ＋ｎ）ビット系列の信号を
入力してクロック速度1/T′で動作しｍビット系列の復
号信号を出力する復号回路と、該復号出力である符号速
度Ｔ′のｍビット信号系列を符号速度1/Tの（ｍ＋ｎ）
ビット信号系列へ変換するスピード変換回路を具備する
ことを特徴とする符号化変復調回路。1. An encoding modulation / demodulation circuit for encoding in symbol units so that the Euclidean distance between codewords in a signal space is maximized, and an (m + n) bit sequence (m, n = 1, 1) is provided on the transmission side. 2, ...
・) The speed conversion that inputs the signal of code rate 1 / T and outputs the speeded up signal of the code rate 1 / T ′ (T ′ = (m / (m + n)) · T) in the m-bit sequence. Circuit and the output of the m-bit series speed converter circuit at clock speed 1 /
A code circuit for outputting a signal of (m + n) bit sequence encoded by T ', and a circuit for setting the output of the code circuit so that the Euclidean distance between the code words in the signal space is maximized are provided. , A decoding circuit for inputting an (m + n) -bit sequence signal from the transmission side to the receiving side, operating at a clock speed of 1 / T ', and outputting an m-bit sequence decoded signal, and a code rate T which is the decoded output 'M-bit signal sequence is (m + n) at code rate 1 / T
An encoding modulation / demodulation circuit comprising a speed conversion circuit for converting a bit signal sequence.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63154923A JP2518355B2 (en) | 1988-06-24 | 1988-06-24 | Coding modem circuit |
| US07/357,573 US4993046A (en) | 1988-06-24 | 1989-05-26 | Coded modulation communication system |
| CA000603849A CA1297159C (en) | 1988-06-24 | 1989-06-23 | Coded modulation communication system |
| EP89401793A EP0348305B1 (en) | 1988-06-24 | 1989-06-23 | Coded modulation communication system |
| DE68918010T DE68918010T2 (en) | 1988-06-24 | 1989-06-23 | Coded modulation transmission system. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63154923A JP2518355B2 (en) | 1988-06-24 | 1988-06-24 | Coding modem circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH025627A JPH025627A (en) | 1990-01-10 |
| JP2518355B2 true JP2518355B2 (en) | 1996-07-24 |
Family
ID=15594904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63154923A Expired - Fee Related JP2518355B2 (en) | 1988-06-24 | 1988-06-24 | Coding modem circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2518355B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07288479A (en) * | 1994-04-18 | 1995-10-31 | Nec Corp | Error correction concatenate coding method/device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6339239A (en) * | 1986-08-05 | 1988-02-19 | Fujitsu Ltd | Encoing, modulating and demodulating circuit |
| JPS6339240A (en) * | 1986-08-05 | 1988-02-19 | Fujitsu Ltd | Encoding and modulating circuit |
-
1988
- 1988-06-24 JP JP63154923A patent/JP2518355B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025627A (en) | 1990-01-10 |
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