JPS6359119A - Calculation circuit for branch metric of viterbi decoder - Google Patents

Abstract

PURPOSE:To provide flexible countermeasure at a high speed operation by providing a phase uncertainty eliminating circuit, a pi/2 phase shift circuit, a ROM group and an inverter. CONSTITUTION:The ROM group 8a outputs to branch metrics lambdai(0). lambdai(1), lambda', lambda'' depending on an even or an odd number of the phase uncertainly and selects the branches by using the LSB 10 of a control signal and an exclusive OR gate 11 and the selected signal 12 is outputted to an output terminal 13 and the inverter 14. The inverter 14 inverts each bit component of the input signal 12 and outputs the inverted signal 15 to an output terminal 13. On the other hand, the pi/2 phase shift circuit 9 rotates the bit pattern of the input signal 7 by pi/2 phase and supplies it to the ROM group 8b. Thus, 8 ways of branch metrics have an output.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a method for receiving signals when a transmission signal encoded by a convolutional encoder is transmitted via a PSK modulator and demodulated by a PSK demodulator. This invention relates to an improvement of the technical metric calculation circuit in a Viterbi decoder that performs error correction on demodulated signals.

[Conventional technology]

Conventionally, there has been a circuit of this type as shown in the block diagram of FIG. In the figure, 1 is a multi-value demodulated signal input terminal obtained by a soft decision method, 2 is a multi-value demodulated signal, and 8 is a continuous M/2 address input terminal for the multi-value demodulated signal 2.
ROM group storing the technique metrics of the street, 21 is the technique metric read out from the ROM group 8 and whose phase uncertainty has not been removed, 22 is the phase uncertainty consisting of M/2 circuits. FIG. 3 is a block diagram showing the detailed configuration of one circuit in the phase uncertainty removal circuit group. In the figure, 31 is a selector that selects one from M/2 technique metrics according to the control signal 4, 32 is a branch metric that includes phase uncertainty in the O-π direction, and 14 is an inverter. , 34 is a technique metric in which each bit component of the branch metric 32 is inverted, 33 is a selector that selects one of the two branch metrics according to the control signal 4, and 12 is a selector with perfect phase uncertainty. 15 is a branch metric whose bit component is inverted, and 13 is an output terminal.

Next, the operation will be explained. In M-phase PSK demodulation, M branch metrics are calculated from the multilevel demodulated signal demodulated using the soft decision method. FIG. 4 shows transmitted signals 401 to 40B, received signals 411, and branch metrics 421 to 428 at time i when M=8, and the transmitted signals are αi
(m) (m = 0, 1, 2.

..., 7), let the received signal be di, turn on at times i, i-1゜i-2, respectively, + ′it-+ + Xl-2
When transmitting , the transition probability P that 11 becomes the received signal is expressed by the following formula % Formula % When the logarithm of P is taken, it becomes a linear function of d2 (e).

Here, di'' (9) is the square of the Euclidean distance between the received signal 7 and the transmitted signal Ai (b).

By the way, di” (2) J=lZ'i-kui(ro))12- (Z
pt ast (m)) ” + (Zqi-aq+(
rn+) ”-l Zi l” +Es-2(Zi,
ii(m)), =・(31here12'il"±Zp♂
10Z□2...(4) ES-II i(m
)l”xa,,”(ml+a,4”fml・
...(5)-(7i, Q l &ll1) ”Z
1111 api (m) ” Z @i a a((
``l, =・(6), so 1nP is a linear function of only the inner product of 2i and ku1 ((2).If the technique metric is λ, then r', <a 17g= + Xt-
+ + i&-t) fossa-(71,kui-)/E
It can be defined as s mi λ i (b) (7).

Here, Therefore, in 8-phase PSK, the technical metrics 421 to 428 of the received signal are expressed as follows.

M/2 consecutive branch metrics λ'i(0), λ' are written by the multi-level signal 2.
1(1), ..., λ'1(--1)21 are successively displayed,
It is input to the phase uncertainty removal circuit group 22.

In FIG. 3, the M/2 technique metrics 21 including phase uncertainties input to the selector 31 are determined by the lower (j!ogzM1) bits of the control signal 4, The phase uncertainty other than 0 is removed, and the remaining uncertainty in the O−π direction is also removed using the most significant bit of the control signal 4 in the 0 selector 33, which is input to the inverter 14 and the selector 33. , outputs branch metrics from which the phase uncertainty of the received signal that occurs during carrier regeneration has been completely removed to the output terminal 13, and simultaneously outputs these branch metrics to the inverter 14.
The zero inverter 14 outputs the remaining M/2 skill metrics to the output terminal 13 based on the relationship of the αφ equation.

[Problem that the invention seeks to solve]

Since the conventional metric calculation circuit of this type of Viterbi decoder is configured as described above, M/2 ROMs are required.
After reading out the technique metric, the phase uncertainty must be removed, and for phase uncertainty removal, M/
It is necessary to prepare a large number of selectors and inverters that select one of the two technique metrics, and a selector that selects one of the two technique metrics. Also, the delay time is large, and the control signal and There were problems such as the need for many latches during high-speed operation.

This invention was made to solve the above-mentioned problems, and it is possible to configure a phase uncertainty removal circuit without increasing the circuit scale, has low delay time, and has flexibility in handling high-speed operation. The purpose of this study is to obtain a technical metric calculation circuit for a Viterbi decoder.

[Means for solving problems]

The branch metric calculation circuit of the Viterbi decoder according to the present invention removes the phase uncertainty included in the received signal at the time of the multi-level demodulated signal, and from the multi-level demodulated signal from which the phase uncertainty has been removed, λ1 (0), .

[Effect]

The technical metric calculation circuit of the Viterbi decoder in this invention removes the phase uncertainty of the received signal at the time of the multi-level soft decision signal based on the control signal, but the required circuit is reduced and the delay time is reduced. At the same time, the scale of the hardware constituting the circuit is also reduced.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 shows a technical metric calculation circuit of a Viterbi decoder according to an embodiment of the present invention, here M-8 or 8
0 indicating the configuration of the technique metric calculation circuit in phase PSK
In the figure, 1, 2, 3, 4, 12, 13, 14, 15 are exactly the same as the conventional ones, 5 is the control signal input from the outside, excluding the LSB, and 6 is the control signal input from the outside. M/4
7 is a multilevel demodulated signal from which phase uncertainty has been removed, and ga and 3b are R each consisting of M/2 ROMs.
OM group, 9 is a π/2 phase shift circuit that rotates the phase of this multilevel demodulated signal 7 by π/2, 10 is the LSB of the control signal
, 11 is an exclusive OR gate, 16 is an inverter for inverting the LSBIO of the control signal, and 17 is an OR circuit.

Next, the operation will be explained.

In FIG. 1, a multilevel demodulated signal 2 inputted from an input terminal 1 is processed by a phase uncertainty removal circuit group 6 based on the information of a signal 5 excluding the LSB of a control signal inputted from an input terminal 3. The bit pattern is converted so that the phase uncertainty shown in FIG. 5 is completely removed when the number is even, and remains "1" when the number is odd. The converted signal 7 is output to the ROM group 9 and the π/2 phase shift circuit 9. ROM#0°R in 110M group 8a, 8b
OM#3 stores the values of λ1 (0) and λth 1) of the αΦ formula, ROM#1 stores the values of λ, and ROM#2 stores the values of λ"-- (-Z”p
cos22.5°+Z ”q 5in22.5”
) -u口However"'p=rcos (-□10)Z"q-rsi
n (−−+θ).

rt = z pt + z qt p The value of is stored.

In the ROM group 8a, the phase uncertainty is as shown in FIG. 5(a).

(C1, (el, (g)) and Fig. 5 (
bl, (d), (f).

When the odd number is shown in (h), the corresponding branch metrics λ1(0), λ1(1), λ゛, λ'' are outputted, respectively, and the LSB of the control signal 10 and the exclusive OR gate 11 are used. The selected signal 12 is output to the output terminal 13 and the inverter 14.The inverter 13 inverts each bit component of the input signal 12 and outputs the inverted signal 15 to the output terminal 12.

On the other hand, the π/2 phase shift circuit 9 rotates the bit pattern of the input signal 7 by π/2 phase, and transfers it to the ROM group 8b.
Output to. The following sequence is the same as the above sequence.

With the above, eight types of branch metrics can be output.

Note that the circuit used in the present invention uses an exclusive OR gate to select the branch metric when the phase uncertainty is even or odd; A selector may also be used to achieve the same effect as in the above embodiment.

〔Effect of the invention〕

As described above, according to the branch metric calculation circuit of the Viterbi decoder according to the present invention, the phase uncertainty of the received signal is removed by converting the focus pattern of the multilevel demodulated signal. This has the effect that a circuit with a simple circuit configuration can be made at low cost, and that superior performance such as a reduction in delay time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a branch metric calculation circuit of a Viterbi decoder according to an embodiment of the present invention, FIG. 2 is a block diagram showing a branch metric calculation circuit of a conventional Viterbi decoder, and FIG. 3 is a block diagram showing a branch metric calculation circuit of a conventional Viterbi decoder. 4 is a diagram showing the relationship between the ideal received signal and the technique metric in the case of 8-phase PSK, and FIG. 5 is a detailed block diagram of the phase uncertainty removal circuit in 8-phase PSK.
FIG. 8 is a diagram showing eight phase uncertainties for K; In the figure, 1 is a multilevel demodulated signal input terminal, 2 is a multilevel demodulated signal, 3 is a control signal input terminal, 4 is a control signal, and 5 is an LS
6 is a phase uncertainty removal circuit; 7 is a multilevel demodulated signal from which phase uncertainty has been removed; 3a and 3b are ROM groups in which technique metrics are stored; 9 is a multilevel demodulated signal is a π/2 phase shift circuit, 10 is the LSB of the control signal, 11 is an exclusive OR gate, 12 is a branch metric of λ1(0) to λ1(3), 13 is an output terminal, and 14 is a The inverter 15 is a branch metric of λ1(4) to λ1(7). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A multi-level demodulated signal obtained by demodulating an M-phase PSK modulated signal with a synchronous detection means employing a soft-decision method is input, and the phase indicated by the multi-level soft-decision demodulated signal is input from an external control signal input terminal. Based on the input control signal, the phase is shifted to the 0th phase that does not include phase uncertainty, or to any phase from this phase to the continuous (M/4-1) phase to eliminate the phase uncertainty. a π/2 phase shift circuit that rotates the phase of the multilevel demodulated signal from which the phase uncertainty has been removed by π/2, and the phase uncertainty removal circuit and π/2 a group of ROMs storing branch metrics that are relative values of Euclidean distances between each output signal of the phase shift circuit and expected received signals of consecutive M/2 phases from which phase uncertainties have been removed; A branch metric calculation circuit for a Viterbi decoder, comprising M/2 inverters for inverting each bit component of a branch metric output from the group.