KR100228474B1 - Bm calculator of viterbi encoder - Google Patents

Abstract

The present invention relates to a decoder for correcting an error generated in a digital communication channel. The present invention relates to calculating a giro evaluation amount between received data and each encoded symbol in a Viterbi decoder used in a trellis coded modulation. It relates to a device for.

The giro evaluation amount calculating apparatus of the present invention calculates a giro evaluation amount between each symbol after being encoded with the received data. Or The circuit is configured to output the Euclidean distance as many as N symbol rats.

Description

Giro evaluation device of Viterbi decoder

1 is a block diagram of a conventional Viterbi decoder used in a trellis coded modulation scheme.

2 is a block diagram of a Viterbi decoder of the present invention used in a trellis coded modulation scheme.

3 is a concrete block diagram of the evaluation apparatus of FIG.

The present invention relates to a decoder for correcting an error occurring in a digital communication channel, and in particular, between a data received in a Viterbi decoder used in a Trellis Coded Modulation method and each symbol encoded. The present invention relates to an apparatus for calculating a giro evaluation amount.

A block diagram of a Viterbi decoder which decodes received data by performing an evaluation amount calculation between the data received by the Viterbi decoder and the encoded symbols is shown in FIG.

Referring to FIG. 1, when data modulated by a transmitter and wirelessly transmitted are received by a demodulator 100 of a receiver, the demodulator 100 performs data demodulation and outputs the I component and Q component analog signals separately. do. Analog signals separated by I and Q components are converted into digital data by first and second ADCs (Analog to Digital Converters 110 and 111). Each of the A / D-converted I and Q component digital data is used as an address of a Giro evaluation amount lookup table. For example, the address is composed of 6 bits. The A / D converted I-component digital data has addresses A6 to A11, and the A / D converted Q-component digital data has addresses A0 to A5. Therefore, the I component digital data output from the first ADC 110 has the address bit A6 being the least significant bit (LSB) of the ADC 110, and the Q component digital data output from the second ADC 111 has the address bit A0 having the same value. It becomes the least significant bit (LSB) of the ADC 111.

The Gero metric lookup table is implemented on the first and second ROMs 120 and 121. In the first ROM 120, a high order branch metric look up table is implemented, and in the second ROM 121, A low order branch metric look up table is implemented.

Based on the addresses provided by the first and second ADCs 110 and 111, among the giro evaluation amounts and sector numbers previously stored in the first and second ROMs 120 and 121, the corresponding giro evaluation amounts BM and sector number SECTOR Provided to Trellis Decoder 130. The trellis decoder 130 decodes the data received from these giro evaluation amounts BM and the sector number SECTOR using a Viterbi decoding algorithm.

In the Viterbi decoder of FIG. 1, the circuit for decoding the received data is complicated by performing a square root operation by calculating a giro evaluation using a lookup table method using a memory such as a ROM. It became complicated.

Accordingly, an object of the present invention is to provide a giro evaluation amount calculating apparatus capable of high-speed processing by calculating a giro evaluation amount without using a look-up table in a Viterbi decoder used in a lattice encoding modulation method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The Viterbi decoding algorithm is one of convolutional candidate decoding methods and is a decoding algorithm that minimizes a decoding error when symbols occur with equal probability. The Viterbi algorithm using Euclidean distance is the Euclidean distance. To minimize.

Where r _i is the received signal sequence and υ _i is the received sequence.

The Euclidine distance calculation is performed by the giro evaluation unit calculating unit 220, which is the first step of the decoder, the formula is as shown in Equation (1).

[Equation 1]

… … … … (One)

Here, X _c and Y _c represent I and Q coordinate values for each signal point in the signal space, and X _i and Y _i are coordinate values for the received data.

When the Euclidean distance ED of the data received by Equation (1) is determined, the Euclidine distance ED finds the smallest giro in each state in the trellis, and this branch becomes a survival path.

The circuit which implements the above equation (1) for the giro evaluation of the received data is very complicated, and in the present invention, since it is not the actual Euclidine distance but the relative comparison that is needed to find the optimal path on the real Trellis, Use an approximation value for the estimate. Therefore, a formula for calculating a squared Euclidean distance (SED), such as the following Equation (2), can be used for the calculation of the giro evaluation.

[Equation 2]

… … … (2)

In this case, since there is no need to implement a square root operator as in the prior art, hardware complexity is reduced, and by configuring and using a dedicated logic circuit for the square operation, the circuit can be optimized.

The dedicated logic circuit used for the square operation is disclosed in detail in patent 92-27557 filed December 31, 1992.

In addition, if the circuit is configured to use the following equation (3), the hardware required for the configuration of the giro evaluation amount computing device can be significantly reduced.

[Equation 3]

… … … (3)

In the case of equation (3), only the implementation of the additive subtraction is required in the actual hardware configuration, so the hardware complexity is higher than that of the Euclidean distance ED in equation (1) or the squared Euclidean distance SED in equation (2). It will be considerably reduced.

In the present invention, the evaluation amount calculating device is implemented in the same manner as the above equations (2) and (3).

FIG. 2 is a Viterbi decoder of the present invention for use in a trellis coded modulation scheme, and includes a branch metric calculator 220 that implements Equation (2) and (3).

In FIG. 2, demodulator 200, first and second ADCs 210, 211 have the same configuration and operation according to the conventional Viterbi decoder of FIG.

The analog signal separated by the I and Q components in the demodulator 200 is then A / D converted by the ADCs 210 and 211 and input to the gyro evaluation unit 220 in the decoder. In this case, when the demodulator 200 is implemented as a digital circuit, the output of the demodulator 200 can be used immediately without the need for an analog to digital converter (ADC).

The branch evaluation apparatus 220 calculates and outputs the Euclidean distance between the received data and each signal point, and the output Euclidean distance is output as many as the number of symbols.

The configuration and operation of the giro evaluation amount calculating device 220 will be described with reference to FIGS. 3 (a) and 3 (b).

FIG. 3 (a) is the equation for evaluating the amount of giro (2) It is a block diagram for implementing

3 (b) is the equation for calculating the amount of giro (3) This is a block diagram for implementing.

The giro evaluation amount calculating device 220, which implements the calculation formula (2) of FIG. 3 (a), includes difference calculators 300 and 301 for calculating and outputting a difference between symbols and received data of I and Q components, respectively;

Square calculation circuits 310 and 311 for square operation of the difference between the received data output from the difference calculators 300 and 301, and

The adder 320 adds data output from the square calculating circuits 310 and 311 and outputs Euclidean distance as many as N symbols.

On the other hand, the giro evaluation amount calculating device 220 for implementing the calculation formula (3) of FIG.

Difference calculators 302 and 303 for calculating and outputting a difference between symbols of I and Q components and received data, respectively;

And an adder 321 that adds the difference between the I and Q component received data output from the difference calculators 302 and 303 and outputs a Euclidean distance.

In FIG. 3 (a), the A / D-converted I and Q components calculate the difference between each symbol and the received data in the difference calculators 300 and 301, and are squared in the square calculation circuits 310 to 311. After the operation, each component is added by the adder 320 to output the Euclidine distance as many as the number of n symbols.

Therefore, the value output from the adder 320 is calculated by the formula (2).

To satisfy.

In FIG. 3 (b), all operations are the same except for the square calculating circuits 310 and 311 in FIG. 3 (a).

Therefore, the value output from the adder 321 is calculated by equation (3).

To satisfy.

As described above, the present invention relates to a Viterbi decoder used in a Trellis-Coded Modulation method, which comprises a giro evaluation apparatus that does not use a lookup table method using a memory or the like. Euclidean distance with all symbols can be processed at high speed simultaneously. In addition, by constructing a giro evaluation unit that does not require square root calculation, it has the effect of reducing the size of the hardware required for the implementation.

Claims (4)

In the apparatus for calculating the giro evaluation of a Viterbi decoder used in a trellis coded modulation method, first and second order calculators for calculating a difference between a symbol and received data of I and Q components, respectively, and the first and second differences. A first and second square calculators that square the difference output from the calculator, and an adder that adds data output from the first and second square calculators and outputs a Euclidine distance value equal to a predetermined number of symbols. Jiro evaluation amount computing device characterized in that the configuration. The method of claim 1, wherein the Euclidine distance value of the predetermined number of symbols in the giro evaluation unit is calculated. Giro evaluation amount calculation device, characterized in that calculated by. In the apparatus for calculating the giro evaluation of a Viterbi decoder used in a trellis coded modulation method, first and second difference calculators for calculating a difference between a symbol and received data of I and Q components, respectively, and the first and second differences. And an adder for adding the differences output from the calculator and outputting Euclidine distance values of a predetermined number of symbols. The euclidine distance value of the predetermined number of symbols is calculated by the giro evaluation apparatus. Giro evaluation amount calculation device, characterized in that calculated by.