JPH01198846A - Successive decoder - Google Patents

Abstract

PURPOSE:To remove the discrepancy of a demodulation reference phase within a short time by reducing the number of a buffer address after a first reset and executing a second reset and onward when the reduced buffer overflows. CONSTITUTION:When the buffer 2 of a reception signal overflows due to the discrepancy of the demodulation reference phase and a control circuit 44 executes the first reset to remove this discrepancy, a decoding processing part 4 reduces the number of the address of the buffer 2 of the reception signal thereafter and repeats the reset by the overflow of the reduced buffer. Thus, the discrepancy of the demodulation reference phase can be removed within a short time and the number of the reception signals to be abandoned in resetting is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a successive decoding device, and more particularly to a successive decoding device that performs error correction decoding of convolutional codes transmitted through an orthogonal modulation transmission path.

[Conventional technology]

In order to detect and correct data transmission errors, the data is divided into several information symbols, convolutionally encoded into code symbols by an error correction encoder, and the transmitted code symbols are passed to an error correction decoder (hereinafter referred to as decoding). Sequential decoding is performed using the fan algorithm in

Such an error correction encoder includes a state holding circuit and a function generation circuit. The state holding circuit is composed of, for example, a shift register, holds an internal state, and changes the internal state by inputting an information symbol. A function generator receives internal states and generates code symbols.

The received signal (hard decision) received by the decoder corresponding to one code symbol does not necessarily match the transmitted code symbol due to transmission errors.

Assuming that the decoder proceeds with decoding coded symbol by symbol,
It has a circuit (hereinafter referred to as an encoder replica) that has the same function as the corresponding error correction encoder, and inputs all possible information symbols to each encoder replica each time a received signal corresponding to one code symbol is received. Each of the code symbols output by the encoder replica at the time is compared with the received received signal and the information symbol that gives the code symbol closest to the received signal is estimated to be the information symbol that was sent. A likelihood called the Fan likelihood is used as a measure of closeness. The fan algorithm basically determines that the information symbol string with the largest cumulative fan likelihood is the sent information symbol string.

However, if transmission errors occur frequently, there is a possibility that an incorrect information symbol will be determined to be the information symbol that was sent. - Once an incorrect decision is made, the internal state of the encoder copy will be different from the internal state of the error correction encoder, and from then on, even if you try to find an information symbol with a large fan likelihood, you will not be able to find it. It is possible to detect erroneous judgments. When an incorrect determination is detected, the internal state of the encoder replica is returned to the past state, and then it is determined that the information symbol that was sent was the information symbol with the next largest fan likelihood after the information symbol selected in the past. and try decrypting again. Even if an attempt is made to find the information symbol with the next highest fan likelihood, if it cannot be found because it has already been searched, the process returns to the previous state and performs the same operation. In this way, decryption is performed by repeating trial and error,
- Since the decoding result once output may be changed later, the decoder requires a buffer for the input received signal and a buffer for the decoding result.

The fan algorithm explained above is based on American fans (R
, M., Fano), and was published by IEEE
Transactions on information
ation Theory, IT-9 (1963) (US) P, 64-74. Further, the error correction encoder and decoder as described above are developed by, for example, American Joe 9 DeHitt Forney e Jr. (George D.
avid Forney, Jr.) U.S. Patent Nos. 3 and 6
65,396.

Now, in transmission systems such as digital microwave communication systems where the spectrum width in the carrier band is severely limited, quadrature modulation methods such as quadrature phase modulation and 16-value quadrature amplitude modulation are often used.

When a code symbol is transmitted in a transmission system using an orthogonal modulation method, each bit constituting the code symbol is divided into two, and each bit group T, , T, is made to correspond to each orthogonal component of the orthogonal modulation signal. The well-known method 4 is used to demodulate orthogonal modulation signals.
There is phase phase uncertainty, and the phase of the reference carrier wave of the demodulator (demodulation reference phase) differs from the phase of the carrier wave of the modulator every 90 degrees, so that even if there is no transmission error, the two bit groups output from the demodulator (Hard decision of) R, , R, may not match the bit group T, , TQ. (R,,R,) is (T,.

T,) or (bottom:,T,) or C-1 ■) or (
T9. T, ). Therefore, (R,,R
,) does not match ('r,,'r,), it is detected and R,,Rq T
, ,T, must match. R,,R,is T,,
If it does not match Tq, the received signal (hard decision) (R,,R,) contains an error with a very high probability,
Since decoding does not progress in the decoder and the buffer of the received signal overflows, a mismatch can be detected.

A conventional sequential decoding device that includes a phase shift circuit and decodes convolutional codes transmitted through an orthogonal modulation transmission path uses the phase shift circuit to perform logical operations on a trial-and-error basis each time a received signal buffer overflows. If such trial and error is repeated up to three times, the discrepancy in the demodulation reference phase can be definitely removed. Note that when an overflow occurs due to a discrepancy in the demodulation reference phase, all received signals stored in the buffer must be discarded.

[Problem to be solved by the invention]

As explained above, in the conventional sequential decoding device, it is necessary to repeat the buffer overflow of the received signal up to three times before removing the discrepancy in the demodulation reference phase, which takes a long time and causes errors during this time. There are drawbacks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a successive decoding device that can remove demodulation reference phase discrepancies in a short time.

[Means to solve the problem]

The successive decoding device of the present invention transmits and demodulates a modulated signal that has been orthogonally modulated using code symbols of a convolutional code, and demodulates a first received signal obtained by demodulating it using four-phase phase uncertainty under the control of a control signal. demodulation reference phase conversion means for performing a logical operation on a trial-and-error basis to remove a discrepancy in the reference phase and outputting the result of the logical operation as a second received signal; and a predetermined first number of said second received signals. received signal storage means capable of storing;
a decoding result storage means capable of storing the first number of decoding results of the second received signal;
At the same time, the decoding results already written are sequentially read out from the decoding result storage means and outputted to the outside, and one of the received signals read from the received signal storage means is sequentially written to the received signal storage means. When the decoding of the second received signal is completed, the decoding result is written into the decoding result storage means, and at the same time, the second received signal written next to the second received signal whose decoding has just been completed is written from the received signal storage means. If the second received signal is read out and attempted to be decoded, and the previous decoding is considered to be erroneous and the decoding is to be performed backwards, the second received signal is written before the second received signal read immediately before from the received signal storage means. At the same time as reading out the second received signal that is currently being read out, the decoding result that was written in the decoding result storage means when the decoding of the second received signal that is currently being read out is read out and the decoding is redone; If the decoding is delayed until the oldest second received signal written in the signal storage means cannot be decoded, and it is determined that there is an error in the logical operation of the demodulation reference phase shift means, the control signal causes the demodulation reference to be changed. The phase conversion means is controlled to redo the logic operation, and then a reset operation is performed to read out the second received signal newly written in the received signal storage means and attempt to decode it, and after this reset operation, the decoding is completed. The decoding does not proceed until the number of the second received signals reaches a predetermined second number, and the first decoding signal is The reset is performed each time it is determined that there is a mistake in the logic operation of the demodulation reference phase changing means because decoding is delayed until the second received signal written a third number earlier than the third number is read out and an attempt is made to decode it. and a sequential decoding processing means that repeats the operation.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a sequential decoding device of the present invention.

In the embodiment shown in FIG. 1, the coding rate is 3/4 and the number of convolutional code symbols, each code symbol consisting of 4 bits, is 16.
Each of the two hard-decision signals is transmitted by a value-orthogonal amplitude modulation transmission system, and is output by a demodulator (not shown) at the receiving end.
This is a sequential decoding device that decodes a bit-parallel received signal D Pi I D ql. A pair of received signals D pl +
A parallel 4-bit received signal consisting of Dml corresponds to one code symbol.

1 is a phase switching circuit, which is controlled by a control signal B1,
Received signal D el l D ql as received signal D
p2 r D @2, or logically manipulate the received signal D , , D, , so that the demodulation reference phase of the demodulator is rotated by 90 degrees, 180 degrees, or 270 degrees, and the received signal D p ! Output as r D ql. 2 is a RAM for buffering received signals, and has a storage capacity of 4 bits×n words. 3 is a RAM for buffering the decoding results, and has a storage capacity of 3 bits×n words. 4 is a decoding processing unit, which reads out the received signal written in the RAM 2, sequentially decodes it, and writes the decoding result into the ROM 3; The decoding processing unit 4 has counters 41 and 42 . Selector 43. It is composed of a control circuit 44 and a decoding circuit 45. The counter 41 has a count output of the maximum value (n-1
) and returns to 0, and outputs an address signal A1 and a control signal B5, which are count outputs. counter 42
is a similar counter and outputs an address signal A2 and a control signal B7. Selector 43 selects either address signal A1 or A2 under the control of control signal B6 and outputs it to RAM 2.3. The control circuit 44 is
The control signal B1 controls the logical operation of the phase shift circuit 1, and the output of the selector 43 and control signals B2 and B3 control the writing and reading of the RAM 2.3. The decoding circuit 45 performs decoding processing on the received signal according to the control signal B4. Note that the clock signal OL input to the counter 41 is equal to the received signal, 1°Dl, (as well as D-2,
This is a clock synchronized with D-2).

When the phase-shifted received signal is input, the counter 41 counts the clock signal CL and increases the address signal A1 by one. At this time, the control circuit 44 responds to the control signal B5 from the counter 41 and outputs the control signal B2. Output B3 and B6.

Selector 43 outputs address signal A1 in response to control signal B6. The RAM 2 responds to the control signal B2 and writes the received signal D p2 p D ql to the address A1, and the RAM 3 responds to the control signal B3 and reads out the decoding result E written to the address A1 and outputs it to the outside.

On the other hand, the address signal A2 indicates the address of the RAM 2 in which the received signal currently being decoded by the decoding circuit 45 is written. When the decoding circuit 45 completes the decoding of the received signal D1 read from the RAMI immediately before, the decoding circuit 45 outputs a control signal B4 notifying the completion of decoding. Control circuit 44 responds to control signal B4 and outputs control signals B2 . B3. Output B6 and B7.

The selector 43 selects the address signal A in response to the control signal B6.
Output 2. The decoding result D2 is written to the address A2 of the RAM 3 under the control of the control signal B3. counter 4
2 increases address signal A2 by one in response to control signal B7 from control circuit 44. And the counter 43 is
In response to the control signal B6, it outputs the address A2 which was recently incremented by one. Furthermore, the decoding circuit 45 receives the control signal B2
Under the control of , the next received signal is newly read out from the address A2 increased by one in the RAM 2, and this received signal is decoded. Since the decoding processing cycle is sufficiently shorter than the cycle of the clock signal CL, if the decoding progresses smoothly, address A2 will catch up with address A1, and the latest received signal written to RAM2 will be decoded and no further reading will be possible. Since there is no more received signal to output, the value of address signal A2 becomes address signal A1.
When the value becomes equal to the value, the control circuit 44 outputs the control signal B4. Then, the decoding circuit 45 temporarily stops the decoding process in response to the control signal B4. When decrypting backwards,
The control circuit 44 receives control signals B2°B3. Output B6 and B7. Counter 42 decrements address signal A2 by one in response to control signal B7. The selector 43 responds to the control signal B6 and outputs the address A2 that was decreased immediately before.

The decoding circuit 45 receives the control signal B2. In response to B3, RAM
The received signal (previously decoded) and the decoded result are read from address A2 of 2.3 and the decoding is performed again. In this way, the decoding circuit 45 sequentially decodes the received signals.

The received signal (address is A2-1) written immediately before the received signal (address in RAM2 is A2) read from RAM2 just before is rewritten by the newly input received signal (this write address is AI). In other words, if the decoding is delayed until A2-1=AI, the received signal that has not been decoded will be rewritten by the next newly input received signal. Therefore, the control circuit 44 controls A2-1=
When it becomes AI, it is determined that RAM2 has overflowed. When the control circuit 44 determines that the demodulation reference positions of the demodulators are misaligned due to the occurrence of overflow, it outputs control signals B1 and B7. phase switching circuit l
is the previously received signal D N r in response to the control signal B1.
The logic operation is reset so that the relative phase relationship between D 41 and the received signal D p2 + D Q2 advances by 90 degrees. For example, if up until now the received signal D p2 * D < 2 was equal to the received signal D PI # D Assuming that the phase is subjected to a logical operation equivalent to 270 degrees and about 6, from now on, the received signal D pi
* D ql is received signal D pt * D
Output as <2. After redoing this logical operation,
Counter 42 responds to control signal B7 and resets the value of address signal A2 to the value of address signal A1. The decoding circuit 45 reads out the received signal newly written to the RAM 2 and restarts decoding.

After performing the logical operation of the phase switching circuit 1 and the above-described resetting of the address signal A2, if decoding is delayed until the address signal A2 becomes smaller than the address signal A1 by the value n1, the control circuit 44 determines that the demodulation reference phase is still at the demodulation reference phase. Determine that there is a discrepancy and perform the above reset again. By repeating the reset a maximum of three times in this manner, the discrepancy in the demodulation reference phase can be definitely removed. Since decoding should proceed if the discrepancy in the demodulation reference phase is removed, the number of received signals for which decoding has been completed is counted after reset, and when this count reaches the value n2, the control circuit 44 changes the demodulation reference phase It is determined that the discrepancy has been removed, and no reset is performed thereafter until RAM2 overflows.

If the demodulation reference phases are different, decoding will be delayed rapidly, so by setting the value n2 appropriately, the value n1 can be changed to RA
Even if it is set considerably smaller than the number n of addresses in M2, a discrepancy in the demodulation reference phase after the first reset can be accurately detected.

For the second and subsequent resets, after the first reset, RAM2
This is equivalent to reducing the number of addresses in (n++1) and resetting the reduced RAM 2 when it overflows.

The operation of the embodiment shown in FIG. 1 has been described above.

If the embodiment shown in FIG. 1 is changed to, for example, a 2-bit soft decision, the decoding processing section 4 is changed to one for a 2-bit soft decision, and the input received signals, 1°D, and l are respectively Since 4 bits are parallelized, the number of processing bits of the phase shift circuit 1 and the number of bits per address of the RAM 2 can be changed accordingly.

Furthermore, if a 4-bit code symbol is transmitted using a transmission system using a 4-phase phase modulation method, the 4 bits of 1 code symbol are transmitted over 2 time slots of the modulated signal, so the number of bits in phase shift circuit 1 is It is necessary to add a serial converter between the phase shift circuit 1 and the RAM 2 to parallelize the received signals of the two time slots. This serial-to-parallel converter needs to perform serial-to-parallel conversion of the received signals of two time slots corresponding to one code symbol by code-synchronizing the received signal sequence, and this code synchronization also involves removing the discrepancy in the demodulation reference phase. Similarly, the decoding processing section performs the process by trial and error. This trial-and-error error is often detected by an overflow of RAM2, and in this case, R
In response to AM2 overflow, it is necessary to separately decide whether to perform a reset to remove the discrepancy in the demodulation reference phase or to perform an operation to reestablish code synchronization.

In the embodiment shown in FIG. 1, writing and reading are performed in RAM2 in units of one code symbol and in RAM3 in units of one information symbol.
It is also possible to change it to symbol units or 3 symbol units. In this case, the decoding processing unit 4 may decode two or three of the 4-bit code symbols as one symbol of the 8-bit or 12-bit code symbols, or the decoding processing unit 4 may A received signal intermediate buffer and a decoding result intermediate buffer each having a storage capacity of 2 or 3 symbols are added to RAM 2 . RAM3
It is also possible to exchange received signals and decoding results with the computer, and to perform decoding in units of one code symbol. In this way R.A.
M2. By accommodating a plurality of symbols in one address of the RAM 3, the degree of freedom in selecting RAM hardware increases.

There are also known decoding processing units that perform decoding not on a code symbol basis but on a bit-by-bit basis. The present invention can also be applied to cases where such codes are used.

〔Effect of the invention〕

As explained in detail above, in the sequential decoding device of the present invention, when the received signal buffer overflows due to a difference in the demodulation reference phase and an initial reset is performed to remove this difference, the received signal buffer is Since the number of addresses is reduced isometrically and reset is repeated by overflow of the reduced buffer, discrepancies in the demodulation reference phase can be eliminated in a short time, and the number of received signals discarded during reset can be reduced. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a sequential decoding device of the present invention. 1... Phase switching circuit, 2, 3... RA
M, 4...Decoding processing unit, 41.42...
・Counter, 43...Selector, 44...
...Control circuit, 45...Decoding circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A first received signal obtained by transmitting and demodulating a modulated signal quadrature-modulated with code symbols of a convolutional code is controlled by a control signal to obtain a demodulation reference phase due to four-phase phase uncertainty. demodulation reference phase shifting means for performing a logical operation by trial and error in order to remove the discrepancy between the two and outputting the result of the logical operation as a second received signal; and storing a predetermined first number of the second received signals. a decoding result storage means capable of storing the first number of decoding results of the second received signal; and a decoding result storage means capable of storing the first number of decoding results of the second received signal; At the same time as writing, the decoding results already written are sequentially read out from the decoding result storage means and outputted to the outside, and when the decoding of one of the second received signals read from the received signal storage means is completed, the decoding is performed. At the same time as writing the result into the decoding result storage means, the second received signal written next to the second received signal whose decoding has now been completed is stored in the received signal storage means.
When decoding is attempted by reading out the received signal of the second received signal read out from the received signal storage means and the decoding is to be performed backwards because there is a possibility of an error in the previous decoding, the second received signal written before the second received signal read immediately before from the received signal storage means is read out and decoded. At the same time as reading out the second received signal currently being read out, the decoding result written in the decoding result storage means is read out when the decoding of the second received signal to be read out is completed previously, and the decoding is redone. If the decoding is delayed until the oldest second received signal written in the storage means cannot be decoded, and it is determined that there is an error in the logical operation of the demodulation reference phase changing means, the demodulation reference phase is changed by the control signal. redoing the logical operation by controlling a conversion means;
Thereafter, a reset operation is performed to read and decode the second received signal newly written in the received signal storage means, and after this reset operation, the number of the second received signals that have been decoded reaches a predetermined number. The decoding does not progress until the number 2 is reached, and the second received signal, which is the latest one written in the received signal storage means, is written a third number earlier than the first number, which is predetermined in advance. and successive decoding processing means that repeats the reset operation every time it is determined that there is a mistake in the logical operation of the demodulation reference phase conversion means. Characteristic sequential decoding device.