JPH01132241A - Sequential decoding device - Google Patents

Abstract

PURPOSE:To shorten the repetitive period of the rerun of a code synchronization by reopening a decoding processing from a receiving signal written into the buffer of the receiving signal the fixed number of times before that time when the buffer overflows, it is judged that there is an error in the code synchronization and the code synchronization is rerun. CONSTITUTION:When a control circuit 34 judges that a RAM 1 overflows for the error of the code synchronization, it outputs control signals B3, B4 and B1. A counter 32 responds to the control signal B3 and resets an address signal A2 into a value smaller than an address A1. A decoding circuit 35 dislocated the phase of the code synchronization by one bit of the code symbol of a convolution code, reads a receiving signal D1 out of the address A2 of the RAM 1 by the control signal B1 and respons a decoding. Thus, the pull-in time of the code synchronization can be shortened.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a sequential decoding device.

[Conventional technology]

In order to detect and correct data transmission errors, the data is divided into several pieces of information, convolutionally encoded into code symbols by an error correction encoder, and the transmitted code symbols are processed by an error correction decoder (decoder). Sequential decoding using the fan algorithm has been carried out.

Such an error correction encoder includes a state holding circuit and a function generation circuit. The state holding circuit is composed of, for example, a shift register, holds an internal state, and changes the internal state by inputting an information symbol.

A function generator receives internal states and generates code symbols.

The received signal (hard decisions) received by the decoder corresponding to one code symbol does not necessarily match the delayed code symbol due to transmission errors.

Assuming that the decoder proceeds with decoding coded symbol by symbol,
It has a circuit (hereinafter referred to as an encoder replica) that has the same function as the corresponding error correction encoder, and inputs all possible information symbols to each encoder replica each time a received signal corresponding to one code is received. Each of the code symbols output by the encoder replica at the time is compared with the received received signal, and the information symbol that gives the received signal the closest code symbol is estimated to be the information symbol that was sent. A likelihood called Fano likelihood is used as a measure of closeness. The Fan algorithm basically determines that the information symbol/L4 sequence for which the cumulative Fano likelihood is the largest is the transmitted information symbol sequence.

However, if transmission errors occur frequently, there is a possibility that an incorrect information symbol will be determined to be the information symbol that was sent. - Once an incorrect judgment is made, the internal state of the encoder copy will be different from the internal state of the error correction encoder, and from then on, even if you try to find an information symbol with a large Fano likelihood, you will not be able to find it. It is possible to detect that an incorrect determination has been made. When it is detected that an incorrect determination has been made, the internal state of the encoder replica is returned to the past state, and then the information symbol is determined to be the information symbol that was sent with the next largest Fano likelihood after the information symbol selected in the past. If you try to find the information symbol with the next highest Fano likelihood but cannot find it because it has already been searched, go back to the previous state and perform the same operation. Since decoding is performed through trial and error and the decoding result once output may be changed later, the decoder requires a buffer for the input received signal and a buffer for the decoding result.

The fan algorithm explained above is based on American fans (R
, M., Fano), and was developed by IEE
E-Transactions on Information
ation Theory, IT-9 (1963)
(US) p. 64-74. Further, the error correction encoder and decoder as described above are developed by, for example, American George David Forney Jr.
The circuit described in U.S. Pat. No. 3,665,396 by David Forney, Jr.

By the way, in order to compare the coded symbols output by the encoder replica with the received signal, it is necessary to
It is necessary to know whether it corresponds to a code symbol. In other words, it is necessary to perform this comparison in code synchronization with the received signal.Normally, the received signal does not contain timing information for code synchronization in a simple form such as a synchronization signal, so conventional sequential decoding devices performs code synchronization by trial and error, as explained below.

If the code synchronization is incorrect, the received signal has a very high probability of containing a transmission error, so decoding will not proceed and the received signal buffer will overflow. If it is determined that the code synchronization is incorrect due to this overflow, the code synchronization phase is shifted by one code bit of the code symbol, and then the received signal is decoded from the received signal newly input to the received signal buffer. If decoding does not proceed and the buffer of the received signal overflows, the same attempt is made again.If one code symbol consists of n code bits, there are n possible phases for code synchronization. Therefore, the above trials are performed at maximum (n−
1) Code synchronization will always be correct if it is repeated several times. Assuming that decoding does not proceed at all if the code synchronization is incorrect, one trial takes time to accumulate the received signal in the entire received signal buffer, and (n-1) times this time is required for the code. This is the maximum value of the synchronization pull-in time. Furthermore, each time a trial is performed, all received signals stored in the buffer at that time are discarded.

[Problem to be solved by the invention]

As explained above, in the conventional sequential decoding device, the maximum time (n-1
), and the received signal cannot be decoded during this time.

An object of the present invention is to provide a sequential decoding device with short code synchronization pull-in time.

[Means to solve the problem]

The successive decoding device of the present invention includes a received signal storage means capable of storing a predetermined first number of received signals obtained by transmitting and demodulating a modulated signal modulated with code symbols of a convolutional code; a decoding result storage means capable of storing the first number of decoding results; and a decoding result storage means capable of storing the decoding results already written from the decoding result storage means at the same time as the received signals are sequentially written into the received signal storage means. sequentially reading and outputting to the outside, sequentially decoding in code synchronization with the received signal read from the received signal storage means by trial and error, and writing the decoding result to the decoding result storage means when the decoding is completed; At the same time, when reading out the received signal written next to the received signal that has just been decoded from the received signal storage means and attempting to decode it, and reverting the decoding because there is a possibility of an error in the previous decoding, At the same time as reading the received signal written before the received signal read immediately before from the received signal storage means, writing the received signal to be read now into the decoding result storage means when the decoding is completed previously. The decoding result is read out and the decoding is redone, until the received signal written immediately before the received signal read out from the received signal storage means is rewritten by the newly input received signal. Each time the decoding is delayed and it is determined that there is an error in the code synchronization, the code synchronization is redone and a second number less than the first number predetermined from the latest received signal written in the received signal storage means is re-executed. and a sequential decoding means that repeats a reset operation of reading out and attempting to decode the previously written received signal by the number of times.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a sequential decoding device of the present invention.

1 is a RAM for buffering received signals, and 2 is a RAM for buffering decoding results. RAMI, 2 are both m1
It has a total number of addresses. Reference numeral 3 denotes a decoding processing unit that controls writing and reading of RAMI 2 using control signals Bl and B2, outputs address signals, and sequentially decodes received signals. Do is a demodulator at the receiving end (not shown)
The received signal CL inputted from is the clock signal of the received signal D0.

The decoding processing unit 3 includes counters 31 and 32, a selector 33,
It is composed of a control circuit 34 and a decoding circuit 35. The counter 31 is an m1-based counter that counts the clock signal OL and outputs the counted value as the 7-dress signal A1. The counter 32 is also an m-base counter and outputs an address signal A2 and a control signal B5. Selector 3
3 selects one of the address signals Al and A2 according to the control signal B6 from the control circuit 34 and outputs it to the RAMs 1 and 2.

When a new reception signal Do is input, the counter 31 counts the clock signal OL and the address signal A1 increases by one. At this time, the control circuit 34 responds to the control signal B5 from the counter 31 and outputs the control signal B6. The selector 33 outputs the address signal A1 in response to the control signal B6, writes the received signal D0 input to the 7 address A1 of the RAMI, and reads the decoding result E written to the address A1 of the RAM2. Output to outside.

Therefore, the address signal AI indicates the 7th address of the latest received signal D0 written to RAMI, and indicates the address in the received signal D10RAMI that is being decoded. When the decoding circuit 35 completes the decoding of the received signal D1 read from the RAMI immediately before, the decoding circuit 35 outputs a control signal B4 notifying the completion of decoding. Control circuit 34 responds to control signal B4 and outputs control signals Bl, B2 . B3.
Output B6. Selector 33 outputs address signal A2 in response to control signal B6. The decoding circuit 35 writes the decoding result to the address A2 of the RAM 2 under the control of the control signal B2. The counter 32 increases the address signal A2 by one in response to the control signal B3 from the control circuit 34. Next, the decoding circuit 35 decodes RAMI (
The next received signal D1 is read from the address A2 (increased by one), and the next decoding process is started.

The cycle of the decoding process is sufficiently shorter than the cycle of the clock signal OL, so if there are few transmission errors in the received signal D0 and the decoding progresses smoothly, the address signal A2 will catch up with the address signal A1 and the RA
The latest received signal D0 written to MI will be decoded. As a result, there is no new received signal D1 to read any more, so when the address signal A2 becomes equal to the address signal AI, the control circuit 34 outputs the control signal B4, and the decoding circuit 35 responds to the control signal B4 and performs the decoding process. Pause.

When performing decoding backwards, the control circuit 34 outputs control signals Bl,
B2. Output B3. The counter 32 receives the control signal B3
In response, the address signal A2 is decreased by one. The decoding circuit 35 outputs control signals Bl, B2°B3. The counter 32 responds to the control signal B3 and receives the 1 address signal A2.
decrease by one.

The decoding circuit 35 outputs ORAM1, ORAM1, and
The received signal D1 (previously decoded) and the decoded result D2 are read from the address A2 of No. 2, and the decoding is performed again.

In this way, the decoding circuit 35 receives the received signal.

are sequentially decoded.

The received signal Ds read out from RAM 1 just before (its R
The received signal written immediately before the address A2 in AMI (its address is A2-1) is replaced by the newly input received signal (the address of this write is AI). For example, if the decoding is delayed until A2-1=AI, the decoding will not be completed due to the next newly input received signal D0 (at address A2).
The received signal will be compromised. Therefore, if the decoding is delayed until A2-1=A1, the decoding circuit 35 determines that the RAMI has overflowed.

If the quality of the transmission path deteriorates and transmission errors occur frequently in the received signal, decoding will not proceed and the RAM 1 will overflow.

If the transmission quality is normal, the number m1 of addresses in RAMI C and 2) is set so that the probability of RAMI overflow occurring is extremely small.

By the way, since the decoding processing unit 3 performs code synchronization by trial and error, as will be described in detail below, the RAMI overflows due to an error in code synchronization.

When the control circuit 34 determines that the RAM1 has overflowed due to an error in code synchronization, the control circuit 34 outputs the control signal B3. B4.
Output Bl. The counter 32 responds to the control signal B3 and converts the address signal A2 from 7 address A1 to mz (however, m
s < m r ) Reset to a small value. The decoding circuit 35 shifts the phase of the code synchronization by 1 bit of the code symbol of the convolutional code, and uses the control signal B1 to shift the code synchronization phase by one bit of the code symbol of the convolutional code.
The received signal is read from the (reset) address A2 and decoding is restarted. In other words, the latest received signal written to RAMI is the received signal D written m2 times earlier.
Even if the code synchronization is redone and the address signal A2 is reset (these are collectively referred to as reset operations), the code synchronization is not correct and R is read out and decoded.
If AMI overflows again, perform the reset operation again, reset operation error code synchronization is still not correct R
The time until AMI overflows again is determined by the clock signal CL, assuming that the decoding does not make full progress during this time.
It is approximately (ml-m times the period of It has already been mentioned that code synchronization will always be correct if the reset operation is repeated a maximum of (n-1) times.

If code synchronization is correct, decoding will proceed smoothly,
Even if (m 1- m !) is considerably smaller than ml, R
It can be expected that the AMI will no longer overflow. As already explained, the conventional sequential decoding device converts the address signal A2 into the 7F-res signal A after code synchronization is redone.
Since it was reset equal to 1, after the reset operation RA
Clock signal OL until MI overflows again
It took approximately m1 times the period of . In the embodiment shown in FIG. 1, this time is approximately (m, -m s) times the period of the black signal OL, so the maximum time required for code synchronization in the embodiment shown in FIG. Maximum required time (ml-mt) in conventional sequential decoding device
/m+. In this way, by reducing (ml mz), the code synchronization pull-in time of the embodiment shown in FIG. 1 can be shortened.

The received signal that cannot be decoded and is discarded after each reset operation is expressed as the number of RAMI addresses (mt-m=-
1) It is in pieces. Therefore, the amount of received signal that is discarded during code synchronization pull-in is also reduced at a rate approximately equal to the reduction in the maximum time required for code synchronization, compared to the conventional sequential decoding apparatus.

Note that code synchronization has been explained here as accurately dividing one code symbol from a received data sequence (referred to here as branch synchronization), but when orthogonal modulation is adopted as the transmission path modulation method, It is synchronized even if interpreted as code synchronization, including a synchronization function to remove the four-phase phase uncertainty of Can be established. However, in this case, it is necessary to separately decide whether to perform branch synchronization, synchronization to remove four-phase phase uncertainty, or resynchronization in the sequential decoding method in response to the overflow of RAM1.

〔Effect of the invention〕

As described above in detail, the sequential decoding device of the present invention is capable of decoding the received signal a certain number of times before when the buffer of the received signal overflows and it is determined that there is an error in code synchronization and code synchronization is re-executed. Since the decoding process is restarted from the received signal written in the buffer to shorten the repetition period of code synchronization, there is an effect that the code synchronization pull-in time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a sequential decoding device of the present invention. 1.2...RAM, 3...Decoding processing unit, 31°32...Counter, 33...
Selector, 34...Control circuit, 35...
・Decoding circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Scope of Claims] Received signal storage means capable of storing a first predetermined number of received signals obtained by transmitting and demodulating a modulated signal modulated with code symbols of a convolutional code, and decoding of the received signal. decoding result storage means capable of storing the first number of results; and at the same time as sequentially writing the received signals into the received signal storage means, sequentially reading out the already written decoding results from the decoding result storage means. The received signal is read out from the received signal storage means and code synchronized with the received signal read out from the received signal storage means to perform sequential decoding, and when the decoding is completed, the decoding result is written to the decoding result storage means and at the same time the When decoding is attempted by reading out the received signal written next to the received signal that has just been decoded from the received signal storage means, and when decoding is to be performed backwards because there is a possibility of an error in the previous decoding, the received signal is The decoding that was written in the decoding result storage means when the received signal to be read now was previously decoded at the same time as the previous received signal written before the received signal read immediately before from the signal storage means. The result is read out and the decoding is redone, and the decoding is delayed until the received signal written immediately before the received signal read from the received signal storage means is rewritten by the newly inputted received signal. Each time it is determined that there is an error in code synchronization, the code synchronization is re-performed and the code synchronization is performed again by a predetermined second number, which is less than the first number, from the latest received signal written in the received signal storage means. A sequential decoding device comprising a sequential decoding processing means for repeating a reset operation of reading out the received signal written in the memory and attempting to decode it.