JPH0748834B2 - Video signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video tape recorder (hereinafter referred to as VTR),
The present invention relates to a video signal processing device that can be used in a television receiver or the like and facilitates channel selection of television broadcasting.

2. Description of the Related Art Conventionally, when selecting a broadcasting station in a television receiver, look at the program column of a newspaper or the like and select a favorite channel, or press the respective channel selection button to change the channel and select the desired channel. The usual tuning method is to stop at a tuning position and watch the station.

Problems to be Solved by the Invention Although the above-mentioned channel selection method is one in which each person selects a channel on his / her own will, it is very troublesome to read newspapers or change channels many times. However, there is a problem that it takes time and effort.

In view of the above-mentioned problems, the present invention automatically selects a channel by displaying the images of a large number of broadcasting stations on one screen and making the currently received channel a moving image for a certain period of time. A video signal processing device that facilitates a station is provided.

Means for Solving the Problems In order to solve the above problems, a video signal processing device of the present invention is a memory having a capacity capable of accumulating a video signal for at least one field, and a sync signal for detecting a sync signal from the video signal. The data of the video signal is read from the separation circuit and the memory, and the television screen is divided into n (n is an integer of 2 to 32) based on the sync signal. A memory control circuit for writing in the memory so that the video signal becomes a reduced image on the screen, a television signal receiving circuit capable of receiving a radio wave of television broadcasting to obtain a video signal, and changing the receiving station according to a command, The video signal received by the television signal receiving circuit is in m (m is an integer of 10 or more) field periods in one of the n small screens divided into n. A small screen different from the small screen in which the video signal is written for the m field period by sending a command to the memory control circuit to write continuously and then sending a command to the television signal receiving circuit to change the receiving station. By repeating the procedure of writing in m field periods for a period of time and then changing the receiving station again, the image of each broadcasting station is displayed on the television screen on the multi-screen of n divisions, and after writing all n small screens, the first time again. From the above, a control circuit for controlling each station to be a moving image for m field periods and an input means for making the image of each broadcasting station into a multi-screen of n divisions or canceling it are provided. .

Operation The present invention has the above-described configuration, in which channels are automatically switched and the images of a large number of broadcasting stations are displayed in order on the TV screen, and the receiving channel displays an appropriate time-reduced image as a moving image. By canceling the n-divided multi-screen using the input means while the desired channel is a moving picture, the desired channel can be selected. In order to cancel the n-division multi-screen while the image of the station you want to see is a moving image, by writing continuously for at least 10 field periods on one of the n small screens. The time can be secured.

Practical Example A video signal processing device according to an example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is an antenna for receiving radio wave signals of television broadcasting, and 2 is an antenna 1.
A television signal receiving circuit that demodulates the signal of the specified broadcasting station from the radio signal received by and outputs it as a video signal. Reference numeral 3 is an A / D converter that performs analog-digital conversion of the input video signal into a digital video signal. 4 is a serial-parallel (S / P) converter that stores a plurality of input serial data and outputs as parallel data. 5 is a parallel-serial that sequentially selects a plurality of input parallel data and outputs as serial data. (P / S) converter, 6 is a D / A converter for converting a digital video signal into an analog video signal, and 7 is a memory having a storage capacity capable of accumulating a digital video signal for one field.
It is composed of a random access memory (D-RAM). 8 is a sync signal separation circuit for detecting vertical and horizontal sync signals from the video signal output from the television signal receiving circuit 2, 9 is a clock generation circuit for generating a clock synchronized with the video signal, and 10 is for the memory 7. A memory control circuit for controlling writing / reading by a switch, 11 a switch for setting / releasing an n-divided multi-screen mode, 12 a control circuit for controlling each circuit according to an input of the switch 11, 13 a television signal receiving circuit 2 output signals
A switch for selecting an output signal of the D / A converter 6 and an output terminal 14 for a video signal.

The operation of the video signal processing device configured as described above will be described below with reference to FIGS. 1, 2 and 3.

FIG. 2 is a diagram showing control signals and write data / read data to the memory.

The memory control circuit 10 sets the memory 7 alternately in a write mode and a read mode in accordance with the reference clock from the clock generation circuit 9, and outputs a CAS (column address strobe) signal, RAS, required for writing and reading.
(Row address strobe signal), WE (write enable) signal, OE (output enable) signal, etc. are generated and supplied to the memory 7. Figure 2 (a) is RA
The waveform of the S signal, (b) shows the waveform of the CAS signal, and the write mode and the read mode are set for each time. (WE signal and OE signal are not shown) A data write operation to the memory 7 when the mode is set in this way will be described.

The digital video signal sampled by the A / D converter 3 is converted into, for example, four parallel data by the S / P converter 4. This operation will be described with reference to FIGS. 2 (c) to 2 (f). FIG. 2 (c) is a diagram showing data (W _{1-0 to} W _2-3 ) sampled by the A / D converter 3, and is a memory 7 once.
After writing to, the data is sampled four times until the next writing. The S / P converter 4 is composed of, for example, four kinds of shift registers and a latch circuit, and inputs the signal of FIG. 2 (c) according to a command from the memory control circuit 10 to sample the four kinds of shift registers. The signals shown in FIGS. 2 (c) to 2 (f) are generated by shifting each time, and four types of data immediately before the memory enters the write mode are latched and supplied to the memory 7. In writing (1) in FIG. 2, W _1-0 , W _1-1 , W _1-2, and W _1-3 are latched, sent to the memory 7, and written. In this way, S / P converter 4
Operates so that continuous data can be written even though the write mode and the read mode are alternately and discontinuously performed with respect to the memory. The address signal to the memory 7 in the write cycle is also output from the memory control circuit 10. The memory control circuit 10 controls the address of the memory 7 in accordance with the vertical / horizontal synchronization signals and clock signals synchronized with the video signals input from the synchronization signal separation circuit 8 and the clock generation circuit 9, and also samples the input video signals. By sending the timing to the S / P converter 4, it becomes possible to write the video signal input to the small screen obtained by dividing the television screen into n as a reduced image.

Next, the operation of reading data from the memory 7 will be described.

In the read cycle of FIG. 2, the memory control circuit 10
Outputs the read address to the memory 7. There are four types of data read from the memory 7 because four types of data are written at the same address during writing. The P / S converter 5 sequentially supplies four types of data read from the memory 7 to the D / A converter 6 in accordance with commands from the memory control circuit 10. This operation will be described with reference to FIGS. 2 (g) and (h). At the timing of reading (1), four types of data R _1-0 , R _1-1 , R _1-2 shown in FIG.
・ R _1-3 is read from the memory 7, and the p / S converter 5 latches the four types of data in response to a command from the memory control circuit 10 and sequentially outputs R _{1- as} shown in Fig. 2 (h). ₀ / R _1-1 / R _1-2 / R
It is supplied to the D / A converter 6 in the order of _1-3 .

As described above, by converting the data to S / P and P / S, the data is not interrupted even if the write mode and the read mode are set separately for the memory. Since the data can be read from the device, the reduced image can be displayed as a moving image on the television receiver by reading the data of one field while writing the input video signal as the reduced image.

Next, each process when displaying images of nine television broadcasting stations on a television screen divided into n (in this embodiment, n = 9 is set to 9 divisions) will be described.

FIG. 3 is a diagram showing a television screen divided into nine parts. The television screen 20 is divided into nine screens, and a multi-screen 21 is displayed.
・ 22 ・ 23 ・ 24 ・ 25 ・ 26 ・ 27 ・ 28 ・ 29 are prepared. The address configuration of the memory 7 is also as shown in FIG. 3, and the video signal input by the write address output from the memory control circuit 10 is used as a reduced image in the control circuit 12 of the 9 positions. It is configured to write to a specified position.

First, normally, the switch 13 is selected so that the output video signal of the television signal receiving circuit 2 is output to the output terminal 14. At this time, when the switch 11 is pressed, the control circuit 12 sends a command to the memory control circuit 10 so that the video signal of the receiving station at that time is displayed on the multi image 21 on the upper left of FIG. 3, and the switch 13 is set to the D / A converter. Switch to 6 side. In the method of reducing the length and width to 1/3, the number of pixels of one field formed by the memory 7 is thinned out by 1/3 of the length and 1/3 of the width and written in the memory 7. That is, the memory control circuit 10 performs S / S at a cycle such that the number of horizontal samplings of the input video signal becomes the number of horizontal pixels of the multi-image 21 in FIG.
A sampling command is sent to the P converter 4 so that it is written in the memory 7 once every three scanning lines in the vertical direction. Also,
Writing to the position of the multi-image 21 on the upper left of FIG. 3 is because the address configuration of the memory 7 is also as shown in FIG.
This is possible by controlling the write address. Since the reading of the memory 7 at this time is configured such that writing and reading of the memory 7 can be performed independently as described above, the memory control circuit 10 sets the read address of the memory 7 from the upper left of FIG. It may be generated so that the scanning is the same as the scanning line of the television signal. In addition, the multi-image of Fig. 3
If a certain level of data is written to the memory 7 before writing 21, the parts other than the multi-image 21 will be the same constant image, making it easier to see. After writing to make a moving image, the control circuit 12 changes the receiving channel of the television signal receiving circuit 2 and writes the video signal of the changed receiving channel to the multi-image 22 of FIG. 3 for a certain period of time. At this time, the still image of the image of the previous channel is displayed on the multi-image 21. And then
If you change the channels again and write to multi-image 23, you can write each channel to multi-images 21 to 29 in order, and in this case you can see images corresponding to up to 9 broadcasting stations as one screen. , If the switch 11 is pressed while the image of the station you want to watch is a movie, the control circuit 12 stops the control to change the channel, and the switch
By switching 13 to the television signal receiving circuit 2 side, it is possible to select the station to be watched. In addition, by writing continuously on at least 10 field periods in one small screen among the n small screens, the n-division multi-screen is canceled while the image of the station you want to see is a moving image. It is possible to secure the time for pressing the switch 13 for.

Further, if the control circuit 12 receives the information of the current channel number from the television signal receiving circuit 2 and sequentially writes the information from the multi-screen 21 after the station having the smallest number is selected, the station can be started from any channel. The relationship with the multi-image is constant and it is easy to see. In addition, the channel with no broadcast signal is detected, and if there is no broadcast signal,
If you do not write the multi-image, you can use the multi-image effectively. Also, in regions where there are less than 9 stations, if the station with the lowest number is re-written before writing 9 multi-images, the multi-image 21 will be re-written. Becomes constant and is easy to see.

As described above, according to the present invention, it is possible to automatically switch the receiving channel and simultaneously display the images of a large number of broadcasting stations on the television screen, so that all the contents of the current broadcasting program can be displayed without trouble. You can check. Further, when the program to be watched is a moving image, if the mode of the multi-screen is released, the excellent effect that the program can be viewed on a normal television screen can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video signal processing device of an embodiment of the present invention, FIG. 2 is a schematic diagram showing a control signal and write data / read data to a memory, and FIG. 3 is a television screen divided into 9 parts. It is a schematic diagram which shows. 1 ... Antenna, 2 ... Television signal receiving circuit, 3
…… A / D converter, 4 …… S / P converter, 5 …… P / S converter,
6 ... D / A converter, 7 ... memory, 8 ... synchronization signal separation circuit, 9 ... clock generation circuit, 10 ... memory control circuit, 11 ... switch, 12 ... control circuit, 13 ... Switch, 14 …… Video signal output terminal.

Claims (1)

[Claims] 1. A memory having a capacity capable of accumulating at least one field of a video signal, a sync signal separation circuit for detecting a sync signal from the video signal, data of the video signal being read from the memory, and the sync signal as a reference. A memory control circuit that writes the video signal to the memory so that a video signal is a reduced image on a small screen specified in advance out of n small screens obtained by dividing the television screen into n (n is an integer of 2 or more).
A television signal receiving circuit capable of receiving a television broadcast wave to obtain a video signal and changing a receiving station according to a command, and a video signal received by the television signal receiving circuit are divided into n. A command is sent to the memory control circuit so that data is continuously written in one small screen out of n small screens for m (m is an integer of 10 or more) fields, and then received by the television signal receiving circuit. A command to change the station is sent, the video signal is written on a small screen different from the small screen written on the m field period for the m field period, and then the receiving station is changed again. The image of each broadcasting station is displayed on an n-divided multi-screen, and after writing all n small screens, it is repeated from the beginning again for each m-field period. A control circuit for controlling a moving image and an input means for making an image of each broadcasting station into an n-divided multi-screen and canceling it are provided, and a desired station in an n-divided multi-screen state. A video signal processing apparatus, characterized in that, when the input means is input while the video is an m field period moving picture, the n split multi-screen is released and a desired station is selected.