JPS60257681A - Television receiver - Google Patents

Abstract

PURPOSE:To display simultaneously a picture of plural channels in one pattern by switching a channel in a predetermined period to use only a tuner. CONSTITUTION:A TV signal is subject to high frequency amplification and intermediate frequency amplification by a tuner 1 and goes to a video signal through a video amplifier circuit 2. The video signal from the circuit 1 is fed to a synchronizing signal processing section 4, from which a horizontal and a vertical synchronizing signal are transmitted. A signal processed by a video signal processing circuit section 3 is stored in a buffer memory 17 via a multiplexer circuit 15. The content of the memory 17 is transferred to a display memory 19, read by an address signal of a synchronizing signal generating/display memory 21 during the display period and displayed on a cathode ray tube 9. A CPU12 commands the selection of the next channel to a channel selection section 10.

Description

TECHNICAL FIELD The present invention relates to a television receiver capable of simultaneously displaying images of a plurality of channels on both sides.

BACKGROUND ART Traditionally, this type of television receiver (such as 1 Japanese Patent Application No. 47-39273 (Japanese Unexamined Patent Publication No. 49-2419)) displays images of two channels, main and sub, on the screen. Simultaneous projection systems have already been proposed and some have been put into practical use.

However, in such a television receiver m, only two images can be displayed at the same time, and if more images are to be displayed simultaneously, it is necessary to install an additional tuner for the number of images.

Currently, in Japan's broadcasting state 1, the number of broadcasting stations that can be received in one area is nine channels at most, and if nine images are displayed simultaneously on one screen, it is possible to check all two channels broadcasting in that area at the same time. However, in this case, there are usually nine tuners and nine BBDs (bu-cket brigade).
device) or RAM (ra-ndam ac
A storage device such as cess memory is required.

Purpose The purpose of the present invention is to solve the above-mentioned technical problems and to provide a television capable of simultaneously displaying images of multiple channels on one screen using one tuner. The purpose is to provide a television receiver.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. First, the operation when receiving normal television broadcasting will be explained. A television broadcast signal is received by an antenna 1a, high frequency amplified and intermediate frequency amplified by a tuner 1, and passed through a video amplification circuit 2 to become a video signal. This video signal is processed by the video signal processing circuit 3 into a luminance signal Y and a color difference signal R.
-Y and B-Y. Luminance signal Y and color difference signal R
-Y and B-Y are applied to the switch 5 and the multiplexer circuit 15.

On the other hand, the video signal from the video amplification circuit 2 is given to a synchronization signal processing section 4, and a horizontal synchronization signal and a vertical synchronization signal are sent out from the synchronization signal processing section 4.

When the contact a1 of the switch 5 is connected to the contact C1, the luminance signal Y1 from the video signal processing circuit 3, the color difference signal RY,
B-Y is applied to a video amplification circuit 7, amplified to a predetermined level, and applied to a cathode ray tube (CRT) 9. When the contact a2 of the switch 6 is connected to the contact C2, the horizontal synchronization signal and the vertical synchronization signal from the synchronization signal processing section 4 are applied to the deflection output circuit 8 to scan the screen of the cathode ray tube 9.

Up to this point, the operation is the same as that of a normal television receiver.

Next, we will read about multi-channel video display (hereinafter referred to as multi-mode). The luminance signal Y1 color difference signal RY, BY processed by the video signal processing circuit 3 is given to the multiplexer circuit 15, and the luminance signal Y, the color difference signal RY,
The color difference signals are selected in the order of B'-Y. The 15 multiplexer circuits are ordinary analog multiplexers. The output of the multiplexer circuit 15 is converted into a digital signal by an A/D (analog/digital) converter 16 and stored in the buffer memory 17 according to a timing signal from the buffer memory control circuit 18.

FIG. 2 is a detailed block diagram of the buffer memory 17 and its vicinity. First, in response to a command from the CPU (central processing unit) 12, the control signal output circuit 35 supplies a control signal of 2 as shown in FIG. 3 (12) to the one vertical period signal generation circuit 28. As a result, the one vertical period signal generation circuit 28 is configured as shown in FIG. 3(1).
3i is generated in the control signal shown in the 31st gH31 only during the vertical period from the vertical synchronizing signal v1 shown in FIG. 1 to the next vertical synchronizing signal v2. 3 to this control signal, the column counter 26
and row counter/receiver 27 generates an address signal during that period.

FIG. 3(4) shows the state of the address signal from the column counter 26. At that time, the contacts a3, a4, and a5 of the switches 23, 24°25 are the contacts c3 Hc4 +C5
are connected to each. Therefore counter 26.27
The outputs are respectively given to the buffer memory 17.

Also, multiplexer circuit 15 and A/D converter 1
The luminance signal Y1 and the color difference signals R-Y and B-Y that have traced through the IP address buffer memory 17 are given to the IP next buffer memory 17.

At this time, the multiplexer circuit 15 is configured so that the switches a, b, and c are opened and closed in sequence according to the address signal supplied from the column counter 26.

As a result, as shown in FIG. 3(4) and FIG. 3(5), for example, the luminance signal Y is placed at address A of the backup memory 17, and the color difference signal RY is placed at address A+1.

The color difference signals B-Y are stored at address A+2, the luminance signal Y is stored at address A+3, and so on. When the luminance signal Y and the color difference signals R-Y and B-Y for one vertical period are thus applied to the buffer memory 17, the counters 26 and 27 stop, and the switch 2
3.24.25 contact b3. b4. b5 is the contact point c3. c.
4. c5 respectively.

Next, the operation regarding the display memory 19 will be explained.

During the display period during which the contents of the display memory 19 are displayed on the cathode ray tube 9, a control signal kli is generated from the control signal output circuit 35 to connect the CPU 12 +-j switches 5 and 6 to the contacts bl, b2i contacts cl and c2. let As a result, the contents of the display memory 19 are converted into an analog signal by the D/A (digital/analog) converter 22,
All signals from the switch 5 are amplified by the video output circuit 7 and supplied to the cathode ray tube 9.

On the other hand, the synchronization signal generation/display memory control section 21 starts operation with the control signal 1, and the display memory 19 receives the address signal ? , and the switch 6, respectively. The horizontal and vertical synchronizing signals from the synchronizing signal processing section 4 are supplied to a deflection power circuit 8 through a switch 6, and then to a cathode ray tube 9.

A detailed configuration around the display memory 19 is shown in FIG. C.P.
When 1 is sent to the control signal from U12, the horizontal synchronizing signal generation counter 30 starts counting in response to the clock signal from the reference oscillation circuit 20. This horizontal synchronization signal generation counter 30 generates a horizontal synchronization signal and at the same time generates a column-direction address signal for the display memory synchronized with the horizontal synchronization signal. also occurs.

Vertical synchronization signal generation counter 3114. Based on the clock pulse from the horizontal synchronization signal generation counter 30, a vertical synchronization signal f'< as shown in the fifth [1m] is generated.

At the same time, an address signal in the row direction is also generated for the display memory 19. These address signals are transmitted through contacts a6, C7 and c5 of switches 32 and 33, respectively. When connected to c7, it is supplied to display memory 19. The data sent from the result display memory 19 is transmitted to the D/A converter 22 through the contacts c8, a8i of the switch 34.
The signal is supplied to the switch 5 shown in FIG. 1, converted into an analog signal, and supplied to the switch 5 shown in FIG. Here, switch 3 shown in FIG.
2, 33, and 34 are controlled by the vertical homecoming erase period signal g generated from the vertical synchronizing signal generation counter 31 as shown in FIG. 5(2). In addition, in FIG. 5 +3+ fd 1 period T1, the contacts b6, b7, of switches 32, 33, 34.
b8 is the contact point c6. c7. contacts a6 .c8 of switches 32, 33, and 34 during period T2. C7,C
8 are connected to contacts c5, C7, and C8, respectively, and contacts b6 and b7 of switches 32, 33, and 34 are connected at T3.
, b8 is the contact point c6. This shows how C7 and C8 are connected, respectively. Contacts b6 of switches 32, 33, and 34. b7 and b8 are the contact points c6. c7. c8, the address bus and data bus (4) from the CPU 12 are applied to the display memory. Also, since the vertical blanking period signal g from the vertical synchronization signal generation counter 31 is also applied to the CPU 12, , the CPU 12 determines that the address bus and take bus are connected to the display memory 19 based on the internal bounds of the vertical blanking period signal g.For example, as shown in FIG. 5(1), when the vertical blanking period signal g is high level, the CPU 12 determines that the address bus and data bus are connected to the display memory 19.As a result, the CPU 2 transfers the entire contents of the buffer memory 17 to the display memory 19.0 The operation of the CPU 12 will be explained below. When the multi-mode is set on the operating section 11 that controls each circuit according to the contents of the operating section 11 of the CPU 2, the control signal output circuit 3
5 instructs the channel selection unit 10 to select channel 1 (chi). -! The CPU 12 has a control signal output circuit 35.
The control signal kl is fully sent out, contacts b1 and b2 of switches 5 and 6 are connected to contacts cl and C2, respectively, and the synchronizing signal generation/display memory control section 21 is operated.

Thereafter, the CPU 12 determines all the vertical #line erasing period signals inputted from the input port 14, and transfers the contents of the buffer memory 17 to a specified position in the store area of the display memory 19 during that period. By this transfer, the backup memory 17
The contents are transferred to the display memory 19, read out by the synchronization signal valve and the address signal of the raw/display memory control section 21 during the display period, supplied to the D/A converter 22, and reproduced as an analog video signal. It is displayed on the cathode N tube 9.

When such transfer is completed, the CPU 12
On the other hand, is it possible to select channel 2 (ch2) following channel 1? Instruct. Therefore, the CPU 12 causes the control signal output circuit 35 to generate the control signal 2 again, and transfers the video information of channel 2 to the buffer memory 17 for one vertical period.
write to. After that, performs the same operation as when channel 1 is selected, and transfers the entire contents of the buffer memory 17 to the display memory 191.The contents of the display memory 19 are as follows:
displayed on the cathode ray tube 9. Such a channel selection operation is performed up to channel 9, and when the series of processing is completed, channel 1 is designated again and the same processing is performed. The display screen thus obtained is shown in 6□□□. As shown in FIG. 6, images from channels 1 to 9 can be viewed simultaneously.

The operation of the CPU 12 as described above is based on the program memory 1
This is performed by a program stored in advance in 3.

Next, what does this program do? , will be explained with full reference to the flowchart shown in FIG. The CPU 12 starts operating in step n1, and moves to step n2.

In step n2, it is determined whether or not there is human power from the operation unit 11. If there is human power, the process moves to step n4, and if there is no human power, the process moves to step n3. In step n3, it is determined whether or not the previous state is multimode, and if it is multimode, the process moves to step n7, and multimode processing 2
If the mode is not multimode, the process returns to step n2.

In step n4, it is determined whether or not the content of the manual input of the key on the operation unit 11 is a channel key. If it is a channel key, the process moves to step n, 16, and if it is not a channel key, the process moves to step n5. In this embodiment, numeric keys indicating channels and a "multi" key indicating multi mode are provided as key glazes. Therefore step n4
Now, I'm wondering if the sand key was entered.

In step n16, the multi mode is canceled and the display screen from the display memory 19 is changed to a normal television screen (C
In order to restore the program, the control signal k 1 '(z IJ) is set. In step n17, an instruction is issued to the channel selection section 10 to select the specified channel according to the contents of the numeric keys, and the process returns to step n2.

In step n5, it is determined whether or not the key manual input is in the multi-mode. If the key is in the multi-mode, the process moves to step n6, and if it is not in the multi-mode, the process returns to step n2.

At step n6, the multi-mode all cents are set, the control signal kli is set, and the multi-mode display is made. Also, channel 1 is selected for initial setting of the channel.

In step n7, it is determined whether or not the data transfer has been completed during the previous vertical blanking period, and if it has been completed, @ moves to step n8, and if data is being transferred +d step n1
Move on to 2. In step n8, it is determined whether or not the data transfer for selecting channel 9 has been completed (T), and if it has been completed, the process moves to step n9;
Move to o. In step n9, channel 1 is set, and the channel selection unit 10 is instructed to enable tuner 1 to receive channel 1, and the process moves to step nil.

In step nlo, the previously set channel number is incremented by 1, the channel number is instructed to the channel selection section 10,
The tuner 1 is instructed to receive the broadcast signal of the broadcast station corresponding to the channel number.

In step nil, the control signal output circuit 35 sends the control signal 2'(i7) to write video information in the buffer memory 17. Then, in step n12, the start of the vertical blanking period (V-BLK) is waited for. When the vertical blanking period arrives, the process proceeds to step n13, where the contents of the backup memory 17 are transferred to the full display memory 19.However, when the contents of the buffer memory 17 are transferred to the constant amount display memory 19, the process proceeds to step n14, where the vertical blanking is performed. The end of the line erasing period is fully confirmed, and when the line erasing period has ended, the process returns to step n2.

Further, if the vertical blanking intercostal period is not completed in step n14, the process waits for a certain period of time in step n15, returns to step n13 again, and returns to the buffer memory 17.
The customer information is transferred to the display memory 19. Note that step n1
The timer No. 5 obtains its timer effect by executing the instruction K1 line without any opinion.

Therefore, the final transfer processing time 1 is determined to be the speed that is visually most effective depending on the amount of video information transferred at one time and the number of instruction steps performed by the timer. In other words, in this embodiment, the transfer time of video information for one screen (small screen) is
It is set at around 50.5 to 1 second. This allows for smooth screen switching and a natural visual effect.

Effects As described above, according to the present invention, multiple channel images can be
This makes it possible to display images on multiple tuners, allowing users to view all receivable broadcasting stations at the same time, and making it possible to judge conventional channel operations based on the content on the screen.

[Brief explanation of the drawing]

Fig. 1 is an overall block diagram of an embodiment of the present invention, Fig. 2 is a detailed block diagram of the buffer memory 17 and its vicinity, and Fig. 3 shows the operation and timing of the block diagram in Fig. 2. 4 is a detailed block diagram of the vicinity of the display memory 19, FIG. 5 is a timing diagram for explaining the block diagram of FIG. It is a flowchart of the program. 1a...Antenna, l...Tuner, 2...Video amplifier circuit, 3...Video signal processing circuit, 4...Synchronization signal processing unit, 5, 6...Switch, 7... Video output circuit, 8... Deflection output circuit, 9... Cathode @ tube, 10.
... Tuning section, 11... Operation section, 12... Central processing unit, 13... Program memory, 14... Input board, 15... Multiplexer circuit, 16... Analog/digital converter, 17...Buffer memory,
18... Panzer memory control circuit, 19... Display memory, 2o... Reference oscillation circuit, 21... Synchronous signal generation/display memory control section, 22... Digital/analog controller, 35...Control signal output [Route 91 agent Patent attorney Kei Nishi

Claims (1)

[Claims] In a television receiver, the channel is switched at a predetermined period, the video content of each channel is stored in a display memory, the content of the display memory is updated every time, and the channel is displayed as a still image on the display means. a first synchronization signal obtained from the first video signal, and a second synchronization signal that is a television synchronization signal generated by a clock signal from a reference oscillation circuit. , a second video signal from the display memory read out by an address signal generated by a clock signal from the reference oscillation circuit and a second synchronization signal;
．． a first switching means for switching the second video signal;
．． A second switching means for switching the second synchronization signal is included, and when receiving normal television broadcasting, the synchronization signal of the first video signal is used to display the first video signal, and when displaying a still image, the synchronization signal of the first video signal is used. , a first video signal is converted into a digital signal by an analog/digital conversion means, and the digital signal is stored in a buffer memory accessed by an address signal generated by a first synchronization signal and a clock signal from the reference oscillation circuit. The content of the buffer memory is transferred to the display memory at a preset transfer time by the full processing circuit, and the second video signal from the display memory is displayed using the synchronization signal of the full result 2. Television reception was only 1.