JPH0745820A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To provide a manufacture of a MOS transistor which can get source and drain diffusion area of shallow junction without increasing the number of steps. CONSTITUTION:Impurities diffuse preferably into a gate electrode too at the same time even if impurities are introduced and diffused so that the depth of the junction of the source and drain regions may be shallow, by introducing impurity ions into source and drain diffusion areas 8 and a gate electrode and further, diffusing them after growing a mask material 7 on a substrate 1, where a gate electrode 4 and an insulating film 6 covering the gate electrode are made, and etching this until the insulating film is exposed. Accordingly, the impurity implantation into the source and drain diffusion areas can be performed at the same time, so the manhours can be reduced, and the work time shortened. Moreover, this mask material can be pattered into source and drain electrodes and/or wrings by using polysilicon as the mask material, whereby the manhours can be lessened further.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type transistor, and more particularly to a source / drain diffusion region and a gate electrode made of a conductive thin film having the same conductivity type.
The present invention relates to a method for manufacturing an OS transistor.

[0002]

2. Description of the Related Art Conventionally, in a complementary MOS transistor having a gate length of 0.5 μm or more (hereinafter abbreviated as CMOS transistor), a source / drain is formed on a gate electrode made of a conductive thin film by, for example, a vapor phase diffusion method. It has been generally performed to reduce the resistance of this gate electrode by introducing an impurity of the same conductivity type as that of the diffusion region.

According to the above method, for example, n is formed on the gate electrode.
When the n-type impurity is introduced, a work function difference is generated between the gate electrode and the substrate in the n-type MOS transistor, and an appropriate threshold voltage can be obtained. However, since the gate electrode of the p-type MOS transistor also becomes n-type, A work function difference does not occur between the gate electrode and the substrate unlike the type MOS transistor. Therefore, particularly when an attempt is made to improve the driving ability by setting the threshold voltage to, for example, 1 V or less, the p-type MOS transistor is of a so-called buried channel type in which the same conductivity type as the source / drain diffusion regions is diffused on its channel surface. It was necessary to take a structure.

However, with the recent trend toward higher integration density of integrated circuits, if the gate length is reduced to 0.5 μm or less, for example, a buried channel type p-type transistor has a punch-through between the source and the drain and a short channel effect. Etc. becomes a problem. Therefore, even in the p-type MOS transistor, it is necessary to adopt a so-called surface channel type structure in which the channel surface does not have an impurity diffusion layer of the same conductivity type as the source / drain diffusion regions as in the n-type MOS transistor. It was Therefore, a MOS transistor in which the gate electrode made of a conductive thin film and the source / drain diffusion region have the same conductivity type and a work function difference does not occur between the gate electrode and the substrate, and the threshold voltage of the transistor does not drop Developed and proposed.

By the way, in the MOS type transistor, it is necessary to make the junction depth of the source / drain diffusion regions shallower as the gate length becomes shorter. Conventionally, generally, a method of directly introducing impurities into the source / drain diffusion regions by an ion implantation method has been adopted.
However, when this method is used, it is impossible to reduce the ion implantation acceleration voltage to a certain value or less, and therefore it is not possible to make the junction depth determined by the acceleration voltage shallower to some extent. It was possible. In order to deal with these problems, the junction forming method as shown in FIGS. 2A to 2D is generally used. That is, first in FIG.
As shown in (a), the element isolation region (LO
COS) 22 is formed, and then a gate electrode 24 made of an insulating film 23 and a conductive thin film is formed.
Side wall spacer 25 made of an insulator on the side wall of the
An insulating film 26 is formed to cover the gate electrode 24 and the upper portion thereof. Next, as shown in FIG. 2B, after forming a polysilicon film 27 as a mask over the entire surface of the substrate 21,
Impurities are introduced into the film 27 as indicated by arrows, and thermal diffusion is performed by, for example, RTA (Rapid Thermal Anneal) to diffuse the impurities into the source / drain diffusion regions 28 as shown in FIG. 2D. Is.

[0006]

However, if the junction depth of the source / drain diffusion regions 28 is made shallow by the above-mentioned conventional method, the impurities do not reach the gate electrode 24, for example, the impurities do not reach the gate electrode 24. Introduction of,
Since the diffusion process had to be performed, the number of steps was increased, and the work tended to be complicated.

The present invention has been made in view of the above-mentioned problems of the prior art, and the main purpose thereof is a MOS type which can obtain a source / drain diffusion region of a shallow junction without increasing the number of steps. It is to provide a method for manufacturing a transistor.

[0008]

Means for Solving the Problems The above-described object is to form a gate electrode made of a conductive thin film and an insulating film covering the upper part thereof on a substrate, and a substrate on which the gate electrode and the insulating film are formed. A step of forming a mask material on the substrate, a step of etching the mask material until the insulating film covering the gate electrode is exposed, and impurity ions
This is achieved by providing a method for manufacturing a MOS transistor, which comprises the steps of introducing into the drain diffusion region and the gate electrode and further diffusing it in this order. In particular, it is preferable that the mask material is made of a polysilicon material, and that the method further includes a step of patterning the mask material to form electrodes and / or wirings of source / drain diffusion regions after the impurity ion introduction and diffusion steps.

[0009]

[Function] The mask material is etched until the insulating layer covering the upper part of the gate electrode is exposed, so that even if impurities are introduced and diffused so that the junction depth of the source / drain diffusion region becomes shallower at the same time, the gate material is simultaneously etched. Impurities are preferably diffused into the electrode. If polysilicon is used as the mask material, the source / drain electrodes and / or the wiring can be formed by patterning the mask material without removing it.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 (a) to 1 (e) are sectional views showing an essential part of a method of manufacturing a p-type MOS transistor according to the present invention. In the present embodiment, only the manufacturing process of the p-type MOS transistor will be described, and the n-type MOS transistor is the same as the p-type MOS transistor, so detailed description thereof will be omitted.

First, as shown in FIG. 1A, after forming an element isolation region (LOCOS) 2 on a substrate 1, an insulating film 3 and a gate electrode 4 made of a conductive thin film are formed, and thereafter, insulation is performed. An insulating film 6 is formed so as to cover the sidewall spacers 5 made of a body and the upper portions of the gate electrodes 4.

Next, a polysilicon film 7 as a mask for introducing impurities is formed on the entire surface of the substrate 1 by the CVD method or the like (FIG. 1B). Then, as shown in FIG. 1C, etching is performed until the insulating layer 6 covering the upper portion of the gate electrode 4 is exposed. After that, impurity ions are introduced into the polysilicon film 7 (FIG. 1D), and the impurity ions are diffused by thermal diffusion to form the source / drain regions 8, and at the same time, the gate electrode 4 is replaced with the source / drain regions 8. The same conductivity type is used (FIG. 1 (e)). Here, the polysilicon film 7 used as a mask for reducing the junction depth is patterned in a later step and used as a source / drain electrode or a wiring (not shown). As a result, steps such as contact hole formation and buried plug formation, which are usually performed after forming the interlayer insulating film, can be omitted, and the wiring pattern forming step is facilitated.

[0014]

As is apparent from the above description, according to the method of manufacturing a MOS transistor of the present invention, a mask material is formed on a substrate on which a gate electrode and an insulating film covering the gate electrode are formed. After etching the mask material until the insulating film is exposed, impurity ions are introduced into the source / drain diffusion region and the gate electrode and further diffused so that the junction depth of the source / drain diffusion region becomes shallow. Even if impurities are introduced and diffused, at the same time, the impurities are suitably diffused in the gate electrode. Therefore, the impurities can be introduced into the source / drain diffusion region and the gate electrode made of the conductive thin film at the same time, so that the number of steps can be reduced and the working time can be shortened. Further, if polysilicon is used as the mask material, the source / drain electrodes and / or wiring can be formed by patterning the mask material without removing it, and the number of steps can be further reduced.

[Brief description of drawings]

1A to 1E are p-type MOs according to the present invention.
FIG. 9 is a cross-sectional view showing the main parts of the method for manufacturing the S transistor.

FIG. 2A to FIG. 2D are cross-sectional views showing a main part of a conventional general MOS transistor manufacturing method.

[Explanation of symbols]

 1 Substrate 2 Element Isolation Region 3 Insulation Film 4 Gate Electrode 5 Sidewall Spacer 6 Insulation Film 7 Polysilicon Film 8 Source / Drain Region 21 Substrate 22 Element Isolation Region 23 Insulation Film 24 Gate Electrode 25 Sidewall Spacer 26 Insulation Film 27 Polysilicon Film 28 Source / drain diffusion region

Claims (2)

[Claims] 1. A process of forming a gate electrode made of a conductive thin film and an insulating film covering the upper part of the conductive film on a substrate, and a process of forming a mask material on the substrate on which the gate electrode and the insulating film are formed. A step of etching the mask material until the insulating film covering the gate electrode is exposed, and a step of introducing impurity ions into the source / drain diffusion regions and the gate electrode and further diffusing the ions. A method for manufacturing a MOS transistor, including: 2. The mask material is made of a polysilicon material, and further comprising a step of patterning the mask material to form electrodes and / or wirings of source / drain diffusion regions after the impurity ion introduction and diffusion steps. The method for manufacturing a MOS transistor according to claim 1, wherein