JPH0745724A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor storage device which is enhanced in reliability by a method wherein an insulating film is restrained from deteriorating due to a write/erase operating characteristic. CONSTITUTION:An insulating film 17 includes a semi-insulating polysilicon layer 14a (SIPOS layer) composed of silicon oxide and polysilicon. The insulating film 17 is of three-layered structure and composed of a lower insulating film 12a on a P-conductivity type semiconductor substrate 10, an intermediate insulating film 14a, and an upper insulating film 16a, wherein the intermediate insulating film 14a is an SIPOS layer. Furthermore, the lower and the upper insulating film, 12a and 16a, are formed of silicon dioxide (SiO2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device (so-called EEPRO) which can be electrically written and erased and which does not require external power supply to retain information.
M).

[0002]

2. Description of the Related Art A conventional non-volatile semiconductor memory device is disclosed in, for example, Document I (Document I: "Effect of temperature").
atur on data retention of
silicon-oxide-nitride-ox
idea-semiconductor nonvola
till memory transistor
s ", S.S. L. Miller at al, J, App
1, Phys, 67 (11), 1 June 199.
0) and Document II (Document II: “MONOS-type EEPR”).
OM ", Monthly Semiconductor Director World
d, Toshiyuki Kishi et al., 1991.4).

FIGS. 6A and 6B show an example of the structure of the nonvolatile memory device disclosed in Documents I and II.

According to the structure of FIG. 6A, 30 is a p-conductivity type semiconductor substrate, 32 is a tunnel oxide film, 34 is a nitride film, 36 is a top oxide film, 38 is an n ⁺ conductivity type gate electrode, 42 is an n ⁺ type source region, and 44 is an n ⁺ type drain region.

An n ⁺ conductivity type source region 42 and drain region 44 are formed on the surface of the substrate 30.
A tunnel oxide film 32, a nitride film 34, a top oxide film 36, and a gate electrode 38 are stacked on the gate electrode 0.

On the other hand, the non-volatile semiconductor device of the type of Document II is a memory cell compatible with a highly integrated IC.

The structure of the highly integrated IC compatible memory cell disclosed in the literature will be briefly described with reference to FIG.

The structure of this highly integrated IC compatible memory cell is as follows. 50 is a p-well, 52 is an n-type semiconductor substrate, 54 is a gate oxide film, 56 is an address gate, 5
8 is ONO (Oxide-Nitride-Oxid)
e) film, 60 is a memory gate, 64 and 66 are field oxide films, 68a and 68b are n ⁻ conductivity type diffusion layers, 70
Reference numerals a and 70b are n ⁺ conductivity type diffusion layers.

Next, a method of operating a memory cell using the nonvolatile semiconductor memory device (hereinafter referred to as EEPROM) shown in FIG. 6A will be briefly described.

The writing operation of this EEPROM is performed by injecting electrons accumulated from the drain region 44 at the interface between the tunnel oxide film 32 and the nitride film 34. When a large number of electrons are accumulated at this interface, the channel does not invert, so that no electrons flow in the channel region 43. At this time, an enhancement state (a state in which the drain current does not flow when the gate electrode voltage is 0V) is set, the threshold voltage increases, and the state becomes an OFF state (“0” state). The top oxide film 36 functions as a barrier against the injected electrons to prevent the electrons from being emitted to the gate electrode 38 side.

On the other hand, the erasing is performed by releasing the electrons trapped in the nitride film 34 and the tunnel oxide film 32 to the substrate 30 side. That is, the channel is inverted by releasing the electrons accumulated at the interface between the tunnel oxide film 32 and the nitride film 34 to the source region 42 of the substrate 30. At this time, the threshold voltage decreases and the ON state (“1” state) is set.

As described above, the writing and erasing of the conventional EEPROM are performed by injecting and releasing the electrons trapped at the interface between the nitride film 34 and the tunnel oxide film 32 (hereinafter referred to as the trap layer). It was

[0013]

However, in the above-mentioned conventional nonvolatile memory device, since the nitride film is deteriorated by repeating the electron injection into the trap layer and the electron emission from the trap layer, the electron injection efficiency is increased. Of the threshold voltage, and thus the fluctuation of the threshold voltage (V _th ) becomes large. Further, the deterioration of the nitride film increases the leak current, making it impossible to hold the charges accumulated in the trap layer, which causes deterioration of device characteristics. Also,
There is also a problem that the strength of dielectric breakdown is lowered due to the deterioration of the nitride film.

The present invention has been made in view of the above-mentioned problems, that is, an object of the present invention is to suppress deterioration of an insulating film due to operating characteristics of writing and erasing and to provide a highly reliable nonvolatile semiconductor. A storage device is provided.

[0015]

In order to achieve this object, according to the configuration of the nonvolatile semiconductor memory device of the present invention, a nonvolatile memory having an insulating film on a base and a gate electrode on the insulating film is provided. In the conductive semiconductor memory device, the insulating film is
It is characterized by including a semi-insulating polysilicon layer composed of a composition of silicon dioxide (SiO ₂ ) and polysilicon.

Further, in carrying out the present invention, preferably, the insulating film is a laminated structure of a lower insulating film, an intermediate insulating film and an upper insulating film on a base, and the intermediate insulating film is a semi-insulating polysilicon layer. It is good to

Further, in carrying out the present invention, preferably, the lower and upper insulating films are formed of silicon dioxide (Si).
It is preferable to use an O ₂ ) layer.

Further, the first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate
A second conductivity type first and second impurity regions provided on an upper surface of the conductivity type semiconductor substrate; and at least the first and second impurity regions provided on the first conductivity type semiconductor substrate. A first insulating film in contact with a part, a second insulating film provided on the first insulating film, a third insulating film provided on the second insulating film, and a third insulating film on the third insulating film A non-volatile semiconductor memory device including at least a conductive layer provided in the semiconductor device, wherein the second insulating film is formed of a semi-insulating polysilicon layer having a composition of silicon dioxide and polysilicon. To do.

In implementing the present invention, preferably, the first and third insulating films are formed of silicon dioxide (Si).
It is preferable to use an O ₂ ) layer.

[0020]

According to the above-mentioned nonvolatile semiconductor memory device, the insulating film includes a semi-insulating polysilicon (hereinafter referred to as SIPOS) layer having a composition of silicon dioxide (SiO ₂ ) and polysilicon. And Regarding SIPOS, reference III (reference III:
"An Advanced MOS-IC Proce
ss Technology Using Local
Oxidation of Oxygen-Dope
d Polysilicon Films ", IEEE
E, JOURNAL OF SOLID-STATE
CIRCUITS, VOL. SC-13, No. 4, A
There is an example disclosed in UGUST, 1978, P472), but it is clear that it shows semiconductivity, but its composition is not yet clear.

Since many electron trap sites exist in such a SIPOS region, silicon (S
i) SIP electrons injected from the substrate side into the SIPOS layer
It can be sufficiently accumulated in the OS layer. Furthermore, by setting the gate electrode to a negative potential, the electrons accumulated in the SIPOS layer can be easily emitted to the silicon substrate side. A detailed description of this reason will be given later. Therefore, the conventional EEPROM
It can be expected that the number of rewriting operations will be improved as compared with. Further, since the deterioration of the SIPOS layer due to the write operation is small, the leak current can be reduced and the strength of the dielectric breakdown can be increased.

Further, the insulating film has a three-layer laminated structure of a lower insulating film, an intermediate insulating film and an upper insulating film, and the intermediate insulating film is a semi-insulating polysilicon layer. By thus forming the three-layer structure of the insulating film, it is possible to stably inject and emit electrons into the SIPOS layer.

Further, it is preferable that the lower and upper insulating films are silicon dioxide (SiO ₂ ) layers. By using such a SiO ₂ layer, the electrons injected through the lower insulating film can be sufficiently trapped in the SIPOS layer.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile semiconductor memory device (hereinafter referred to as an EEPROM) according to an embodiment of the present invention is shown in FIG. 1, and an EEPROM forming method of the present invention is shown in FIGS. This will be described with reference to (D) and (A) to (C) of FIG. However, the respective drawings are merely schematic representations of the shapes, sizes, and arrangements of the respective constituents so that the present invention can be understood. In addition, each figure is EEPR
A part of the cross-sectional structure of the main part when cut at a right angle to the longitudinal direction of the OM is shown, but in an actual EEPROM, a large number of elements are arranged on a substrate.

FIG. 1 shows the EEPR of the first embodiment of the present invention.
It is sectional drawing which showed the main structure of OM.

First, as the first conductivity type semiconductor substrate 10, a p conductivity type semiconductor substrate (hereinafter referred to as a substrate) is used. This substrate 10 has, for example, a specific resistance of 3 Ω · cm to 5 Ω.
-Cm, the orientation of the crystal plane is the (100) plane. A first insulating film 12a, a first insulating film 14a, a third insulating film 16a and a conductor layer 18a are laminated on the substrate 10, respectively. Further, the surface of the substrate 10 is provided with a first impurity region 20 and a second impurity region 22 of the second conductivity type. Note that here, the first, second, and third insulating films 12a, 14 are formed.
The a and 16a are collectively referred to as an insulating film 17.

Next, referring to FIGS. 2 (A), (B), (C) and (D) and FIGS. 3 (A), (B) and (C), manufacture of the embodiment of the present invention. The steps will be described. The thin film forming apparatus used in this example is a CVD (chemical vapor deposition) apparatus (not shown).

First, impurities adhering to the substrate 10 are removed from the substrate 10 by using any suitable cleaning liquid. afterwards,
The cleaned substrate 10 is immediately loaded into any suitable reaction furnace (not shown).

After that, oxygen gas is introduced into the reaction furnace and heated at about 900 ° C. for 5 minutes to form the first insulating film 12 on the substrate 10 ((A) of FIG. 2). This first insulating film 1
2 is also referred to as a tunnel oxide film. This tunnel oxide film 1
2 is formed of, for example, SiO ₂ and has a film thickness of, for example, about 2 nm
(Nanometer).

Subsequently, the structure shown in FIG. 2B is immediately placed in the thin film forming CVD apparatus. Then, in the reaction furnace, for example, silane (SiH ₄ ) gas, dinitrogen monoxide (N
A mixed gas containing ₂ O) gas and nitrogen (N ₂ ) gas is introduced. At this time, the flow rate ratio of N ₂ O and SiH ₄ is set to, for example, 2: 1 and the heating temperature is, for example, about 600 ° C. and the heat treatment is performed for about 10 minutes. At this time, the second insulating film 14 is formed ((B) of FIG. 2). The second insulating film 14 is formed of a semi-insulating polysilicon layer (also referred to as SIPOS layer) made of a composition of silicon dioxide and polysilicon. Moreover, the film thickness of the SIPOS layer 14 is, eg, about 10 nm.

Then, after the supply of silane (SiH ₄ ) gas, dinitrogen monoxide (N ₂ O) gas and nitrogen (N ₂ ) gas was stopped, the structure of FIG. 2B was cooled to room temperature. Let

Then, after the sample is loaded into the oxide film forming apparatus, a mixed gas of oxygen (O ₂ ) gas and hydrogen (H ₂ ) gas is introduced into the reaction furnace, and the heating temperature is set to, for example, 950 ° C.
The third insulating film 16 is formed by a heat treatment for about 10 minutes ((C) in FIG. 2. The third insulating film 16 formed at this time)
Is called a top oxide film. The thickness of the top oxide film 16 at this time is about 4 nm.

Next, the structure of FIG. 2C is immediately loaded into a thin film forming CVD apparatus (not shown), and silane (SH ₄ ) gas and phosphine (PH ₃ ) gas are introduced into the furnace. It is introduced after adjusting the flow rate to a predetermined value, and the heating temperature is, for example, about 63.
Heat treatment is performed at 0 ° C. for 10 minutes. At this time, the conductive layer 18 is formed on the top oxide film 16 ((D) of FIG. 2). This conductive layer 18 is also referred to as a gate electrode preliminary layer. The preliminary layer 18 for gate electrode is doped with phosphorus (P).

Next, a mask material is applied on the preliminary layer 18 for the gate electrode using any suitable mask material, and then a photolithography method and etching are performed to form a resist pattern 19 ((A) of FIG. 3). ).

Next, any suitable anisotropic etching is performed to first etch the preliminary layer 18 for the gate electrode to obtain the structure shown in FIG. 3 (B). 18a formed at this time is called a gate electrode.

Next, the gate electrode 18a is masked by using any suitable method, and the top oxide film 16 and the SIPOS layer 1 are formed by using, for example, a photo etching method or a dry etching method.
4 and the tunnel oxide film 12 are etched respectively.
In this way, the structure of FIG. 3C is obtained. The 12a, 14a, and 16a formed at this time are referred to as a tunnel oxide film, a SIPOS layer, and a top oxide film, respectively.

Next, the tunnel oxide film 12a, SIPOS
After masking the layer 14a and the top oxide film 16a by any suitable method, for example, arsenic (As) is ion-implanted to form an n ⁺ conductivity type source region 20 and drain region 22 on the surface of the substrate 10 (FIG. 3). (C)).

Through the manufacturing steps described above, the main part structure of the nonvolatile semiconductor memory device is formed.

Next, a situation in which electrons are trapped during the write and erase operations will be described with reference to the energy band schematic diagram of FIG.

FIG. 4A shows the energy band state of the write operation, and there are many electron trap sites 101 in the SIPOS region. By increasing the potential of the silicon substrate side 104, the electrons 102 pass from the substrate side through the SiO ₂ region 107 to the SIPOS region 1.
05 is captured by the electron trap site 101. on the other hand,
FIG. 4B shows the state of the energy band of the erase operation. When a negative potential is applied to the gate electrode side 106, the electrons 10 trapped in the SIPOS region 105 are shown.
2 is easily released to the silicon electrode side 104.

Next, the hysteresis characteristic of the EEPROM formed in the embodiment of the present invention will be described with reference to FIG. In the figure, the horizontal axis represents the gate voltage (V _g ) and the vertical axis represents the threshold voltage (V _th ).

As can be understood from FIG. 5, in the written state (w curve), the threshold voltage becomes about 1.8V,
In the erased state (e curve), it becomes about -1.8V. As in the embodiment of the present invention, the insulating film is formed of SiO ₂ / SIPOS / Si.
The applicants have confirmed through experiments that the change in the hysteresis characteristic is small even if the number of times of rewriting is increased by adopting a three-layer structure of O ₂ .

As described above, since the deterioration of the SIPOS layer is small even when the writing and erasing operations are performed, it is possible to expect a decrease in leak current and an increase in the strength of dielectric breakdown.

According to the above-described embodiment of the present invention, the crystal plane of the substrate 10 is the (100) plane, but the crystal plane is not limited to this and may be another crystal plane.

[0045]

As is apparent from the above description, according to the structure of the nonvolatile semiconductor memory device of the present invention, the insulating film is a semi-insulating polysilicon layer (composition of silicon dioxide and polysilicon). Hereinafter, it will be referred to as a SIPOS layer). By forming such a SIPOS layer, a large number of electron traps (trap sites) exist in the SIPOS region, so that injection and emission of electrons from the substrate side can be extremely facilitated. Further, the insulating film has a three-layer laminated structure including a lower insulating film, an intermediate insulating film, and an upper insulating film, and the intermediate insulating film is a SIPOS layer. Therefore, injection of electrons into the SIPOS region and emission of electrons from the SIPOS region can be extremely facilitated. Even if the number of write operations is increased, S due to injection and emission of electrons
Little deterioration of the IPOS layer. Therefore, the leak current of the insulating film is reduced, and the strength of dielectric breakdown can be increased. Also,
When the lower and upper insulating films are made of silicon dioxide (SiO ₂ ) layers, it becomes easy to sufficiently capture and release the electrons injected into the SIPOS layer through the lower insulating film. Therefore, it can be expected that the number of times of rewriting of EEPROOM will be significantly increased.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an EEPROM structure according to an embodiment of the present invention.

2 (A) to (D) are process drawings provided for explaining a manufacturing process of an embodiment of the present invention.

3 (A) to 3 (C) are process drawings provided for explaining the manufacturing process of the embodiment of the present invention following FIG.

FIGS. 4A to 4B are schematic diagrams provided for explaining changes in energy band during writing and erasing according to the present invention.

FIG. 5 is a hysteresis graph of an embodiment of the present invention.

6A and 6B are cross-sectional views of a conventional nonvolatile memory device.

[Explanation of symbols]

10: p conductive type semiconductor substrate 12a: tunnel oxide film (SiO ₂ film) 14a: SIPOS layer 16a: top oxide film (SiO ₂ film) 17: insulating film 18: preliminary layer for gate electrode 18a: gate electrode 19: resist pattern 20: source region 22: drain region 101: electron trap site 102: electron 103: SiO ₂ region 104: silicon substrate 105: SIPOS region 106: gate electrode 107: SiO ₂ region

Claims (5)

[Claims] 1. A non-volatile semiconductor memory device comprising an insulating film on a lower surface and a gate electrode on the insulating film, wherein the insulating film is made of a composition of silicon dioxide (SiO ₂ ) and polysilicon. A non-volatile semiconductor memory device comprising an insulating polysilicon layer. 2. The insulating film according to claim 1, which has a laminated structure of a lower insulating film, an intermediate insulating film, and an upper insulating film on the base, and the intermediate insulating film is the semi-insulating polysilicon layer. And a nonvolatile semiconductor memory device. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the lower and upper insulating films are made of silicon dioxide (Si).
A non-volatile semiconductor memory device having an O ₂ ) layer. 4. A semiconductor substrate of a first conductivity type, first and second impurity regions of a second conductivity type provided on an upper surface of the semiconductor substrate of the first conductivity type, and the semiconductor substrate of the first conductivity type. A first insulating film provided on the first insulating film and in contact with at least part of the first and second impurity regions; a second insulating film provided on the first insulating film; and a second insulating film A nonvolatile semiconductor memory device comprising at least a third insulating film provided on the third insulating film and a conductive layer provided on the third insulating film, wherein the second insulating film is composed of silicon dioxide and polysilicon. A non-volatile semiconductor memory device comprising a semi-insulating polysilicon layer made of. 5. The non-volatile semiconductor memory device according to claim 4, wherein the first and third insulating films are made of silicon dioxide (Si).
A non-volatile semiconductor device having an O ₂ ) layer.