JPH0743420A - Inspection device for multi-pin semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the measuring of a multi-pin semiconductor integrated circuit by eliminating an increase in the number of pin electronics without providing components on a test board. CONSTITUTION:An electronics 5 has a driver circuit to supply an arbitrary signal to an LSI12 to be measured and a comparator circuit to judge a signal from the LSI12 to be measured and pattern memories 1 and 2 store logic values of signals to be applied to the pin electronics 5. In a first matrix circuit 3, arbitrary separate pins are connected between the pattern memories 1 and 2 and the electronics 5 and in the second matrix circuit 7, arbitrary separate pins are done between a test board 9 and the pin electronics 5. A pin table memory 6 stores a data corresponding to the pins to determine the connection of individual matrixes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for testing electrical characteristics and functions of a multi-pin semiconductor integrated circuit device.

[0002]

2. Description of the Related Art FIGS. 4 and 5 show a conventional multi-pin measuring device using a relay system (Japanese Utility Model Laid-Open No. 1-160376).
FIG. 4 is related to the pin electronics (hereinafter,
FIG. 3 is a model cross-sectional view showing connections of a PE, a relay, a test board, and a semiconductor integrated circuit device (hereinafter, referred to as an LSI). Further, FIG. 5 is a configuration diagram showing electrical connection. In FIG. 4 and FIG. 5, 21 is the LSI to be measured,
22 is PE, 23 is test board, 24 is relay, 25
Is a socket. Further, 26 is a driver, 27 is a comparator, and 28 is a control signal for switching the relay. Further, 29 is a pogo pin. Here, even if the switch circuit formed of a semiconductor is used instead of the relay 24, it is functionally equivalent. Then, on the test board 23, a signal transmission pattern for electrically connecting the PE 22 and the relay 24 is formed in advance, and is connected via the pogo pin 29. In addition, relay 2
A signal pattern is also formed between 4 and the socket 25. It is equivalent to connect with a wire material that transmits an electric signal such as a cable instead of the signal transmission pattern.

Next, the operation will be described. When testing the LSI to be measured 21 in the inspection apparatus, the PE 22 of the inspection apparatus and the pins of the LSI to be measured 21 are connected one to one. At this time, in the test board 23, the socket 2
5 is attached, and the signal pattern described above is connected to each pin terminal of the socket 25. In the following description, it is assumed that the socket 25 is an auxiliary jig for mounting the LSI to be measured 21, and the socket 25 is omitted and is directly connected to the LSI to be measured 21. Similarly, the pogo pin 29 is also omitted.
Here, when the number of pins of the LSI to be measured 21 is the same as or smaller than the number of PEs 22, the LSI to be measured 21 and the PE 22 are connected via the signal pattern without the relay 24, and the driver on the PE 22 is connected. It is possible to apply the signal from 26 or to judge the signal from the LSI to be measured 21 by the comparator 27 to perform the test. Further, in general, the number of pins of the LSI to be measured includes a power supply and a ground terminal. Therefore, each of them has a reference voltage source such as a power supply other than PE, or an external power supply prepared separately from the inspection device. Since it is connected to, it is possible to test up to the LSI to be measured having a pin number slightly larger than PE.

However, compared to the number of PEs, the measured L
When the number of SI terminals is extremely large, as shown in FIGS. 4 and 5, the PE 22 and the LS to be measured are connected via the relay 24.
The test is conducted by connecting I21 and switching the relay by the control signal 28. Now, the LSI to be measured 21
Pins 13 and 14 on one PE and 23 and 24 on another
If it is connected to two PEs, in the first test, the pins 13 and 23 are electrically connected to the PEs, respectively, and the pins 14 and 24 are electrically disconnected. Then, when the first test is completed, the relay 24 is switched by the control signal 28 as the second test, and this time, the pins 14 and 24 are electrically connected to PE, respectively, and the pins 13 and 23 are cut off. , The test is completed by conducting the test.

[0005]

In the conventional inspection apparatus, a relay is provided on the test board and a multi-pin LSI can be tested by switching the relay. However, the size of the test board is large. There is a problem that the number of relays that can be mounted is limited, and an LSI having an extremely large number of pins cannot be measured. Furthermore, it is necessary to form a signal pattern in consideration of switching on the test board in advance.
There is a drawback that a common test board for each package cannot be used for / A. Moreover, it is necessary to supply a signal for controlling the relay for each relay, and further, there is a limitation on the position of the relay mounted on the test board and the signal pattern.

Further, simply increasing the number of pin electronics cards (hereinafter referred to as PE cards) as an extension of the conventional technique increases the system price and also increases the size of the test head. Redesign is required and not practical. In particular, in a high-performance inspection device called a per-pin system, which has a timing system for each pin, the system price increases in proportion to the number of pins, and the ratio of the pin electronics part to the system price is about 30%. Occupy

An object of the present invention is to solve the above-mentioned drawbacks and problems. Even if the signal pattern of the test board is constant, no relay is provided on the test board. The purpose is to realize a low-cost inspection device capable of supplying an arbitrary signal to an arbitrary pin.

[0008]

The present invention provides a pin electronics card having a driver circuit for supplying an arbitrary signal to a semiconductor integrated circuit mounted on a test board and a comparator circuit for judging a signal from the semiconductor integrated circuit.
A first test pattern memory for storing a logic value of a signal to be applied to the pin electronics card; a first matrix circuit for connecting the first test pattern memory and arbitrary pin numbers of the pin electronics card; A second matrix circuit that connects arbitrary pin numbers of the test board and a pin table memory that stores the pin numbers of the first test pattern memory, the pin electronics card, and the test board are stored in the pin table memory. The first test pattern memory and the pin electronics card are connected through the first matrix circuit by the pin number on the first test pattern memory and the pin number on the pin electronics card, and the pin electronics stored in the pin table memory are connected. B is characterized by connecting the pin electronics card and the test board by a pin number on the pin numbers and the test board on Nix card through the second matrix circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a first inspection device according to the present invention.
It is a block diagram which shows the Example of. In FIG. 1, reference numerals 1 and 2 denote a first pattern memory, and a first pattern memory 1
Is a memory for storing logical values to be supplied to the PE driver circuit and the comparator circuit of 1 to n pins, and the first pattern memory 2 is a memory for storing logical values corresponding to pins of n + 1 to 2n. Is a first matrix circuit that distributes information in the first pattern memories 1 and 2 to PEs,
4 is a PE card on which a plurality of PEs are mounted, 5 is a PE, 6
Is a pin table memory, 7 is a second matrix circuit for distributing signals from the PE 5 to the test board, 8 is a pogo pin for electrically connecting to the test board, 9 is a test board, and 10 is formed on the test board 9. Electrically conductive signal pattern, 11 is socket, 12 is LS to be measured
I and 13 are logical value data from the pattern memory, 14 is logical value data distributed by the first matrix circuit 1,
Reference numeral 5 is a control signal for controlling the first matrix circuit 3 to connect the first pattern memories 1 and 2 to the PE 5, and 16 is also controlling the second matrix circuit 8 to connect the PE card 4 and the test board 9. The control signal 17 is a signal from PE5.

FIG. 2 shows, as the first pattern memory 1,
This is an example of the case where the first and second pins are assigned to the third and fourth pins as the first pattern memory 2, and the case where the matrix is composed of the switch circuit here. Although this switch circuit may be configured by a relay or the like, it is generally formed by a semiconductor switch circuit because it is necessary to increase the packaging density.
Here, the data of the pattern memory (see Table 1) is supplied to the PE 5 via the first matrix circuit 3 and controls the output state and the input state of the PE 5. The PE 5 is composed of a driver circuit and a comparator circuit and supplies a signal of "1" or "0" to the test board 9 via the pogo pin 8 in accordance with the logical value data 14 or an LSI to be measured.
In response to the signal from 12, the comparator circuit
It is determined as "1" or "0". The test board 9
The test boards 9 are connected by the pogo pins 8, and the test board 9 can be freely designed and replaced according to the number of pins of the LSI 12 to be measured. A socket 11 is connected to the test board 9 by an electrically conductive signal pattern 10 or signal line.

[0011]

[Table 1]

Here, in a normal state where the pins 1 and 2 are used (state of # 1 of the pin table memory 6: 1; ON,
2; ON, 3; OFF, 4; OFF), and in the first matrix circuit 3, the switch circuits A and B are selected.
As a result, the data in the first pattern memory 1 is supplied to the PE card 4. Similarly, in the second matrix 7, the switch circuits G and J are selected, and the PE 5 and the test board 9 are selected.
Are connected via the pogo pin 8 and a signal is supplied to the LSI to be measured 12, or a signal from the LSI to be measured 21 is compared and judged.

Next, assuming that the pin number 3 is selected instead of the pin number 2, the state of the pin table memory 6 is
(# 2: 1; ON, 2; OFF, 3; 2, 4; OFF)
, Switch circuits A and E are selected, and G and I are selected in the same manner.
Is selected. All other switch circuits are non-conductive.
As a result, the pattern data of the pin 1 and the pin 3 is supplied to the PE 5, and further the signal is supplied to the LSI under test 12 via the second matrix 7 and the pogo pin 8, or the signals from the LSI under test 12 are compared and judged. .

As described above, by using the pin 2 and the pin 3, the pin 1 and the pin 4, and the like in combination, the test can be performed as if the tester has the pins 1 to 4.

Next, a second embodiment of the present invention will be described. FIG. 3 is a configuration diagram showing a second embodiment of the inspection apparatus of the present invention. In FIG. 3, reference numeral 18 is a second pattern memory for temporarily storing the data of the first pattern memories 1 and 2. Further, 19 is provided instead of the first matrix circuit 3 in the first embodiment.

Here, as in the first embodiment, the second pattern memory 18 is selected according to the data written in the pin table memory 6, and the first pattern memories 1 and 2 are selected.
Is transferred via the bus 19 and stored in the second pattern memory 18. Further, the second matrix circuit 7 is connected to the LSI to be measured 12 via the pins of the predetermined test board 9 and the pogo pins 8 in the same manner as in the first embodiment, and the signal is supplied to the LSI to be measured 12 or the LSI to be measured is supplied. The signal from the measurement LSI 12 is compared and judged.

By providing the second pattern memory 18 in the PE 5 as described above, the first matrix circuit is unnecessary, the modification of the inspection apparatus main body is minimized, and the multi-pin LSI can be determined. .

As described above, in the inspection apparatus according to the present invention, the conventional inspection apparatus has the relay on the test board and the PEs are connected to the pins of the plurality of LSIs, whereas the pattern memory and the PEs are connected to each other. A first matrix circuit (generally a switching circuit using semiconductor elements) for connecting arbitrary pins to each other is provided, and a second matrix circuit (general for connecting each arbitrary pin to each other between the test board and the PE). In particular, a relay circuit) and a pin table memory that determines the connection of each matrix are provided.

Further, in the conventional inspection apparatus, the signal from the PE is switched in accordance with the signal pattern formed on the test board in advance.
Any PE can be connected to the LSI without being restricted by the signal pattern on the test board.

Furthermore, the data of the test pattern is supplied to an arbitrary PE by the first matrix, and as a result, the signal supplied to the LSI to be measured can be changed even if the connection from the PE to the LSI remains constant. Yes, and each control can be performed by the contents of the pin table memory.

[0021]

According to the present invention, signals can be switched and exchanged without providing a component such as a relay on a test board, and a multi-pin LSI can be measured. Therefore, by connecting the necessary pins according to the test and dividing the test into multiple times, it is possible to measure a multi-pin LSI, and especially, to change the input pins of the LSI under test without changing the output pins. By dividing, it becomes possible to easily measure a multi-pin LSI.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an inspection apparatus of the present invention.

FIG. 2 is a detailed view of the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment of the inspection apparatus of the present invention.

FIG. 4 is a schematic cross-sectional view of a conventional relay-type multi-pin measuring device.

FIG. 5 is a configuration diagram showing electrical connection of a conventional multi-pin measuring device.

[Explanation of symbols]

 1, 2 1st pattern memory 3 1st matrix circuit 4 pin electronics card (PE card) 5 22 pin electronics (PE) 6 pin table memory 7 2nd matrix circuit 8 29 Pogo pin 9 23 Test board 10 Signal pattern 11,25 Socket 12,21 LSI to be measured 13,14 Logical value data 15,16,28 Control signal 17 Signal from pin electronics 18 Second pattern memory 19 Bus 24 Relay 26 Driver 27 Comparator

Claims (3)

[Claims] 1. A pin electronics card having a driver circuit for supplying an arbitrary signal to a semiconductor integrated circuit mounted on a test board and a comparator circuit for determining a signal from the semiconductor integrated circuit, and a signal to be applied to the pin electronics card. A first test pattern memory that stores a logical value, a first matrix circuit that connects the first test pattern memory and arbitrary pin numbers of the pin electronics card, and arbitrary pin numbers of the pin electronics card and test board A second matrix circuit for connecting to each other and a first test pattern memory, a pin table memory for storing pin numbers of the pin electronics card and the test board, respectively, and a first test pattern memory stored in the pin table memory. Pin number and pin above The first test pattern memory and the pin electronics card are connected to each other through the first matrix circuit according to the pin number on the pin electronics card, and the pin number on the pin electronics card and the pin number on the test board stored in the pin table memory. The multi-pin semiconductor integrated circuit testing device is characterized in that the pin electronics card and the test board are connected via the second matrix circuit according to. 2. The inspection apparatus for a multi-pin semiconductor integrated circuit according to claim 1, wherein the first matrix circuit and the second matrix circuit are composed of semiconductor switch circuits in the matrix, and the arbitrary pin numbers are assigned to each other. An inspection device for a multi-pin semiconductor integrated circuit, which is characterized by being connected. 3. The inspection apparatus for a multi-pin semiconductor integrated circuit according to claim 1, wherein the first matrix circuit is omitted, and the first matrix circuit is selected according to the data written in the pin table memory on the pin electronics card. An inspection apparatus for a multi-pin semiconductor integrated circuit, comprising a second test pattern memory for storing data of the test pattern memory.