JP2974984B2 - Circuit device testing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for performing a circuit test of a circuit device including a programmable logic element whose logic circuit configuration can be externally rewritten by a program.

[0002]

2. Description of the Related Art An example of a programmable logic element is an FPGA (Field Programmable Gate Array). The FPGA includes an array of AND and OR elements. By applying a predetermined current pulse from a terminal to blow an intersection of an array-like wiring, a desired logic circuit configuration is programmed in a chip. can do. Although it is difficult to rewrite the contents once written in the type in which the wiring is blown, there is another type having a configuration in which rewriting can be performed electrically repeatedly using a floating gate or the like.

As a prior art of a circuit test method for testing a circuit device including a rewritable FPGA, there is an "arithmetic logic diagnostic device" disclosed in Japanese Patent Application Laid-Open No. Hei 7-198784. This will be described below. FIG.
FIG. 1 is a general block configuration diagram of a basic logic block configuring the inside of an FPGA device. The basic logic block 2 receives at least one input signal 4 and outputs an output signal 6. In the basic logic block 2, a logical operation “x” is performed based on the values “a”, “b”, and “c” of the input signal 4.
= F (a, b, c) ". The output x of the logic cell 8 is supplied to the register 10 and the selector 12
Passed to. The selector 12 receives the output of the logic cell 8 directly passed from the logic cell 8 and the output of the logic cell 8 once held in the register 10, selects one of them, and selects one of them. Output as output signal 6. The configuration shown in FIG. 13 is a general type, and there may be a configuration in which the register 10 and the selector 12 are not actually included.

FIG. 14 shows such a basic logical block 2
FIG. 1 is a schematic circuit configuration diagram of an example of an FPGA configured to include nine. The figure shows that the FPGA 20 is composed of nine basic logical blocks 2 in three columns and three rows separated by dotted lines. The prior art described here is
The original circuit incorporates a scan register to identify a failure location. FIG. 15 is a schematic circuit configuration diagram of an example of an FPGA having a built-in scan register. In the prior art, when programming the FPGA, a correction process for incorporating the scan register 30 is performed based on the circuit information of the original circuit, and the scan register 30 is executed.
Is generated. Then, the FPGA is programmed based on the generated circuit information.
The scan register 30 is connected to the signal terminal 3 of the FPGA 20.
2, 34 are connected in a chain. These scan registers 30 are used to temporarily hold the operation results of each basic logic block 2 and observe them outside the FPGA. The scan register 30 includes, for example, a signal terminal 32
, A value specified by a control signal is set, or a value is read to the signal terminal 34.

By arranging the scan register 30 between the basic logic blocks 2 in this manner, a known value is set in the scan register 30 on the input side of each basic logic block 2 and the output of the basic logic block 2 corresponding thereto is set. Can be observed by the scan register 30 on the output side. That is, this makes it easy to specify a failure location in the FPGA.

An input / output data pattern which can detect a single stuck-at fault where only one fault location exists on the signal path of the circuit is, for example, an ATPG (Auto Test Pattern).
Generator). The algorithm of the ATPG is described in, for example, Makoto Watanabe, edited by "Super LSI Design", Planning Center Co., Ltd .: Published (1983), p. 198-
207.

FIG. 16 is a flowchart showing the procedure of the above-described conventional circuit test method. First, a scan register is inserted on the output side of each basic logic block 2 constituting the original circuit (S100) shown in FIG. 14 (S102), and a second circuit is obtained (S104).

In this scan register, since the output result of each basic logic block can be observed, this scan register can be regarded as a pin for observing an output value. Therefore, conversion that regards the scan register as a pin is performed on the circuit configuration information (S10).
6), the circuit configuration information of the third circuit is obtained (S108).
For the third circuit, a test pattern is generated assuming a single stuck-at fault (S110), and the input test data (S
112) and its expected value (S114).

The circuit configuration information of the second circuit into which the register has been inserted is written to the FPGA (S116). The input test data is set in the register of the FPGA (S118), and the logical operation is advanced by one clock (S12).
0). As a result, the output data is stored in the register and read out (S122). The output data is compared with the expected value (S124). If they do not match, a failure exists for the basic logical block (S126). Steps S118 to S124 are repeated as long as the input data remains (S128), and the test ends when there is no more input data (S130). According to the above-described conventional method, it is possible to specify a failure location inside the FPGA.

[0010] In another conventional technique, a specific element on a substrate on which a plurality of elements are arranged is set as an element to be tested. In this method, a probe needle is arranged and brought into contact with a wiring around the element to be tested which is connected to a signal terminal of the element to be tested, and a signal for a test is input / output via the probe needle. This includes, for example, a method of adjusting the position of the probe needle for each terminal, and a method using a probe card that is often used when performing many tests in which the arrangement of signal terminals is the same. In the latter probe card, since the probe needles are attached to a single substrate in advance according to the signal terminal arrangement of the device under test, the labor for adjusting the position of the probe needles is reduced.

As other conventional techniques for performing a circuit test on a substrate on which a plurality of elements are arranged, there are a method of performing a function test on the entire substrate and a method of performing a test by a boundary scan method. Among them, the former is to input various test patterns that can be considered for all the elements on the substrate of the circuit device, and to specify a failure location by the output. In the latter boundary scan method, a test pattern is input and its output is taken out via a scan register or the like arranged as close as possible to a device under test.

Also, a failure external to the FPGA, ie, an FP
As a conventional technique related to detection of a defect of a substrate wiring to which a GA is attached, there is a “continuity test method” disclosed in Japanese Patent Application Laid-Open No. 60-167554. This continuity test method is for finding a fault location that can occur in a communication path for each service call of the time division exchange.
A can be applied.

FIGS. 17 and 18 are schematic configuration diagrams of a transmission system for explaining the continuity test method. In the figure, individual terminating circuits 40a and 40b include data used by subscriber telephones 42a and 42b related to various lines,
This is a device for converting a signal suitable for a transmission method applied to a transmission line. Continuity test function units 48a and 48b are provided in the individual termination circuits 40a and 40b, respectively. Communication terminal interfaces 44a and 44b are provided between the individual terminating circuits 40a and 40b and the transmission line, thereby performing a predetermined protocol conversion. An exchange exists on the transmission line, and the individual termination circuits 40a and 40b are connected to each other via time switches 46a to 46c of the exchange.

The subscriber telephone set on the service calling side and the subscriber telephone set on the called side are connected to each other at each time switch by a connection indicated by a dotted arrow shown in FIG. In the prior art, before making the actual call connection, a loopback connection realized by the connection of the wide blank arrow shown in FIG. 17 or FIG. 18 is performed at each time switch. For example, FIG.
In the example shown in FIG. 7, the continuity test function unit 48a on the calling side transmits a digital test pattern to a channel used for a call. This test pattern is turned back by the time switch 46a, and returns to the continuity test function unit 48a. Continuity test function unit 48
In a, the transmission pattern is compared with the received pattern to confirm the continuity of the transmission lines 50a and 50b. Transmission line 50
a and 50b, the time switch 46a and the time switch 46 connected next to the time switch 46a
b, the continuity of the transmission lines 52a and 52b is confirmed.
This is performed by forming a folded connection in the time switch 46b, as in the continuity test for the transmission lines 50a and 50b. In this way, the continuity of the transmission path from the calling side to the called side is sequentially confirmed. If an abnormality is detected in the loop connection test at a certain time switch, it is specified that there is an abnormality in the loop transmission path including the time switch.

FIG. 18 is basically the same as FIG. 17 except that the order of the continuity test by the folded connection is different from that of FIG. By using this technique, a two-wire connection from a certain element to the FPGA is formed in the FPGA in a folded connection.
It is possible to detect a wiring abnormality related to the line.

[0016]

As described above, Japanese Patent Laid-Open No.
The conventional technique disclosed in Japanese Patent Application Laid-Open No.
Is effective for detecting the stuck-at fault occurring in the basic logic block configuring the FPGA, but when mounting components on a board or a multi-chip module (hereinafter abbreviated as MCM) on which an FPGA is mounted, and using the device. Open failure on the joints of parts and the substrate, which can occur due to vibration at the time of
There is a problem that it is not suitable for detecting a short-circuit failure. Further, in the circuit device including the FPGA, components other than the FPGA are used.
A circuit test method for detecting a stuck-at fault inside a PGA is FP
There is also a problem that it is not suitable for detecting a defect occurring in a component other than the GA.

Further, in the probing using the probe needle, there is a problem that the positioning of the probe needle is difficult. In particular, this problem is when the degree of integration of the element is high,
It becomes more significant as the number of signal terminals increases. On the other hand, in probing using a jig such as a probe card, it is necessary to produce a jig, which requires production time and cost, and there is a problem that a circuit test cannot be easily performed. The advantage of the probe card is exhibited when the test for the same terminal arrangement is repeated, but otherwise the disadvantages due to this problem are greater.

Next, the method of performing a function test on the entire substrate has a problem that the test target cannot be narrowed down to a specific element. Therefore, the test target is all elements on the substrate, and the number of test patterns increases exponentially as the target becomes complicated. Therefore, there is a problem that it takes a long time to generate a test pattern and to execute a test using the test pattern.

Further, there is a problem that the method based on the boundary scan method cannot be applied when the device under test does not have a built-in boundary scan. In addition. Even in such a case, if an element around the element to be tested has a boundary scan, a test pattern can be input / output via the boundary scan. However, in that case, the area defined by the boundary scan includes a part other than the test target element, and the target is accordingly complicated. Therefore, the same kind of problem occurs, though not as much as when the whole substrate is targeted.

In a test method using a “continuity test method” disclosed in Japanese Patent Application Laid-Open No. 60-167554, an FPGA
However, there is a problem that it is impossible to specify which of the two signal lines connected due to the return inside has an abnormality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a circuit which can easily specify the location of a fault that can occur in a circuit device including a programmable logic element such as an FPGA. It is intended to provide a test method.

[0022]

According to a first aspect of the present invention, there is provided a circuit test method for testing a circuit device including a programmable logic element capable of rewriting an internal operation logic by an external access. A test method,
When performing a test on a test target element included in the circuit device, the arithmetic logic of the programmable logic element interposed between the test target element and the input / output terminal of the circuit device is rewritten, and the programmable logic element is rewritten. Inside, a through path for transmitting a signal between the device under test and the input / output terminal is formed.

The circuit test method according to the second aspect of the present invention comprises:
The circuit test method according to the present invention is applied to a test apparatus for a circuit device that can perform a circuit test by probing by bringing a probe needle into contact with a substrate wiring of the circuit device and that includes a probe control unit that controls the probing. For the signal terminals of the device under test, those that cannot directly transmit the signal between the input / output terminal of the circuit device and the input / output terminal of the circuit device, the probe control unit includes the through-path formation information and the circuit The probe needle is brought into contact with the substrate wiring connected to the signal terminal based on the substrate wiring information of the device, and the signal is transmitted between the input / output terminal and the probe needle of the circuit device and the device under test. Then, the circuit test of the test target element is performed.

According to a third circuit test method of the present invention, the first
In the circuit test method according to the invention, at least a part of the signal terminals of the device under test includes a signal path among the programmable logic elements interposed between the signal terminal and the input / output terminal of the circuit device. Selecting the nearest programmable logic element closest to the signal terminal, rewriting the operation logic of the near programmable logic element, and inputting the input data from the input / output terminal to the signal terminal or the A scan register for temporarily holding output data from a signal terminal to the input / output terminal is configured.

The circuit test method according to the fourth aspect of the present invention includes the third method.
In the circuit test method according to the invention, when testing a test target element included in the circuit device, the programmable logic element includes a plurality of signal terminals at a subsequent stage of the scan register that temporarily holds the input data. A decoder capable of distributing its output is formed in correspondence with the above, and the scan register stores coded data obtained by combining a plurality of the input data into one from the input / output terminal, and the decoder , Reading the encoded data, restoring a plurality of the input data, and outputting the input data to the corresponding signal terminals.

The fifth circuit testing method according to the present invention is the third method for testing a circuit.
In the circuit test method according to the invention, when testing a test target element included in the circuit device, the programmable logic element includes a plurality of signal terminals at a stage preceding the scan register that temporarily holds the output data. A coder capable of receiving the output data corresponding to
The coder integrates the plurality of received output data into one encoded data, and the scan register temporarily holds the encoded data.

According to a sixth circuit test method of the present invention,
In the circuit test method according to the invention, when performing a test on a test target element included in the circuit device, the programmable logic element includes a signal terminal at a stage subsequent to the scan register that temporarily holds the input data. A selector for selecting one of the corresponding plurality of output lines is formed, and the selector outputs the input data read from the scan register to the selected output line.

The circuit test method according to the seventh aspect of the present invention includes the third
In the circuit test method according to the invention, when performing a test on a test target element included in the circuit device, the programmable logic element includes a signal terminal at a stage preceding the scan register that temporarily holds the output data. A selector for selecting one of a plurality of input lines respectively corresponding to the input lines is formed, and the selector outputs the output data obtained from the selected input line to the scan register.

According to an eighth aspect of the present invention, there is provided a circuit test method for testing a circuit device including a programmable logic element capable of rewriting an internal operation logic by an external access. Selecting two signal terminals of the programmable logic element, rewriting the operation logic of the programmable logic element to connect the two signal terminals, and based on the presence / absence of signal conduction between the two signal terminals, Detecting a failure of the board wiring related to the two signal terminals, generating a combination of two signal terminals including one of the two signal terminals and the signal terminal other than the two signal terminals, and Is rewritten to connect the two signal terminals, and based on the presence / absence of signal conduction between the two signal terminals, the board wiring related to any of the signal terminals is defective. Is that to determine whether it is.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a schematic circuit diagram showing an example of an original circuit of a circuit device including an FPGA according to a first embodiment. This circuit device 200
Four rewritable FPGAs 202a to 202 on the substrate
d and the device under test 204 are mounted. The device under test 204 may or may not be an FPGA. The board is provided with connectors 208a and 208b for collecting input / output terminals 206 for the circuit device. Generally, at least some of the signal terminals of the device under test 204 are connected to the input / output terminals 20 through other components.
6 is connected. The present invention implemented here is effective when the intervening component includes a programmable logic element such as an FPGA.

In the example shown in the figure, each signal terminal of the device under test 204 is connected to the input / output terminal 206 via any of the FPGAs 202a to 202d. FP
Arithmetic logic is programmed in the GAs 202a to 202d. That is, since the operation logic is interposed between the signal terminal of the device under test 204 and the input / output terminal 206, test data input from the input / output terminal 206 is generally directly transmitted to the signal terminal of the device under test 204. Does not reach the input / output terminal 206 directly. Therefore, it is difficult to test the test target element 204. That is,
The above-described problem occurs when the entire substrate is to be tested.

FIG. 2 is a schematic circuit diagram showing an example of a circuit device to which the circuit test method according to the first embodiment is applied. In this method, the operation logic of the FPGAs 202a to 202d existing around the test target device 204 is rewritten when the test target device 204 is tested, and each FPG is rewritten.
A through path for transmitting a signal between the signal terminal of the device under test 204 and the input / output terminal 206 is formed in each of the A 202 a to 202 d. Here, “transmit a signal” means that an input signal input from a certain signal terminal of the FPGA is output from another signal terminal as it is, so-called FPGA
Is bypassed. The rewriting of the FPGA is performed by an input signal from the input / output terminal 206.

By rewriting to bypass the FPGA, the controllability of the input signal terminal to the device under test 204,
And the observability of the output signal terminal is improved.
04 test becomes easy.

In the example shown in FIG. 2, each signal terminal of the device under test 204 is directly connected to the input / output terminal 206 in a one-to-one correspondence. In other words, the test pattern is
Since only four may be used, the number is limited to a necessary minimum. Usually, each device is individually tested before being mounted on one substrate. In the example illustrated in FIG. 2, a test relating to the test target element 204 can be performed using the test pattern used for the test using the test target element 204 alone. Here, the test target element 204
The test related to not only the failure of the test target element 204 itself after the board is assembled on the substrate but also the test target element 20
A connection failure between the substrate 4 and the substrate and a failure in wiring around the test target element 204 are also detected.

When components other than the programmable logic element exist between the signal terminal and the input / output terminal 206 of the device under test 204, the signal terminal and the input / output terminal 206 of the device under test 204 are directly connected. You cannot connect. However, by performing the rewriting for bypassing the programmable logic element as described above, the circuit configuration is simplified as compared with the original circuit. In this case, too, the controllability of the input terminal and the observability of the output terminal are obtained. Is improved, and a test can be performed with fewer test patterns than when the entire original circuit is to be tested.

When there are a plurality of devices to be tested, the above test is performed on each of them. When all tests have been completed, an input signal is
Processing for restoring the contents of 202a to 202d to the operation logic of the original circuit is performed. Thus, in the test, it is not necessary to add another new component, and the FPGA on the board is effectively used.

The circuit test method according to the present embodiment
The present invention can be realized by using an electronic computer that stores the entire circuit configuration information of the circuit device 200 and the circuit configuration information of each component. Such a computer is connected to the input / output terminal 206 via, for example, an interface, and generates an input signal for rewriting the FPGA based on the circuit configuration information, or performs a test in a circuit configuration in which the rewritten FPGA is bypassed. It is configured to generate a pattern and input the pattern to the circuit device 200 via an interface.

[Second Embodiment] The second embodiment of the present invention relates to a test apparatus (prober) provided with a probe needle moving device. FIG. 3 is a schematic diagram illustrating a schematic configuration of the test apparatus according to the second embodiment. A plurality of elements 222 are arranged on a substrate 220 to be tested. The substrate 220 is placed on the test table 224,
The input / output terminals are connected to, for example, a connector provided on the test stand 224.

On the other hand, these elements 22
2 are provided. Probe needle 23
Numeral 0 is attached to the probe moving device 232 and is moved by the probe moving device 232 so as to be aligned with the wiring on the substrate 220, then lowered and contacted with the wiring.

The control device 234 is connected to the probe moving device 23
2 and control of input / output of test patterns between the test table 224 and the probe needles 230 and the substrate 220.
The input device 236 and the display device 238 are connected to the control device 234. The input device 236 is used to input test pattern data, wiring pattern data of the substrate 220, and the like to the control device 234. The display device 238 includes:
Display test results. The control device 234 is, for example, a computer connected to the prober or built in the prober.

FIG. 4 is a schematic circuit diagram showing an example of a circuit device to which the circuit test method according to the present embodiment is applied. FPGAs 242a to 242d in the configuration shown in FIG.
As described in the first embodiment, the arithmetic logic of the original circuit is rewritten to a logic that passes through a signal between the input / output terminal 206 and the device under test 244.

This embodiment is different from the first embodiment in that the device under test 244 has signal terminals 246 a and 246 b which are not connected to the input / output terminal 206. That is, elements 250a and 250b are connected to these signal terminals 246a and 246b via the wirings 248a and 248b of the substrate 220, but these elements 250a and 250b are not connected to the input / output terminal 206. . Therefore, in the input / output of the test pattern via the input / output terminal 206, disconnection of the wirings 248a and 248b and poor contact between the wiring and the signal terminals 246a and 246b cannot be detected.

In the present embodiment, such a signal terminal 2
In order to also perform failure detection relating to 46a and 246b, two probe needles 230 are connected to wirings 248a and 248b, respectively.
To make contact with these wirings. The probe needle 230 can be used not only in such a case but also for a signal terminal of the device under test 244 capable of inputting / outputting a signal from the input / output terminal 206. For example, even if input / output from the input / output terminal 206 is possible in design, there is a failure or the like related to an element around the test target element 244, in the example shown in the figure, FPGAs 242a to 242d. When it is difficult to input / output data from / to, a test can be performed by using the probe needle 230 to avoid the failure location.

FIG. 5 is a flowchart showing the flow of the processing of the test method according to the present embodiment. First, the control device 234
The original circuits written in the FPGAs 242a to 242d are rewritten to test circuits (S300 to S304). The test circuit is basically configured to pass through signals as described in the first embodiment. The control device 234
Based on the wiring pattern information of the substrate 220 and the failure location information obtained by the already performed test, the probe needle 2
The position where 30 is to be contacted is determined. Then, the position of the probe needle 230 is changed by controlling the probe moving device 232 to the determined position (S306).

Further, the control device 234 generates a test pattern for the test circuit thus configured (S
308). Here, since the test circuit is determined by determining the arrangement of the probe needles 230 in consideration of the already detected fault location, the test pattern is also generally changed according to the obtained test result.

Here, the test pattern is composed of a pattern of an input to the test circuit and a pattern of an output simulated thereto. The control device 234 inputs the input pattern to the test circuit and outputs the corresponding pattern to the test circuit.
The output pattern is compared with the output pattern included in the test pattern (S310).

If the result of the comparison is a mismatch, it indicates that there is a possibility that a fault exists, and the fault location is specified (S312). If the failure location cannot be specified, the control device 234 generates a test pattern that can further narrow down the location, changes the arrangement of the probe needles 230, and returns to the processing S308 or S306. Attempt to identify the fault location.

The test is performed on various places.
If the test for the scheduled portion remains (S314), the test circuit is changed (S316) and the process S
Return to 304 and continue the test. When the tests for all the test points have been completed, the circuit test processing ends (S318).

Third Embodiment FIG. 6 is a schematic circuit diagram showing an example of a circuit device to which a circuit test method according to a third embodiment is applied. FPGA with the configuration shown in the figure
Basically, as described in the first embodiment, 332a to 332d have the operation logic of the original circuit rewritten to a logic such that a signal between the input / output terminal 206 and the device under test 244 passes through. Things. However, the first embodiment is different from the first embodiment in that not all the signal terminals of the device under test 334 have a circuit for passing a signal through between the input / output terminal 206 and the FPGA 332a to 332d. It is different from the form. That is, for a part of the signal terminals of the device under test 334, the FPGA
A scan register (boundary scan register) is configured in each of 332a to 332d. In the example shown in the figure, scan registers 338a and 338b are connected to the signal terminals 336a and 336b of the device under test 334, respectively.
32b and 332d.

For example, when the number of signal terminals connected to the connector 208 among the signal terminals of the FPGAs 332 a to 332 d is smaller than the number of signal terminals of the device under test 334, the input / output terminal 206 prepared for the connector 208 is used.
It is not possible to independently control all the signal terminals of the device under test 334 by using only the above.

In such a case, in the prober having the probe needle 230 as in the second embodiment, the input / output terminal 2
The circuit test can be performed by supplementing the shortage of 06 with the probe needle 230. However, this is impossible with a test apparatus that does not have a mechanism for setting the probe needle 230 on the substrate 220. In a device that does not have the probe moving device 232 and the control device 234 for automatically controlling the position of the probe needle 230, the probe needle 23
Zero must be adjusted manually, which poses practical difficulties in testing with multiple test patterns.

The circuit test method of the present embodiment is a method applicable to a test apparatus in which a test using these probe needles 230 cannot be performed. That is, FPGA
A number of scan registers corresponding to the shortage of the input / output terminals 206 are formed in 332a to 332d, and they are connected in a chain. The chain can be one,
There may be more than one. One I / O terminal 206 is usually assigned to each end of the chain for input and output between the scan register and a control device outside the board 220. From the input / output terminal 206 at the end of the chain, data is set one by one in a scan register on the chain. The set data is simultaneously output to the device under test 334 by a control signal from an input / output terminal at the end of the chain. The data set in the scan register from the test element 334 is transmitted to the input / output terminal 20 at the end of the chain.
6 can be read one by one. As described above, setting and reading of data in each scan register can be controlled with fewer input / output terminals than the number of scan registers, and the problem of the shortage of the input / output terminals 206 is solved by using the probe needle 230 and its moving device. It can be avoided without.

[Embodiment 4] This embodiment is a circuit test method applied in the same case as the above-described Embodiment 3. In other words, this method is one of the methods for using a scan register to compensate for the shortage of the input / output terminals 206. 7 and 8 are schematic diagrams for explaining the difference between the present embodiment and the third embodiment. FIG.
FIG. 9 is a schematic diagram showing a correspondence between an output from a test target element and a scan register in the third embodiment. In the figure, separate scan registers 352a to 352 are provided for outputs 350a to 350d from the device under test, respectively.
The configuration described in Embodiment 3 is provided with d.

On the other hand, FIG. 8 is a schematic diagram showing the correspondence between the output from the device under test and the scan register in the present embodiment. In the present embodiment, the outputs 350a to 350d from the device under test are
Input to 54. The coder 354 outputs the input 3
50a to 350d are integrated into one encoded data and output. For this coder 354, scan register 3
56 is provided, and stores encoded data 358 output from the coder 354. This encoded data is read from the substrate.

The coder 354 and the scan register 3
56 is configured by rewriting the operation logic in the FPGA around the test target element. By performing such rewriting, the number of scan registers can be reduced.

While the above is an example on the output side of the device under test, similar things can be done on the input side of the device under test. In this case, a scan register that stores encoded data obtained by integrating a plurality of input data and a decoder corresponding to the scan register are configured in a peripheral FPGA through which an input to the device under test passes. Then, encoded data is input from the input / output terminal of the board,
This is stored in the scan register. Then, the trigger control signal for starting the test is received and read out by the decoder. The decoder decodes the data into input data to a plurality of signal terminals of the device under test, and inputs the data to the device under test.

Thus, the number of scan registers for holding input data can be reduced.

As described above, by reducing the number of scan registers by using a decoder and a coder, it is possible to reduce the overhead of storing data in the scan register and conversely, of reading data.

[Fifth Embodiment] The present embodiment is a circuit test method applied to the same case as the third embodiment. In other words, this method is one of the methods for using a scan register to compensate for the shortage of the input / output terminals 206. FIG. 9 is a schematic diagram showing the correspondence between the output from the device under test and the scan register in the present embodiment. A corresponding diagram in the third embodiment is FIG. 7 used in the fourth embodiment. Here, the description will be made with reference to FIG.

In the present embodiment, the outputs 350a to 350d from the device under test are
Is input to The selector 370 controls the control signal 372a,
372b selects and outputs one of the input signals. The scan register 3 is provided to the selector 370.
74 is prepared, and stores data 376 output from the selector 370. Scan register 374
The data 376 is read from the substrate by performing a read operation on.

The selector 370 and the scan register 374 are constructed by rewriting the operation logic in the FPGA around the device under test. By performing such rewriting, the number of scan registers can be reduced. In order to read each of the four data input to the selector 370, the test may be performed four times using the test pattern of the same input data. As a result, the time required for the test, that is, the number of clocks is quadrupled, but the operation of reading from the scan register is simplified, and the overhead is reduced.

While the above is an example on the output side of the device under test, similar things can be done on the input side of the device under test as well. In this case, a scan register that stores one input data and a selector corresponding to the scan register are configured in the peripheral FPGA through which the input to the test target element passes. The selector switches the signal terminal of the device under test, which is the output destination of the data read from the scan register, according to the control signal for switching.

Thus, the number of scan registers for holding input data can be reduced.

As described above, by reducing the number of scan registers by using the selector, it is possible to reduce the overhead of the operation of storing data in the scan register and, conversely, the operation of reading data.

[Sixth Embodiment] FIGS. 10 and 11 are schematic diagrams showing connection examples of an FPGA for explaining a circuit test method according to a sixth embodiment of the present invention.

In the figure, the left side is the side near the input / output terminals of the substrate. In the example shown in FIG.
The GA 400 and the FPGA 402 located at the subsequent stage are connected. First, of the signal terminals of the FPGA 400, two signal terminals 404a connected to the input / output terminals of the board,
The FPGA4 is connected so that a loopback connection is made between the 404b.
The operation logic of 00 is rewritten (FIG. 10A). In this state, the signal terminals 404a to 404a to
A test pattern is given to 404c and the like. Thus, the presence or absence of a failure related to the signal terminals of the FPGA, particularly the signal terminals 404a and 404b, is detected.

The failure includes, for example, a failure inside the FPGA, but rather seems to be an open failure or a short failure that can occur when the FPGA 400 is mounted on a board. If there is no failure in the connection shown in FIG. 10A, conduction is established between the signal terminals 404a and 404b, and between the other signal terminals 404a and 404c and between the signal terminals 404a and 404c.
04b-404c should be non-conductive. Therefore, when the signal terminals 404a and 404b are out of communication, it is estimated that there is an open failure such as a poor contact between the board and the terminal in either of the signal terminals 404a or 404b. However, it cannot be specified only by this connection pattern until which terminal is related. Also,
When the signal terminals 404a to 404c are in a conductive state, there is a possibility that there is a short-circuit failure between these terminals or between wirings related thereto. However, signal terminal 4
In this case, since the signal terminals 04a and 404b are connected in the FPGA, the signal terminals 404b and 404c should normally be in a conductive state contrary to expectation. Therefore, the signal terminals 404a-4
It is not possible to specify which of the terminals 04c and the signal terminals 404b-404c has the cause of the short-circuit failure.

A feature of the circuit test method according to the present embodiment is that the cause of the above-described failure is specified by further changing the connection pattern in the FPGA. FIG.
(B), (c) is a figure explaining the circuit test procedure which specifies a fault location.

FIG. 10 (b) shows signal terminals 404a, 40
FPGA 400 so that a folded connection is made between 4c.
Shows a state in which the operation logic is rewritten. FIG.
(C) shows a state in which the operation logic of the FPGA 400 has been rewritten so that the signal terminals 404b and 404c are folded back. In this state, a test pattern is applied to the signal terminals 404a to 404c and the like.

For example, when an open failure is detected between the signal terminals 404a and 404b in the test shown in FIG. 10A, the signal terminals 404a to 404c in FIG.
During this time, it is expected that an open failure is detected in any of the areas between the signal terminals 404b and 404c in FIG. If it is detected between signal terminals 404a-404c, the open fault is identified as relating to signal terminal 404a. On the other hand, the signal terminal 40
4b-404c, the signal terminal 404
b.

Also, in the case where the signal terminals 404a and 404c are brought into conduction in the test shown in FIG. 10A, various signal patterns between the signal terminals 404a and 404c in different connection patterns shown in FIGS. The location of the short-circuit failure is identified from the information of the conduction / non-conduction in the above.

In this manner, an open fault or a short fault between the input / output terminal and the FPGA 400 directly connected thereto is specified. Then, this circuit test method
A circuit test for identifying an open fault or a short fault between the FPGA 400 and the FPGA 402 located at a subsequent stage is performed. FIGS. 11A to 11C are schematic diagrams for explaining the method. Here, an example in which no failure has occurred in a circuit test using the FPGA 400 is shown. In that case, F
Signal terminal on the input / output terminal side of PGA 400 and FPGA 40
A through path is formed between the signal terminals on the two sides. Thus, a test pattern can be directly supplied from the input / output terminal to the FPGA 402, and a circuit test similar to that performed on the FPGA 400 is performed using the test pattern.

In the same manner, in the same manner, the object can be sequentially advanced to the FPGA far from the input / output terminal on the wiring, and the circuit test can be performed on a wide portion on the substrate.

FIG. 12 is a flowchart showing the flow of the processing of the test method according to the present embodiment. First, the control device of the circuit test apparatus that performs the circuit test rewrites the original circuits written in the FPGAs 400 and 402 shown in FIGS. 10 and 11, for example, and configures a test circuit including a folded connection (S
500 to S504).

Further, the control device generates a test pattern to be input to the test circuit thus configured (S506). In addition, an output pattern for the test pattern is generated, and the output pattern is compared with the actual output.
8, S510).

If the failure location is not specified (S
512) Further, the circuit is changed to another connection pattern or the test pattern is changed (S514), and the process S504 is performed.
Is repeated. If the failure location is specified and a test for another planned location remains (S516), the test circuit is changed (S518), and the process returns to step S504 to continue the test. When the tests for all the test points are completed, the circuit test processing ends (S520).

[0078]

According to the first aspect of the present invention, a through path is formed in a programmable logic element around a device under test,
Signals between the input / output terminals of the circuit device and the device under test are transmitted. As a result, the circuit configuration to be tested can be simplified, so that the types of test patterns can be reduced and the circuit test can be simplified. In addition, since the test does not require jigs such as probe needles or probe cards and their moving means, the test itself can be performed easily, and the configuration of the test equipment is simplified, enabling circuit testing at low cost. Is also obtained.

According to the second aspect of the present invention, among the signal terminals of the device under test that cannot directly transmit signals to and from the input / output terminals, the signal transmission to and from the device under test is performed using the probe needle. Done. This has the effect of reducing the number of probe needles used, facilitating adjustment of their mutual positions, and simplifying the configuration of the moving device. In addition, even when a probe card is produced, the number of probe needles attached to the probe card is small, so that it is possible to produce the probe card at a low price and to easily perform a circuit test.

According to the third aspect, the scan register for temporarily holding the input data to the test target device or the output data therefrom is configured in the programmable logic element around the test target device. A plurality of scan registers provided in one programmable logic element are connected in a chain, and setting or reading data to or from them requires only fewer signal terminals than the number of registers.
Thereby, for example, even when the number of input / output terminals to the circuit device is smaller than the signal terminals of the device under test, an independent signal is supplied to each signal terminal of the device under test, and The effect is obtained that an independent signal can be read from the signal terminal.

According to the fourth invention, for one scan register, a decoder is provided in a programmable logic element.
A coder is provided. The decoder decodes the coded data obtained by coding the plurality of input data stored in the scan register and outputs the coded data to the corresponding signal terminals of the device under test, and the coder encodes the plurality of output data from the device under test. And store it in the scan register. As a result, the number of scan registers can be reduced, and the effect of reducing the data input / output processing overhead for these scan registers configured in the programmable logic element can be obtained.

According to the fifth aspect, a selector is provided in a programmable logic element for one scan register. The data held in the scan register is
The signal is supplied to one of the signal terminals of the device under test connected to the plurality of output terminals by the selector. Alternatively, one of a plurality of output data from the test target element is selected by the selector, and the data is stored in the scan register. As a result, the number of scan registers can be reduced, and the effect of reducing the data input / output processing overhead for these scan registers configured in the programmable logic element can be obtained.

According to the sixth aspect, the operation logic of the programmable logic element is rewritten, and the two signal terminals are connected back. By changing the folded connection point, etc.
The effect of being able to specify the fault location up to which of the two signal terminals there is an open fault or a short fault is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic circuit configuration diagram illustrating an example of an original circuit of a circuit device including an FPGA according to a first embodiment.

FIG. 2 is a schematic circuit configuration diagram illustrating an example of a circuit device to which the circuit test method according to the first embodiment is applied.

FIG. 3 is a schematic diagram illustrating a schematic configuration of a test apparatus according to a second embodiment.

FIG. 4 is a schematic circuit configuration diagram illustrating an example of a circuit device to which a circuit test method according to a second embodiment is applied.

FIG. 5 is a flowchart showing a processing flow of a test method according to the second embodiment.

FIG. 6 is a schematic circuit configuration diagram illustrating an example of a circuit device to which a circuit test method according to a third embodiment is applied.

FIG. 7 is a schematic diagram illustrating a correspondence between an output from a device under test and a scan register according to a third embodiment.

FIG. 8 is a schematic diagram illustrating a correspondence between an output from a test target element and a scan register according to a fourth embodiment.

FIG. 9 is a schematic diagram illustrating a correspondence between an output from a test target element and a scan register according to a fifth embodiment.

FIG. 10 is a schematic diagram illustrating a connection example of an FPGA for explaining a circuit test method according to a sixth embodiment;

FIG. 11 is a schematic diagram illustrating a connection example of an FPGA for explaining a circuit test method according to a sixth embodiment;

FIG. 12 is a flowchart illustrating a processing flow of a test method according to a sixth embodiment.

FIG. 13 is a general block configuration diagram of basic logical blocks constituting the inside of an FPGA device.

FIG. 14 is a schematic circuit configuration diagram of an example of an FPGA configured to include nine basic logic blocks.

FIG. 15 is a schematic circuit configuration diagram of an example of an FPGA having a built-in scan register.

FIG. 16 is a flowchart showing a procedure of a circuit test method according to a first conventional technique.

FIG. 17 is a schematic configuration diagram of a transmission system illustrating a continuity test method according to a second conventional technique.

FIG. 18 is a schematic configuration diagram of a transmission system illustrating a continuity test method according to a second conventional technique.

[Explanation of symbols]

200 circuit devices, 202, 242, 332, 400,
402 FPGA, 204, 244, 334 Device under test, 206 input / output terminal, 208 connector, 220
Substrate, 222 elements, 230 probe needle, 232
Probe moving device, 234 control device, 352, 35
6,374 scan register, 354 coder, 370
selector.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Chiba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (56) References JP-A-8-102492 (JP, A) JP-A-9 -139667 (JP, A) JP-A-9-127201 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01R 31/28-31/3193

Claims (8)

(57) [Claims] 1. A circuit test method for testing a circuit device including a programmable logic element whose internal operation logic can be rewritten by an external access, comprising: When performing a test, the arithmetic logic of the programmable logic element interposed between the test target element and the input / output terminal of the circuit device is rewritten, and the test target element and the input / output are rewritten in the programmable logic element. A method for testing a circuit device, comprising forming a through path for transmitting a signal between a terminal and a terminal. 2. A test apparatus for testing the circuit device, the test device being capable of performing a circuit test by probing by bringing a probe needle into contact with a substrate wiring of the circuit device, and having a probe control unit for controlling the probing. Yes, among the signal terminals of the element under test, those that cannot directly transmit the signal between the input / output terminal of the circuit device and the probe control unit, the probe control unit, the formation information of the through path and the circuit device Based on the board wiring information,
The probe needle is brought into contact with the substrate wiring connected to the signal terminal, and the signal is transmitted between the input / output terminal and the probe needle of the circuit device and the device under test, thereby forming the circuit of the device under test. The test method for a circuit device according to claim 1, wherein the test is performed. 3. The programmable logic device interposed between the signal terminal and the input / output terminal of the circuit device, for at least a part of the signal terminal of the device under test, the signal terminal on the signal path. The closest programmable logic element is selected, and the operation logic of the near programmable logic element is rewritten so that the input data from the input / output terminal to the signal terminal or the previous signal from the signal terminal are written in the near programmable logic element. 2. The test method for a circuit device according to claim 1, wherein a scan register that temporarily holds output data to a writing output terminal is configured. 4. When a test target element included in the circuit device is tested, the programmable logic element has a plurality of signal terminals corresponding to a plurality of signal terminals at a subsequent stage of the scan register that temporarily holds the input data. A decoder capable of distributing its output is formed, and the scan register stores encoded data obtained by combining a plurality of the input data into one from the input / output terminal. 4. The method according to claim 3, further comprising reading data, restoring a plurality of the input data, and outputting the input data to the corresponding signal terminals. 5. When testing a test target element included in the circuit device, the programmable logic element includes a plurality of the signal terminals corresponding to a plurality of the signal terminals at a stage preceding the scan register that temporarily holds the output data. A coder capable of receiving output data is formed, the coder integrates the plurality of received output data into one piece of encoded data, and the scan register temporarily holds the encoded data. A method for testing a circuit device according to claim 3. 6. When testing a test target element included in the circuit device, the programmable logic element includes a plurality of signals corresponding to the signal terminals at a stage subsequent to the scan register that temporarily holds the input data. 4. The circuit device according to claim 3, wherein a selector for selecting one of the output lines is formed, and the selector outputs the input data read from the scan register to the selected output line. Test method. 7. When performing a test on a test target element included in the circuit device, the programmable logic element includes a plurality of signals corresponding to the signal terminals at a stage preceding the scan register that temporarily holds the output data. 4. The circuit device according to claim 3, wherein a selector for selecting one of the input lines is formed, and the selector outputs the output data obtained from the selected input line to the scan register. Test method. 8. A circuit test method for testing a circuit device including a programmable logic element whose internal operation logic can be rewritten by external access, wherein two signal terminals of the programmable logic element are connected to each other. Select, rewrite the operation logic of the programmable logic element, connect the two signal terminals, and determine whether the board wiring related to the two signal terminals is defective based on the presence or absence of signal conduction between the two signal terminals. And generating a combination of two signal terminals including one of the two signal terminals and the signal terminal other than the two signal terminals, rewriting the arithmetic logic of the programmable logic element, and
Connecting between the signal terminals, and identifying which of the signal terminals is defective in the substrate wiring based on the presence or absence of signal continuity between the two signal terminals. .