JPH0741265Y2 - Time axis correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a time base correction circuit called a time base collector. In particular, it relates to a time axis correction circuit that creates a write clock based on a horizontal synchronization signal.

(B) Conventional technology A reproduced video signal from a video tape recorder (VTR) has a jitter component. Therefore, the time axis correction circuit removes the jitter.

A time axis correction circuit is disclosed in, for example, Japanese Patent Laid-Open No. 61-10378 (H04N5).
/ 95) It is well known as shown in JP-A-62-150985 (H04N5 / 95) and the like.

FIG. 2 shows a feedback type time base correction circuit.

As is well known, (10) is a video signal input terminal, (12) is a horizontal sync signal separation circuit, (14) is a write clock creation circuit for creating a write clock signal synchronized with the horizontal sync signal, and (16) is A / The D converter, (18) is a buffer memory circuit, (20) is a D / A converter, and (22) is a read clock generation circuit that outputs a stable clock signal.
(23) is an output terminal.

This write clock generation circuit (14) has a built-in PLL loop circuit. In addition, the read clock generation circuit (2
In 2), a read clock may be created by a crystal oscillator, and the input horizontal sync signal may be a PL with a very long time constant.
A stable clock signal may be created by the L loop circuit.

In order to correct the time base correctly, it is necessary to perform sampling according to the time base distortion. Therefore, in the past,
The write clock is created based on the horizontal sync signal with time axis distortion and components. In order to prevent a delay in the write clock creating circuit (14) that creates this write clock,
The response time is increased by setting the time constant of the PLL loop small.

(C) Problems to be solved by the device However, no matter how high the responsiveness of the write clock generation circuit (14) is, the horizontal synchronization signal is used as a method for detecting the time distortion. The scanning period is delayed.

That is, the accurate write clock frequency can be determined by the intervals of the horizontal synchronizing signals positioned before and after the video period. Therefore, when the subsequent horizontal synchronizing signal is input to the write clock generation circuit (14), the corresponding video period has already ended and the video period of the next horizontal line has started.

An object of the present invention is to provide a time axis correction circuit that compensates for a delay of one horizontal period of a write clock signal that occurs when a write clock signal is created by a horizontal synchronization signal.

(D) Means for Solving the Problems The present invention is directed to a video signal input terminal (10) and a horizontal sync signal separating circuit (separating a horizontal sync signal from a video signal applied to the video signal input terminal (10) ( 12), a write clock creation circuit (14) for creating a write clock synchronized with the horizontal sync signal from the horizontal sync signal separation circuit (12), and a memory circuit (18) in which the video signal is written by the write clock. ) And a read clock creating circuit (22) for creating a stable read clock signal for reading from the memory circuit (18), the video signal input terminal (10) and the memory. A delay circuit (24) provided between the circuits (18) for delaying the video signal by one horizontal scanning period is provided.

(E) Action According to the present invention, the write clock corresponds to the video signal with one horizontal synchronization delay, so that the video signal is delayed by the same one horizontal synchronization period in the delay circuit (24), and the two correspond substantially completely. I did it.

(F) Embodiment FIG. 1 shows an embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals.

In the figure, (24) is a 1H delay circuit.

The video signal input from the video signal input terminal (10) is input to the horizontal sync separation circuit (12) and the 1H delay circuit (24). And horizontal sync separation circuit (12)
The horizontal synchronizing signal including the jitter component separated by is input to the write clock creating circuit (14). The write clock generation circuit (14) outputs a write clock having a frequency that reflects the jitter component one horizontal scanning period before. This write clock is input to the A / D converter (16) and the memory circuit (18). The A / D converter (16) and the memory circuit (18) A / D convert the delayed video signal from the 1H delay circuit (24) by a write clock and store it.

Then, the read clock generation circuit (22) outputs a stable read clock to read the video signal from the memory circuit (18) and convert it into an analog signal in the D / A converter (20).

The above operation will be described.

For example, when a video signal for one horizontal period expanded in the time axis due to jitter is input, the write clock generation circuit (14) receives the horizontal synchronization signal at the rear end of this one horizontal period to determine the expansion condition. It starts to generate a low-frequency write clock corresponding to the write clock. At this time, the video signal at the beginning of the one horizontal period delayed by the 1H delay circuit (24) is input to the A / D converter (16) and A / D converted. The A / D converted digital video signal is stored in the memory circuit (18) by the write clock.

On the contrary, when a video signal for one horizontal period contracted on the time axis due to jitter is input, the write clock signal has a high frequency according to the contraction degree.

As described above, in the present embodiment, by providing the 1H delay circuit (24), the jitter component (expansion / contraction amount) of the video signal can be detected in advance, and sampling can be performed in a form reflected in the write clock frequency. it can. As a result, in real time, a video signal having a jitter component is sampled in a form that absorbs the jitter. The same clock is used as it is for writing to the buffer memory circuit (18), and then the reading is performed with a stable read clock that is not affected by the jitter of the original video signal. It can be eliminated.

Although the 1H delay circuit (24) is formed by the glass delay line in the above embodiment, it may be formed by the charge transfer element which delays for a certain time, or the second A / D, D / The A converter may be formed by a memory provided on the input / output side. still,
In such a case, a clock that is stable at high frequency is used.

(G) Effect of the Invention As described above, according to the present invention, it is possible to correct the jitter in units of one horizontal scanning period.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. (24) …… Delay circuit.

Claims (1)

[Scope of utility model registration request] 1. A video signal input terminal (10) and a horizontal sync signal separation circuit (12) for separating a horizontal sync signal from the video signal applied to the video signal input terminal (10).
A write clock creating circuit (14) for creating a write clock synchronized with the horizontal sync signal from the horizontal sync signal separation circuit (12); and a memory circuit (18) for writing the video signal by the write clock. , Read clock creation circuit (2) that creates a stable read clock signal for reading this memory circuit (18)
And a delay circuit (24) provided between the video signal input terminal (10) and the memory circuit (18) for delaying the video signal by one horizontal scanning period. A time axis correction circuit characterized by.