JPS61148676A - Time base correcting system - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by fixing the phase-relation between the clock for drive a D-A converter and a digital input signal at a prescribed relation by using a phase-modulated reference clock as a memory-read clock and the clock for the D-A converter. CONSTITUTION:The read output from a memory 3 is directly the digital input signal to the D-A converter 5, and no timing circuit is provided. As a clock for a memory-read control circuit 12, a clock which is made by modulating the output of a clock phase modulator 15 i.e. the reference clock with phase modulation by a component of which period is less that of the reference clock for the time base deviation detecting signal, is used. The extent of delaying of a fixed delay line 16 that delays the output of the modulator 15 is so determined as to make the phase relation between the digital input signal to the D-A converter 5 and the clock supplied through the said delay line 16 most suitable i.e. the phase-relation between them is set in the center of the range P shown in the figure.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to 11 devices such as video tape recorders (VTR).
The present invention relates to a time axis correction device for correcting time axis fluctuations occurring in a video signal recording/reproducing system such as the above.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional time axis correction device disclosed in, for example, Japanese Unexamined Patent Publication No. 58-124385.
In the figure, 1 is an A-D converter that converts an analog input video signal into a digital signal, 2 is a delay device that delays this digitized video signal for a predetermined time, 3 is a memory that stores the digitized video signal, and 5 is a D -A converter, 4 is D-A
The digitized video signal which is the input of the converter 5 and the D-A
A timing circuit is used to synchronize the timing with the drive clock of the converter 5, and 6 is a low-pass filter (LPF) that removes unnecessary frequency components of the analog video signal that is the output of the DA converter 5. .

Further, 17 is a reference clock generator that generates a reference clock, 7 is a sync separator that separates and extracts a reproduced horizontal synchronization signal (hereinafter referred to as tape H) from the digitized video signal, and 8 is for detecting time axis fluctuations. a burst flag generator that generates a burst flag as a reference; 9 a time-base fluctuation detector that detects time-base fluctuations of the input video signal using this burst flag as a reference; 10 a time delay in the time-base fluctuation detector 9; Tape H delayer to compensate for, 11
a write control circuit 1 that generates a write clock based on the reference clock and controls writing to the memory 3;
2 is a read control circuit that similarly generates a read clock based on the reference clock and controls reading from the memory 3; 13 is a read H for resetting the read address;
This is a read H generator that generates a signal from the reference clock.

14 is a delay device for compensating for the time delay between writing and reading in the memory 3; 15 is a component that is less than or equal to the reference clock period of the detection signal output from the time axis variation detector 9; the reference clock is phase-modulated; This is a clock phase modulator.

Next, the operation will be explained.

First, a reproduced video signal from a VTR or the like is input to an A-D converter 1. This A/D converter 1 is driven by a reference clock generated by a reference clock generator 17, and converts the input reproduction signal into a digitized video signal. This video signal is sent to a video delay device 29, a time axis variation detector 9. The signal is supplied to the synchronous separator 7 in parallel.

Then, in the synchronization separator 7, the reproduced horizontal synchronization signal (tape H) is separated and extracted from the digitized video signal.
This tape H is supplied to a burst flag generator 8.

The burst flag generator 8 generates a burst flag based on this tape H as a reference for detecting time axis variation, and this burst flag is supplied to the time axis variation detector 9.

In this time axis variation detector 9, a burst signal in the video signal is extracted based on the burst flag, and a phase difference between the reference clock and this burst signal is detected. At the same time, the phase difference is converted into a time axis variation of the input video signal and is sent to the write control circuit 11 and the time axis variation detection signal delay unit 14 as a time axis variation detection signal.
supplied to

Further, the tape H is supplied to the write control circuit 11 after the time delay in the time axis variation detector 9 is compensated for in the tape H delay device 10. The write control circuit 11 is driven by the above-mentioned reference clock, and at the same time generates a write clock and sends it to the memory 3, the write control circuit 11 controls the delayed tape H by the component of the reference clock period unit of the above-mentioned time axis fluctuation detection signal. The write address is reset with a further delay depending on the write address.

On the other hand, the digitized signal input from the A-D converter 1 to the video delay device 2 is compensated for the time delay during time axis fluctuation detection by the delay device 2, and is written to the memory 3 by the write control circuit 11. be included.

Therefore, the time axis fluctuation component of one reference clock period unit included in the input video signal is corrected in the process of writing the digitized video signal into the memory 3.

The digitized video signal once written in the memory 3 in this way is read out by the gs driven by the reference clock.
It is read by the read clock from circuit 12. Further, in this read control circuit 12, the read address is reset by a read H signal generated by dividing the reference clock at a predetermined ratio by a read H generator 13.

The minute time axis fluctuation component that is less than the reference clock period and included in the digitized video signal read out from the memory 3 is corrected in the process of converting the digitized video signal into an analog signal. That is, first, the video signal read out from the memory 3 is once input to the timing circuit 4. Further, the above-mentioned time axis fluctuation detection signal is written in the memory 3 by the delay device 14.

The time delay during readout is compensated and input to the timing circuit 4 and clock phase modulator 15. The video signal input to the timing circuit 4 is now D-
The timing is matched with the driving clock of the A converter 5, and the signal is output to the DA converter 5. At this time, as the clock for driving the DA converter 5, a reference clock obtained by phase-modulating the reference clock with a component equal to or less than the reference clock cycle of the time axis variation detection signal is used. In this way, minute time axis fluctuation components that are less than or equal to the reference clock period and included in the digitized video signal are corrected in the process of this DA conversion.

The video signal converted into an analog signal in this way is
Unnecessary frequency components are removed through a low-pass filter 6 and output as a corrected output video signal.

Note that all the digital signal processing systems shown in this figure are driven by the reference clock of the reference clock generator 17 shown by the broken line.

[Problem that the invention seeks to solve]

However, in the conventional time axis correction device as described above, D-
The digital input signal of the A conversion circuit 5 is a digitized video signal read from the memory 3 using the reference clock, and the driving clock is a phase modulated version of the reference clock. This has the disadvantage that the timing of the input signal and the driving clock must be matched, making the circuit complex.

In other words, if the timing between the driving clock and the digital input signal does not fall within a certain range, the D/A converter will lose the S/A of the analog output signal after D/A conversion.
This results in a very bad N.

This will be explained using Fig. 2. In Fig. 0, (a
) is the digital input signal of the D-A converter, (b) and (
C) is the driving clock for the D-A converter, and assuming that the setup of the digital input signal (a) must be completed by the falling edge of this driving clock, (b)
) indicates the limit to which the driving clock can be phase modulated to the leading side with respect to the digital input signal (a), and (0) indicates the limit to which the driving clock can be phase modulated to the delayed side with respect to the digital input signal (a). Therefore, as mentioned above, when applying phase modulation to the driving clock of the D-A converter 5, the phase relationship between the driving clock after phase modulation and the digital input signal should be within the range P in FIG. Therefore, it was necessary to provide a timing circuit composed of variable delay lines and the like.

This invention was made to solve the above-mentioned problems, and it is possible to simplify the circuit by omitting the above-mentioned timing circuit, and furthermore, the phase of the digital input signal of the above-mentioned D-A converter and the driving clock can be adjusted. The purpose of this invention is to obtain a time axis correction device that can optimally maintain the

[Means for solving problems]

A time axis correction device according to the present invention includes: a clock phase modulator that modulates the phase of a reference clock with a time axis variation component that is less than or equal to the reference clock period; and a memory read control circuit that performs memory read control using the phase modulated clock. A delay means is provided for giving a certain delay to the phase modulated clock so that the phase relationship between the phase modulated clock and the digital input signal of the DA converter is optimized, and the delayed clock causes the It is designed to drive a DA converter.

[Effect]

In this invention, the memory read control clock is phase-modulated with a component of time axis fluctuation less than or equal to the reference clock period,
While using the output from the memory successively using the clock as a digital input signal of the DA converter, the phase relationship between the clock and the digital input signal of the DA converter is optimized for the phase modulated clock. This delay is applied as a clock for driving the DA converter.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a time axis correction device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. It is a digital input signal for the A converter 5,
No timing circuit is provided. Further, as the clock for the memory read control circuit 12, a clock obtained by phase modulating the output of the clock phase modulator 15, that is, the reference clock with a component shorter than the reference clock period of the time axis variation detection signal is used. Furthermore, 16 is a fixed delay line that delays the output of the clock phase modulator 15 for a predetermined time,
This amount of delay is determined so that the phase relationship between the digital input signal of the DA converter 5 and the clock supplied via the delay line 16 is optimal, that is, the phase relationship between the two is within the range shown in FIG. It is set to be at the center of P.

Next, the operation will be explained. In the time axis correction device of this embodiment, operations such as A-D conversion, time axis fluctuation detection, write control including correction of time axis fluctuation components in units of reference clock cycles, and read H The operations of the generator 13 and the delay device 14 are exactly the same as those of the conventional device described above, so a description thereof will be omitted, and below, a correction operation for a minute component less than the reference clock period in the time axis variation detection signal will be described.

The minute components of the time axis fluctuation detection signal that is the output of the time axis fluctuation detection device 9, which are equal to or less than the reference clock period, are detected by the delay device 1.
After the time delay required for writing and reading the digitized video signal in the memory 3 is compensated for in step 4, the signal is input to the clock phase modulator 15, and becomes a signal for phase modulating the reference clock in the phase modulator 15. The clock phase modulated by the clock phase modulator 15 is sent to the memory read control circuit 12 and becomes the read clock for the memory 3. That is, the readout output from the memory 3 becomes a digital input signal to the DA converter 5 at the timing of the phase-modulated clock.

Further, the phase modulated clock is transmitted through a fixed delay line 16.
It is also sent as a driving clock for the DA converter 5 via the DA converter 5. Therefore, in the DA converter 5, both the digital input signal and the drive clock are input at the timing of the phase modulated clock. Here, the amount of delay in the fixed delay line 16 is determined when the phase relationship between the digital input signal of the DA converter 5 and the driving clock is at the center of the appropriate phase relationship P shown in FIG. Since it is set at the optimum position, even if the degree of clock phase modulation changes, the optimum position of the above phase relationship can always be maintained.

Furthermore, it is conventional that a corrected output signal is obtained through the low-pass filter 6 after D-A conversion, and that the digital signal processing system in FIG. 1 is driven by one reference clock system shown by a broken line. It is similar to the device.

In the device of this embodiment, memory readout is controlled using a phase-modulated clock, and the phase relationship between the phase-modulated clock and the digital input signal of the D-A converter 5 is optimized. Since the D-A converter 5 is driven by giving a certain delay so that the above-mentioned delay occurs, there is no need to provide a timing circuit consisting of a variable delay line etc. as in the conventional device, and the circuit configuration is simplified. be able to.

Note that although the above embodiment describes the case of correcting the time axis fluctuation for each horizontal scanning line, the present invention can also be applied to the case of correcting the time axis fluctuation within one horizontal scanning line, that is, the speed error, and the above-mentioned Effects similar to those of the embodiment can be obtained.

In addition, in the above embodiment, the case where all processing of digital signals is driven by only one reference clock system has been explained, but for example, when writing to memory, the video signal is compressed by one time axis, and when reading from memory, Even when the clocks for A-D conversion and memory writing of the video signal and the clocks for memory read-out and D-A conversion are configured in separate systems and made independent, as in the case of axis expansion, the above embodiment does not apply. A similar effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, a phase-modulated reference clock is used as the memory successive clock and the DA converter driving clock, and the DA converter driving clock and the digital input signal are synchronized. Since the phase relationship is fixed to a predetermined relationship, the phase relationship between the digital input signal and the driving clock of the D-A converter can be maintained optimally without providing a timing circuit in conventional devices.
This has the effect of simplifying the circuit configuration of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time axis correction device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the phase relationship that should be maintained between the driving clock of the D-A converter and the digital input signal, and FIG.
The figure is a block diagram of a conventional time axis correction device. 1...A-D converter, 3...memory, 4...D-
A converter, 11...Memory write control circuit, 12...
・Memory read control circuit, 15...clock phase change l
lI device, 16...fixed delay line, 17...reference clock generator. Note that the same reference numerals in the figures indicate the same or equivalent parts. Zennobe System Diagram 2

Claims (4)

[Claims] (1) Time axis fluctuations that occur in the video signal recording and reproducing system,
After converting the video signal from analog to digital, the time axis correction device corrects the component in units of periods of the reference clock and the components less than or equal to the period of the clock. a clock phase modulator that modulates the phase of the clock according to the value of a time axis fluctuation component that is less than or equal to the period of the clock; a memory read control circuit for controlling reading of the memory, a delay means for delaying the output of the clock phase modulator for a predetermined time, and a D-A conversion of the video signal read from the memory using the output of the delay means as a driving clock. A time axis correction device comprising: a D-A converter. (2) The delay means is a fixed delay line that delays the phase-modulated clock so that the phase relationship between the digital input signal of the D-A converter and the driving clock is optimal. A time axis correction device according to claim 1. (3) The clock used for A-D conversion and memory writing of the video signal and the clock used for memory reading and D-A conversion are clocks of the same system. 2. The time axis correction device according to item 1 or 2. (4) The scope of the claim characterized in that the clock used for AD conversion and memory writing of the video signal and the clock used for memory reading and D-A conversion are of independent systems. The time axis correction device according to item 1 or 2.