JPH0740183B2 - Display address generator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display address generating device for generating a display address for a bitmap display.

2. Description of the Related Art As a conventional display address generator, for example, Japanese Patent Laid-Open No.
No. 61-232485.

FIG. 3 is a block diagram of the conventional display address generator, in which 1 is a register for holding a display address (DADR), 2 is a register for holding a start address of a display line (TAR), 3 is a register. 4 is for each non-interlace,
Register that holds the image width during interlacing (PCH, 2PC
H), 5 is a register (NR) for holding the number of data read simultaneously, 6 is a register (DSTR) for holding the display start address of the display screen, 7 is an adder, 8 is an address output register (VAR), 9 Is a register (ATR) that holds the display request generation interval, and 10 is a control circuit that controls the reading and writing timing of the register.

The operation of the conventional display address generating device configured as described above will be described with reference to FIG. Reference numeral 20 in FIG. 4 shows a map of the image memory. Reference numeral 211 denotes an area to be displayed in the image memory 20. In this case, the display start address "0" is stored in DSTR6, the image width "64" is stored in PCH3, the image width "128" is stored in 2PCH4, and "4" is stored in NR5. At the start of display, the value of DSTR6 passes through the adder 7 and DADR1, TA
It is stored in R2 and VAR8, and the value of VAR8 is used as the display address. Thereafter, during the same row, the contents of DADR1 and VAR8 are updated to the value added by NR5 every machine cycle indicated by ATR9.

At the beginning of the next line, addition is performed between TAR2 and PCH3 (when non-interlaced) or 2PCH4 (when interlaced), and the result is stored in DADR1, TAR2, and VAR8. FIG. 4 shows address generation in the case of non-interlace.

However, in the above configuration, since the display request generation interval and the address update are fixed by ATR9 and NR5, the flexible setting of the display start address as shown in FIG. 5 is possible. It was not possible, and had the problem that it was not suitable for dual port memory for images.

In view of such a point, an object of the present invention is to provide a display address generation device which can flexibly set a display start address and can easily scroll a display screen in an image dual port memory.

Means for Solving the Problems According to the present invention, a first register for holding an address and a write and read bus common to the first register are connected to hold a start address of a row being displayed. A first register file composed of two registers, a third register for holding the image width of the display screen, and a read bus common to the third register are connected, and an address is assigned every machine cycle. A fifth register which is connected to a second register file composed of a fourth register holding a value to be updated and a read bus of the first register file and holds a display start address of a display screen.
Register and the data on the read buses of the first and second register files as an input to perform addition,
An adder for outputting the result to the write bus of the register file, a sixth register for receiving the output of the adder and holding the same contents as the first register, and a specific bit of the address And a display address generating device including a seventh register.

With the above-described configuration, the present invention adds the value of the fourth register in each machine cycle to the first register and the sixth register holding the display address, and sets the bit designated by the seventh register. When a change occurs in bits at positions or more, a display request is generated and the value of the sixth register is used as a display address to generate a display address.

Embodiment 1 FIG. 1 is a block diagram of a display address generator according to an embodiment of the present invention. In FIG.
11 is a register that holds the display address (DADR), 12 is a register that holds the start address of the display line (TAR), 1
3 and 14 are registers (PCH and 2PCH) that hold the image width during non-interlace and interlace, respectively, and 15 is a register (WR) that holds the number of words that are added per machine cycle. Stores the number of words (NR) divided by the display request occurrence interval (ATR). 16 is a register DSTR that holds the display start address of the display screen, 17 is an adder, 18 is an address output register (VAR), 19 is a register that specifies a specific bit of the address (BIT), 110 is a control circuit register Control read and write timing.

The operation of the display address generating device of this embodiment having the above-described structure will be described below with reference to FIG. FIG. 2 shows address generation corresponding to the display example shown in FIG. In this case, the display start address is "2" in DSTR16, the image width is "64" in PCH13, and the image width is "128" in 2PCH14.
However, "1" is stored in WR15. At the start of display, the value of DSTR16 passes through the adder 17 and DADR11, TAR12, V
It is stored in AR18 and the value of VAR18 is used as the display address. Thereafter, during the same row, the contents of DADR11 and VAR18 are updated to the value added by WR5 ("1") every machine cycle. The adder 17 issues a display request when detecting an address update at a bit above the specific bit position designated by the BIT 19.

TAR12 and PCH13 (when non-interlaced) at the beginning of the next line
Alternatively, addition is performed during 2PCH14 (during interlace) and the result is stored in DADR11, TAR12, and VAR18. FIG. 2 shows address generation in the case of non-interlace.

As described above, according to this embodiment, the update interval (ATR) in the control circuit is updated by updating the address every machine cycle.
The control circuit is simplified without the need for controlling.

Although the case where the address change at a specific bit position or more is detected by the carry signal of the adder 17 is shown in the present embodiment, an address comparator may be used.

EFFECTS OF THE INVENTION As described above, according to the present invention, the display start address can be flexibly set, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a display address generating device according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the same embodiment, FIG. 3 is a block diagram of a conventional display address generating device, and FIG. FIG. 5 is a diagram for explaining the operation of the conventional display address generator, and FIG. 5 is a diagram showing an example of display addresses that cannot be generated by the conventional display address generator. 11 …… First register, 12 …… Display line start address register, 13 …… Non-interlaced image width register, 14
...... Image width register during interlacing, 15 …… Update word count register per machine cycle, 16 …… Display start address register, 17 …… Adder, 18 …… Address output register, 19 …… Specific bit designation register , 110 …… Control circuit.

Claims (1)

[Claims] 1. A first register which holds an address, and a second register which is connected to a write and read bus common to the first register and holds a start address of a row being displayed. Is connected to a first register file, a third register for holding the image width of the display screen, and a read bus common to the third register, and holds a value for updating the address every machine cycle. A second register file including a fourth register and a fifth register which is connected to the read bus of the first register file and holds a display start address of a display screen.
Register and the data on the read buses of the first and second register files as an input to perform addition,
An adder for outputting the result to the write bus of the register file, a sixth register for receiving the output of the adder and holding the same contents as the first register, and a specific bit of the address And a seventh register,
A display request is generated when the address updated by the adder changes at a bit of a bit position specified by the seventh register or more, and the value of the sixth register is used as the display address. Characteristic display address generator.