JPH0738444B2 - Method for manufacturing vertical field effect transistor - Google Patents
Method for manufacturing vertical field effect transistorInfo
- Publication number
- JPH0738444B2 JPH0738444B2 JP61082708A JP8270886A JPH0738444B2 JP H0738444 B2 JPH0738444 B2 JP H0738444B2 JP 61082708 A JP61082708 A JP 61082708A JP 8270886 A JP8270886 A JP 8270886A JP H0738444 B2 JPH0738444 B2 JP H0738444B2
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- conductivity type
- mask
- semiconductor substrate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は縦型電界効果トランジスタの製造方法に関し、
特に、しきい値電圧のコントロール性を向上させた縦型
電界効果トランジスタの製造方法に関する。The present invention relates to a method for manufacturing a vertical field effect transistor,
In particular, the present invention relates to a method of manufacturing a vertical field effect transistor having improved controllability of threshold voltage.
従来の縦型電界効果トランジスタの製造方法は、第２図
（ａ）に示すように一導電型半導体基板１の表面にゲー
ト酸化膜12および多結晶シリコン８を形成し、第２図
（ｂ）に示すようにフォトリソグラフィ技術を用いて多
結晶シリコン８とゲート酸化膜をエッチングし、ゲート
電極８′を形成する。その後ゲート電極８′をマスクに
して第２図（ｃ）に示すように基板と反対導電型の不純
物領域（ベース）５と基板と同じ導電型の不純物領域
（ソース）６とを形成し、その後、第２図（ｄ）に示す
ようにゲート電極８′上に層間絶縁膜９を設け、第２図
（ｅ）に示すように基板裏面側にドレイン電極11を形成
し、基板表面側にソース電極を形成する。As shown in FIG. 2 (a), a conventional method for manufacturing a vertical field effect transistor is to form a gate oxide film 12 and a polycrystalline silicon 8 on the surface of a one-conductivity type semiconductor substrate 1, and then, as shown in FIG. As shown in FIG. 7, the photolithography technique is used to etch the polycrystalline silicon 8 and the gate oxide film to form a gate electrode 8 '. After that, using the gate electrode 8'as a mask, an impurity region (base) 5 having the opposite conductivity type to the substrate and an impurity region (source) 6 having the same conductivity type as the substrate are formed as shown in FIG. , An interlayer insulating film 9 is provided on the gate electrode 8'as shown in FIG. 2 (d), a drain electrode 11 is formed on the back surface of the substrate as shown in FIG. 2 (e), and a source is formed on the front surface side of the substrate. Form electrodes.
上述した従来の縦型電界効果トランジスタの製造方法に
おいては、多結晶シリコンのゲート電極をマスクにベー
ス及びソースを形成しているので、ゲート電極直下に、
イオン注入などでしきい値をコントロールする不純物層
を形成することができなかった。このためしきい値がベ
ース、ソースの不純物注入量及び拡散条件だけで決定さ
れ、しきい値のコントロールが困難であるという欠点が
ある。In the above-described conventional method for manufacturing a vertical field effect transistor, since the base and the source are formed using the gate electrode of polycrystalline silicon as a mask, immediately below the gate electrode,
An impurity layer for controlling the threshold could not be formed by ion implantation or the like. For this reason, the threshold value is determined only by the base and source impurity implantation amounts and the diffusion conditions, which makes it difficult to control the threshold value.
本発明は、縦型電界効果トランジスタの製造方法におい
て、窒化膜をマスクにして、Ｐベース,N+ソースを形成
し、その後、この窒化膜を除去し、窒化膜のあった所の
全面もしくは一部のみにイオン注入をすることにより、
しきい値電圧のコントロール性を向上したものである。According to the present invention, in a method for manufacturing a vertical field effect transistor, a nitride film is used as a mask to form a P base and an N + source, and then this nitride film is removed to remove the entire surface of the nitride film or a part thereof. By implanting ions only in the part,
The controllability of the threshold voltage is improved.
本発明の縦型電界効果トランジスタの製造方法は、半導
体基板の表面側にソース及びゲート電極が形成され裏面
側にドレイン電極が形成された縦型電界効果トランジス
タの製造方法において、半導体基板の表面に酸化膜及び
窒化膜を順に成長させる工程と、フォト・リソグラフィ
技術を用いて窒化膜をエッチングし窒化膜をマスクにし
て半導体基板と逆の導電型の第１不純物領域を形成する
工程と、第１不純物領域内に半導体基板と同じ導電型の
第２の不純物領域を形成する工程と、窒化膜をマスクに
して酸化膜を形成した後窒化膜を除去する工程と、窒化
膜の除去された所の全面もしくは一部に半導体基板と逆
の導電型の第３不純物領域をイオン注入により形成する
工程とを有することを特徴とする。A method for manufacturing a vertical field effect transistor according to the present invention is a method for manufacturing a vertical field effect transistor in which a source and a gate electrode are formed on a front surface side of a semiconductor substrate and a drain electrode is formed on a rear surface side of the semiconductor substrate. A step of sequentially growing an oxide film and a nitride film; a step of etching the nitride film using a photolithography technique to form a first impurity region having a conductivity type opposite to that of the semiconductor substrate using the nitride film as a mask; A step of forming a second impurity region having the same conductivity type as the semiconductor substrate in the impurity region; a step of forming an oxide film using the nitride film as a mask and then removing the nitride film; and a step of removing the nitride film. And a third impurity region having a conductivity type opposite to that of the semiconductor substrate is formed on the entire surface or a part thereof by ion implantation.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例の工程毎の断面図である。FIG. 1 is a sectional view of each step of one embodiment of the present invention.
第１図（ａ）に示すように一導電型半導体基板１に、酸
化膜2,窒化膜３を成長させ、第１図（ｂ）に示すよう
に、レジスト４によりフォト・リソグラフィ技術を用い
て、パターニングを行う、その後第１図（ｃ）に示すよ
うに窒化膜３をマスクにして、半導体基板と反対の導電
型の不純物領域５および半導体基板と同じ導電型の不純
物領域６を形成する。その後第１図（ｄ）に示すよう
に、窒化膜３をマスクに酸化する窒化膜３の下は酸化膜
が成長しないので、第１図（ｄ）に示すような、形状
（バーズ・ビーク）になる。As shown in FIG. 1 (a), an oxide film 2 and a nitride film 3 are grown on one conductivity type semiconductor substrate 1, and as shown in FIG. 1 (b), a resist 4 is used to perform photolithography. Then, patterning is performed, and then, using the nitride film 3 as a mask, an impurity region 5 of a conductivity type opposite to the semiconductor substrate and an impurity region 6 of the same conductivity type as the semiconductor substrate are formed using the nitride film 3 as a mask. Thereafter, as shown in FIG. 1 (d), since the oxide film does not grow under the nitride film 3 which is oxidized by using the nitride film 3 as a mask, the shape (bird's beak) as shown in FIG. 1 (d) is formed. become.
次に第１図（ｅ），（ｆ）に示すように窒化膜３を除去
し、窒化膜のあった所の全部もしくは、一部に基板と逆
の不純物領域15を形成する。その後第１図（ｇ），
（ｈ）及び（ｉ）に示すような順序でゲート電極8,ソー
ス電極13,ドレイン電極11を形成し、縦型電界効果トラ
ンジスタを形成する。Next, as shown in FIGS. 1E and 1F, the nitride film 3 is removed, and an impurity region 15 opposite to the substrate is formed in all or a part of the place where the nitride film was. After that, FIG. 1 (g),
The gate electrode 8, the source electrode 13, and the drain electrode 11 are formed in the order shown in (h) and (i) to form a vertical field effect transistor.
不純物領域15によりしきい値電圧が決定できるので、コ
ントロール精度がよくなる。Since the threshold voltage can be determined by the impurity region 15, control accuracy is improved.
以上説明したように、本発明は、縦型電界効果トランジ
スタの製造方法において、窒化膜を用いて二重拡散を行
ない、さらに窒化膜をマスクに酸化し、ゲート直下にイ
オン注入できる形状にすることにより、しきい値電圧の
コントロール精度を向上することができる効果がある。As described above, according to the present invention, in the method of manufacturing a vertical field effect transistor, double diffusion is performed using a nitride film, and further, the nitride film is oxidized by a mask so that ions can be implanted directly under the gate. Thus, there is an effect that the control accuracy of the threshold voltage can be improved.
第１図（ａ）〜（ｉ）は本発明の一実施例の工程断面
図、第２図（ａ）〜（ｅ）は従来の縦型電界効果トラン
ジスタの工程断面図である。 １……半導体基板、２……酸化膜、３……窒化膜、４…
…レジスト、５……基板と反対の導電型の不純物領域
（ベース）、６……基板と同じ導電型の不純物領域（ソ
ース）、７……イオン注入、８……多結晶シリコン、
８′……ゲート電極（例えば、ポリミリ・ゲート）、９
……層間絶縁膜、10……基板と反体の導電型の不純物領
域、11……ドレイン電極、12……ゲート酸化膜。1 (a) to 1 (i) are process sectional views of an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are process sectional views of a conventional vertical field effect transistor. 1 ... Semiconductor substrate, 2 ... Oxide film, 3 ... Nitride film, 4 ...
... resist, 5 ... impurity region of opposite conductivity type to the substrate (base), 6 ... impurity region of the same conductivity type as the substrate (source), 7 ... ion implantation, 8 ... polycrystalline silicon,
8 '... gate electrode (for example, poly-millimeter gate), 9
...... Interlayer insulation film, 10 ...... Conductor type impurity region opposite to substrate, 11 ...... Drain electrode, 12 ...... Gate oxide film.
Claims (1)
逆導電型のベース領域と、該ベース領域内に形成された
一導電型のソース領域と、ソース領域と半導体基板との
間のベース領域の表面に絶縁膜を介して形成されたゲー
ト電極とを有する縦型電界効果トランジスタの製造方法
において、前記半導体基板の表面に第１の酸化膜及び窒
化膜を順に成長する工程と、前記窒化膜を選択的にエッ
チングして、所定の領域に窒化膜を残し、残った該窒化
膜をマスクとして前記半導体基板に不純物を導入し逆導
電型ベース領域を形成する工程と、該窒化膜をマスクと
して前記ベース領域内に不純物を導入し一導電型ソース
領域を形成する工程と、その後、該窒化膜をマスクとし
て前記半導体基板を酸化し第２の酸化膜を形成したの
ち、該窒化膜を除去し、前記第２の酸化膜をマスクとし
て該窒化膜が存在していた部分の前記ベース領域表面
に、閾値電圧を制御するための、逆導電型不純物をイオ
ン注入する工程とを有することを特徴とする縦型電界効
果トランジスタの製造方法。1. A reverse conductivity type base region formed on one main surface of a conductivity type semiconductor substrate, a conductivity type source region formed in the base region, and a source region and a semiconductor substrate. A method of manufacturing a vertical field effect transistor having a gate electrode formed on the surface of a base region via an insulating film, a step of sequentially growing a first oxide film and a nitride film on the surface of the semiconductor substrate, A step of selectively etching the nitride film to leave a nitride film in a predetermined region, introducing impurities into the semiconductor substrate using the remaining nitride film as a mask to form a reverse conductivity type base region, and the nitride film Forming a one-conductivity type source region by introducing impurities into the base region using the mask as a mask, and then oxidizing the semiconductor substrate to form a second oxide film using the nitride film as a mask, and then forming the nitride film. Remove And, using the second oxide film as a mask, ion-implanting an impurity of opposite conductivity type for controlling the threshold voltage on the surface of the base region where the nitride film was present. Method for manufacturing vertical field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61082708A JPH0738444B2 (en) | 1986-04-09 | 1986-04-09 | Method for manufacturing vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61082708A JPH0738444B2 (en) | 1986-04-09 | 1986-04-09 | Method for manufacturing vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62238669A JPS62238669A (en) | 1987-10-19 |
| JPH0738444B2 true JPH0738444B2 (en) | 1995-04-26 |
Family
ID=13781901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61082708A Expired - Lifetime JPH0738444B2 (en) | 1986-04-09 | 1986-04-09 | Method for manufacturing vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0738444B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146367A (en) * | 1987-12-02 | 1989-06-08 | Nec Corp | Field effect transistor |
| IT1252625B (en) * | 1991-12-05 | 1995-06-19 | Cons Ric Microelettronica | FIELD-EFFECT TRANSISTORS MANUFACTURING PROCESS WITH ISOLATED GATE (IGFET) AT LOW SHORT DENSITY CIRCUITS BETWEEN GATE AND SOURCE AND DEVICES OBTAINED WITH IT |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5550661A (en) * | 1978-10-07 | 1980-04-12 | Mitsubishi Electric Corp | Insulated gate type field effect semiconductor device |
| JPS6021571A (en) * | 1983-07-15 | 1985-02-02 | Tdk Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-04-09 JP JP61082708A patent/JPH0738444B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62238669A (en) | 1987-10-19 |
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