JPH0736407A - Driving circuit for matrix display device - Google Patents

Abstract

PURPOSE:To provide an excellent display by receiving a low speedclock from a control circuit, coverting it again in an internal driving circuit and generating a stable clock signal DCLK. CONSTITUTION:By the driving circuit 2, a video signal V and a frequency divided signal 1/8DCLK are received, and the former is subjected to synchronization separation by a synchronizing separator circuit 4, and by the latter, a pixel clock signal DCLK is reproduced through a PLL(phase locked loop) circuit 5. In such a case, the PLL circuit 5 is designed so that the output frequency becomes eight times as much as the frequency of an input signal. Thus, the PLL circuit is operated through a prescribed path, and the pixel clock signal DCLK' is generated. That is, since the signal DCLK' is synchronized with the period (8 pixels unit) of the frequency divided signal 1/8DCLK, it becomes the stable clock with less period fluctuation over a horizontal scanning interval. Then, by a signal processing circuit 6, the signal processing is performed based on the signal, and the video signal and the frequency divided signal are converted to the video signal Vm and a control signal Sm suitable for a matrix display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a matrix display device, and more particularly to a drive circuit for a matrix display device which receives a video signal and a low-speed clock signal synchronized with the video signal.

[0002]

2. Description of the Related Art A CRT (Cathode Ray Tube) display has been conventionally used as a display device of a control device such as a computer. When this CRT display is replaced with a matrix display device, in addition to the conventional video signal, horizontal and vertical synchronizing signals, a pixel clock signal synchronized with these is required.

FIG. 2 is a block diagram of a conventional example in the case of receiving a signal from the control device 1 and displaying an image on the matrix display device 3 via the drive circuit 2. In FIG.
The horizontal and vertical sync signals are combined in the video signal V, and are separated into horizontal and vertical sync signals (Hs, Vs) by the sync separation circuit 4 of the drive circuit 2. Furthermore, the horizontal synchronization signal H
s is input to, for example, a PLL (Phase Locked Loop) circuit to generate a pixel clock signal DCLK '(first conventional example).

When the image clock signal reproducing circuit such as the PLL circuit is not built in, as shown by the broken line in the figure,
The pixel clock signal DCLK is directly received from the pixel clock generation circuit 7 of the control device 1 (second conventional example).

The signal processing circuit 6 converts the above-mentioned video signal V and timing signals Hs, Vs and DCLK into a video signal Vm and a control signal Sm suitable for a display device, and achieves display by these signals.

FIG. 3 is a timing diagram of the video signal V, the horizontal synchronizing signal Hs, and the pixel clock signal DCLK. When an image is displayed on the matrix display device, at least the number of pixel clocks of the number of horizontal pixels of the display device is required in one horizontal scanning period (1H). The frequency of this pixel clock signal increases as the display scale increases. For example,
When the number of display dots is 1000 × 1000, the pixel clock signal frequency reaches about 100 MHz.

[0007]

SUMMARY OF THE INVENTION In the above conventional technique,
In particular, no consideration is given to the pixel clock signal when the display scale is large. That is, in the above-mentioned first conventional example, since the phase synchronization is achieved during the horizontal scanning period 1H, the period of the pixel clock signal may fluctuate during this period. For example, in the case of the video signal shown in FIG. 3, where the screen brightness should change linearly in the horizontal direction under normal conditions, the brightness shown by the broken line in FIG. 3 may be displayed. is there.

In the second conventional example, since the pixel clock signal DCLK has a high frequency, the drive circuit 2 is apt to malfunction due to signal transmission attenuation, noise, etc., and the display image is disturbed. It will be easier. In particular, inconvenience occurs when the control device 1 and the drive circuit 2 are separated from each other.

The present invention has been made in view of the above circumstances, and receives a low-speed clock from the control device and converts the low-speed clock again by a circuit inside the drive to generate a stable pixel clock signal DCLK. It is intended to provide a drive circuit for a matrix display device which can obtain a good display by generating.

[0010]

According to the present invention, a signal obtained by synchronously dividing a pixel clock signal DCLK synchronized with a video signal is received from a control device, and this is converted into a pixel clock signal DCLK again by a drive circuit. A drive circuit of a matrix display device characterized by the above.

[0011]

The controller transmits the composite video signal and the frequency division signal synchronized with the pixel clock signal. On the drive circuit side,
A PLL circuit that operates in synchronization with this frequency-divided signal is provided, and this generates a pixel clock signal DCLK.
Therefore, signal attenuation and noise between the control device and the drive circuit are reduced. Furthermore, since the synchronization is performed a plurality of times during the horizontal scanning period (1H), the fluctuation of the pixel clock signal cycle is alleviated. Therefore, since a stable clock is supplied to the matrix display device, a good display can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 4.

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 4 is a timing explanatory diagram thereof. In FIGS. 1 and 4, the same reference numerals as those in FIGS. 2 and 3 indicate the same constituent elements.

In FIG. 1, reference numeral 1 denotes a control device in which a video signal generation source (not shown) and a pixel clock signal DCLK are provided.
The generating circuit 7 and its frequency dividing circuit 8 are incorporated. The cycle of the output signal of the frequency dividing circuit 8 is set to be at least shorter than the horizontal scanning cycle 1H.

FIG. 4 is a timing chart of the pixel clock signal DCLK and the frequency divider circuit output 1/8 DCLK when the frequency division ratio is 8. The frequency division ratio is set to a ratio that does not cause a malfunction due to signal attenuation, external noise, etc., taking into consideration the distance between the control device 1 and the drive circuit 2. In the figure, one cycle of the pixel clock signal DCLK corresponds to one pixel of the video signal.

On the other hand, the drive circuit 2 uses the above-mentioned video signal V
And the frequency-divided signal ⅛DCLK, the former performs the synchronous separation in the synchronous separation circuit 4, and the latter reproduces the pixel clock signal DCLK via the PLL circuit 5. The PLL circuit 5 is
In this embodiment, the output is designed to have a frequency eight times the frequency of the input signal. Therefore, in FIG.
The PLL circuit operates on the path (a '), and the pixel clock signal DCLK' is generated thereby. That is, the signal DCLK 'is synchronized with the cycle of the frequency-divided signal ⅛DCLK (8 pixel units), so that it is a stable clock with little cycle fluctuation in the horizontal scanning period.

The signal processing circuit 6 performs signal processing based on the above signals and converts them into a video signal Vm and a control signal Sm suitable for a matrix display device. Since these signals have different signal forms depending on the display device and are not the essence of the present invention, they are omitted.

[0018]

According to the present invention, a stable pixel clock signal can be obtained, so that the operation of the drive circuit is stable and therefore the display quality of the matrix display device is improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a conventional circuit configuration diagram.

FIG. 3 is a timing explanatory diagram of one horizontal scanning cycle.

FIG. 4 is a detailed timing chart.

[Explanation of symbols]

3 ... Matrix display device, 5 ... PLL circuit, 1/8 DC
LK ... Divided output signal, DCLK ... Pixel clock signal.

Claims (3)

[Claims] 1. A drive circuit for receiving a video signal using a pixel clock signal as a reference signal and a clock synchronized with the video signal, and converting the video signal and the control signal suitable for driving a matrix display device, The drive circuit of the matrix display device, wherein the clock signal has a cycle shorter than that of the horizontal scanning signal and is a signal (frequency division ratio: a) obtained by frequency division in synchronization with the pixel clock signal. 2. The drive circuit for a matrix display device according to claim 1, further comprising a circuit which receives the clock signal as an input and multiplies a frequency division ratio (a) to reproduce a pixel clock signal. 3. A drive circuit for a matrix display device according to claim 2, wherein the circuit for reproducing the pixel clock signal is a phase synchronization (phase locked loop) circuit.