JPH07335891A - Activation method of impurities, thin film transistor and its manufacture, and liquid crystal display - Google Patents

Abstract

PURPOSE:To activate impurities implanted in a polycrystalline silicon film, by implanting specific ions in a polycrystalline silicon film on an insulating substrate and an insulating film deposited on the polycrystalline silicon film, by using an ion implanter without using mass separation, implanting hydrogen ions, and heating the insulating substrate in a specific temperature range. CONSTITUTION:Impurity ions 2 formed from mixed gas wherein PH3 of 10% or less is contained and the residual part is composed of helium are implanted through an SiO2 film deposited on a polycrystalline silicon film formed on an insulating substrate 5, by using an ion implanter without using mass separation. Hydrogen ions 2 formed from a pure oxygen gas are continuously implanted by using an ion implanter without using mass separation. The insulating substrate 5 is heat-treated at a temperature 300 deg.C or higher and 600 deg.C or lower A trace amount of impurities implanted in the polycrystalline silicon film is activated by heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for activating a trace amount of impurities implanted in a polycrystalline silicon film, a thin film transistor, a method for manufacturing the same, and a liquid crystal display device.

[0002]

2. Description of the Related Art One of the important characteristics of a thin film transistor for driving a pixel used in a liquid crystal display device is reduction of leak current. This leakage current is preferably as small as possible, and it is desired that it does not exceed at least 1 pA. As a means for reducing the leak current, it has been reported that the effect of thinning the silicon film in the channel portion of the thin film transistor and using a plurality of gate electrodes of the thin film transistor. However, there is a limit to thinning the silicon film in the channel portion, and making a plurality of thin film transistor gate electrodes has a drawback that the aperture ratio, which is one of the important qualities of a liquid crystal display device, is reduced. . On the other hand, LD
It is reported in Japanese Patent Publication No. 3-38755 that the leak current can be reduced by using a thin film transistor having a D (Lightly Doped Drain) structure. The LDD structure is certainly a structure capable of solving the above-mentioned drawbacks, but in order to manufacture a thin film transistor having the LDD structure, for example, an ion implantation technique used in a general semiconductor manufacturing technique was used. In this case, activation of impurities implanted in the source / drain regions of the thin film transistor requires a high temperature of 600 ° C. or higher. for that reason,
Inexpensive glass substrates cannot be used. Also recently
When using an ion implanter that does not use mass separation, which is premised on the use of a large-area glass substrate that has been developed, a mixed gas that contains an impurity gas as a doping gas and is diluted with hydrogen is used to 300 ° C when injected
M. Matsuo is able to activate impurities at low temperature.
et al .: Jpn. J. Appl. Phys. 31 (1992) 4567 and JP-A-4-370937. FIG. 3 is a cross-sectional view of an example of an ion implantation apparatus that does not use mass separation. Impurity ions 2 are extracted from the plasma source 1 by the extraction electrode 3, the impurity ions 2 are accelerated by the acceleration electrode 4 to have a predetermined energy, and the thin film transistor formed on the glass substrate 5 is implanted to form source / drain regions. . The energy given to the impurity ions 2 is determined by the sum of the voltage of the extraction electrode 3 and the voltage of the acceleration electrode 4. It takes 13.5 to generate plasma as in this example.
There is a method using a filament or the like in addition to the method using a high frequency of 6 MHz. However, in the technique reported above, 1 × 10 ¹⁹ pieces / cm ³ such as an LDD region is used.
The following trace impurities could not be activated at low temperatures below 600 ° C. 1 × 10 ¹⁹ contained in the LDD region
As a method for activating a minute amount of impurities of less than 60 pieces / cm ^{3 at} a low temperature of less than 600 ° C., M. Matsue
t al. : Extend Abstract o
f the Conference on Solid
State Devices and Material
als, Makuhari, 1993 pp. 43
A method has been proposed in which a specific amount of hydrogen is additionally implanted only into the LDD region of a thin film transistor after the implantation of impurities as reported in 7-439. However, even in the technique reported above, since the doping gas used at the time of injecting a slight amount of impurities is diluted with hydrogen, it goes without saying that, at the same time when the impurities are injected into the LDD region, hydrogen is entirely supplied to the TFT element. Is also caused, and there is a defect that it is difficult to control the injection amount of hydrogen in the LDD region to be additionally injected and the deterioration of TFT characteristics. In order to prevent the implantation of hydrogen into the TFT element, JP-A-2-202028 proposes a method of using a helium-diluted gas as a doping gas for an ion implantation apparatus that does not use mass separation. The formation of the LDD region is difficult because hydrogen injection is suppressed in all regions of the device.

[0003]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to remove impurity ions in an amount of 1 × 10 ¹⁹ ions / cm ³ or less implanted by using the ion implantation apparatus which does not use mass spectrometry. Provided is a method that is activated at a low temperature of less than 600 ° C. and is highly controllable, and a method for stably forming a thin film transistor having an LDD structure on an inexpensive glass substrate, and a liquid crystal display device. is there.

[0004]

DISCLOSURE OF THE INVENTION The present invention is to solve the above-mentioned problems, and a polycrystalline silicon film formed on an insulating substrate and an insulating film deposited on the polycrystalline silicon film. The film contains a gas serving as a donor or an acceptor by using an ion implanter that does not use mass separation, and all the ions generated from a mixed gas containing helium as the balance pass through the insulating film into the polycrystalline silicon film. Implantation, and then using the ion implantation device without mass separation, hydrogen ions generated from pure hydrogen gas are implanted into the polycrystalline silicon film through the insulating film, and then the insulating substrate is It is characterized in that it is heated to 300 ° C. or higher to activate the impurities implanted in the polycrystalline silicon film.

[0005]

【Example】

(Example 1) FIG. 1 is a schematic view showing that a polycrystalline silicon film having a thickness of 500 Å formed on an insulating substrate is subjected to heat treatment at 300 ° C. for one hour by using phosphorus as an impurity. It is an example showing the sheet resistance value with respect to the amount of H ⁺ ion implantation at that time. The heat treatment temperature is preferably 300 ° C. or higher and 600 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower, and even more preferably 3
The temperature is preferably 00 ° C or higher and 350 ° C or lower. If the activation temperature decreases, the number of glass substrates that can be used increases, and a cheaper substrate can be used. In addition, the expansion and contraction of the substrate are reduced, and there is an advantage that an alignment error in manufacturing a thin film transistor can be reduced. As the polycrystalline silicon film, a film having a crystallization rate of 75% or more, preferably 90% or more is used. The method for producing the polycrystalline silicon film in the first period is not particularly limited, but a method using laser irradiation, a low pressure chemical vapor deposition method (LPCVD method), a plasma chemical vapor deposition method (PCVD method), or the like can be used. In FIG. 1, impurities are PH ₃ of more than 0% and less than 10%, preferably more than 0.01% and less than 5% by using the ion implantation apparatus without mass separation shown in FIG. Preferably, the amount of ions produced from a mixed gas containing more than 0.1% and 1% or less and the balance of helium is 8
Through the SiO ₂ film having a thickness of 1200 Å deposited on the polycrystalline silicon film so that the number of P ⁺ ions is 1 × 10 ¹⁴ / cm ² at an energy of ⁰ keV. Drive in. Concentration of impurities is 10%
If it exceeds, the amount of impurities accumulated in the plasma generation chamber increases, and the maintenance of the apparatus must be frequently performed. If the concentration of impurities to be implanted is 1 × 10 ¹⁴ / cm ² or less as in the present invention, the amount of impurity ions per unit time of implantation is 1 × 10 ¹² / cm ² · sec.
Below, in order to improve the controllability of the amount of impurities in the implantation, the concentration of the gas as impurities is preferably 1% or less. At this time, the maximum concentration of the implanted P ⁺ ions in the polycrystalline silicon film is 1 × 10 ¹⁹ / cm ³ . At the same time, helium ions are implanted into the silicon film at a maximum concentration of 2 × 10 ¹⁹ ions / cm ³ or more, but the helium ions are electrically inactive and have no electrical effect on the silicon film. . Hydrogen ions generated from 100% hydrogen gas are continuously implanted with an energy of 20 keV by using the ion implantation apparatus that does not use the mass separation. The energy at the time of implantation can be appropriately adjusted by the thickness and type of the gate insulating film and the type of implanted ions, as in the case of the ion implantation apparatus generally used for manufacturing semiconductor devices. It is not limited to. For example, in the case of using the ion implantation apparatus shown in FIG. 3, which does not use mass separation, most of the ions ionized from 100% hydrogen gas are H ₂ ⁺ , and in order to carry out hydrogenation efficiently, _The implantation energy is set to 20 keV so that the maximum concentration of ₂ ^{+ in} the depth direction comes to the interface between the polycrystalline silicon film and the SiO ₂ film of the previous period. However, when H ⁺ is generated as the main ions, the same effect can be obtained by setting the energy at the time of implantation to about 10 keV. In addition, the above-mentioned SiO ₂
When the film thickness is 800 Å, PH ₃ exceeds 0% and exceeds 10% by using the above-mentioned ion implantation system without mass separation.
% Or less, preferably more than 0.01% and 5% or less, and more preferably more than 0.1% and 1% or less, and the ions generated from a mixed gas with the balance being helium are converted into P ⁺ ions at an energy of 50 keV. A thickness of 800Å deposited on the polycrystalline silicon film so that the maximum concentration of implanted phosphorus in the polycrystalline silicon film is 1 × 10 ¹⁹ pieces / cm ^3. 6.5 × 10 ¹³ ions / cm ^{2 are} implanted through the SiO ₂ film having the above-mentioned impurities, and the ion implantation device without mass separation is continuously used to obtain 10
Hydrogen ions generated from 0% hydrogen gas may be implanted with an energy of 12 keV. In the present embodiment, when the impurity ions and hydrogen ions are implanted, the implantation energy is set so that the peak concentration of the implanted ions becomes the maximum concentration, but the maximum concentration is not necessarily implanted. It does not have to match the peak concentration determined. Since the distribution of the implanted ions shows a normal distribution, for example, the implantation energy can be set so that the peak concentration of the implanted ions in the SiO ₂ film comes and the tail of the broadened distribution can be used. And
This is an easy analogy. That is, it is clear that the present invention does not limit the implantation energy. As can be seen from this example, in the polycrystalline silicon film in which a slight amount of impurities are implanted, the amount of implanted H ⁺ ions is 1 × 10 ¹⁴ ions / cm ² or more and 1 × 10 ¹⁵ ions / cm ² or less. In the case of quantity, more preferably 3 × 10 ¹⁴ pieces / cm ²
When the implantation amount is 7 × 10 ¹⁴ pieces / cm ² or less, that is, the maximum concentration in the polycrystalline silicon film is 6 × 10 ^18.
1 × 10 ²⁰ / cm ³ or less in the range in number / cm ³ or more, still low preferably when in the range of 4.2 × 10 ¹⁹ atoms / cm ³ or less 1.8 × 10 ¹⁹ atoms / cm ³ or more To resist. This is due to the effect of termination of asymmetric bonds in the polycrystalline silicon film by the implanted hydrogen ions and competition with the defects caused by the implanted hydrogen ions. Figure 2
According to the present invention, phosphorus as an impurity implanted into a polycrystalline silicon film having a thickness of 500 Å formed on an insulating substrate at 300 ° C. is subjected to a heat treatment for one hour with respect to the implantation amount of phosphorus ions. It is one example which shows a sheet resistance value. The heat treatment temperature is preferably 300 ° C. or higher and 6
00 ° C or lower, more preferably 300 ° C or higher and 450 ° C
The temperature is more preferably 300 ° C. or higher and 350 ° C. or lower. The polycrystalline silicon film has a crystallization rate of 75.
% Or more, preferably 90% or more of the film is used. In FIG. 2, impurities are obtained by using the ion implantation apparatus shown in FIG. 3 which does not use mass separation, and PH ₃ is more than 0% and 10% or less, preferably more than 0.01% and 5% or less, It is preferable that the amount of ions generated from the mixed gas containing 0.1% or more and more than 0.1% and the balance being helium is 1 × 10 ¹² ions / cm ² to 1 × 1 in terms of P ⁺ ions at an energy of 80 keV.
The SiO ₂ film having a thickness of 1200 Å deposited on the polycrystalline silicon film is implanted into the polycrystalline silicon film so that the number becomes 0 ¹⁴ pieces / cm ² . At this time, the maximum concentration of implanted phosphorus in the polycrystalline silicon film is 1 ×
From 10 ¹⁷ pieces / cm ³ to 1.1 × 10 ¹⁹ pieces / cm ³ . In addition, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 1 × 10 ¹⁸ pieces / cm ³ or more,
Helium is electrically inactive and has no electrical effect on the silicon film. Using the ion implantation apparatus without using the above mass separation, hydrogen ions produced from 100% hydrogen gas at an energy of 20 keV and the maximum concentration of the implanted H ⁺ ions in the polycrystalline silicon film were obtained. Is 6 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³
The following range, more preferably within a range of 1.8 × 10 ¹⁹ pieces / cm ³ or more and 4.2 × 10 ¹⁹ pieces / cm ³ or less,
The range of 1 × 10 ¹⁴ pieces / cm ² to 1 × 10 ¹⁵ pieces / cm ² , more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ²
Enter within the following range. The energy at the time of implantation can be adjusted at any time depending on the thickness and type of the gate insulating film and the type of implanted ions, and is not limited to this embodiment. As shown in FIG. 2, the trace amount of impurities implanted in the polycrystalline silicon film is
It is apparent that the present invention activates the heat treatment at 300 ° C. According to the present invention, since helium is used as the diluent gas, the plasma is stabilized, and the controllability of the amount of implanted impurities is increased. In addition, helium ions do not etch the oxide film, have less damage to the silicon film, and do not cause unnecessary characteristic changes that occur due to the implantation of a large amount of hydrogen.

Example 2 FIG. 4 is a sectional view of an example of a thin film transistor manufactured by using the present invention.
SiO ₂ for preventing diffusion of heavy metals from the glass substrate 5
Film 6, film thickness 500 to be a channel portion of a thin film transistor
A polycrystalline silicon film 7 having a thickness of about Å, a SiO ₂ film having a film thickness of 1200 Å formed as a gate insulating film 8, a gate electrode 9 made of Ta, Al or Cr, an n ⁻ type source / drain region 10 of a thin film transistor, An interlayer insulating film 11 made of SiO ₂ , a source electrode 12 made of Al,
A drain electrode 13 made of Al or ITO is shown. The embodiment of FIG. 4 will be described with reference to the process chart of FIG.
First, as shown in FIG. 5A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The SiO ₂ film 6 is made of a heavy metal contained in the substrate,
The purpose is to prevent diffusion to the element part during heat treatment,
It is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used.
Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 6000 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 5 (b), using an ion implantation apparatus that does not use the mass spectrometer shown in FIG. 3, the PH ₃ 10% over 0%
All the ions 14 produced from the doping gas, which are contained in a concentration of 0.01% to 5% and more preferably 0.1% to 1% and more preferably 0.1% to 1%, are P ⁺ ions. The driving amount is 3 × 10 ¹³ pieces / c
Implanting with an energy of about 80 keV so as to be in a range of 1 × 10 ¹⁴ pieces / cm ² or less at m ² or more, more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / cm ² or less. . Further, at this time, the maximum concentration of helium implanted at the same time in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. It has no effect. Next, as shown in FIG. 5 (c), by using the above-mentioned ion implantation apparatus that does not use mass spectrometry, 1 × 10 ^{14 of} all the ions 15 that generate pure hydrogen as a doping gas are generated at an energy of about 20 keV. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 1
Implantation is performed within a range of 0 ¹⁴ / cm ² or less to form n ⁻ type source / drain regions 10. The energy at the time of implantation may be adjusted appropriately depending on the thickness of the gate insulating film,
The present invention is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG.
Impurities in the drain region are activated by performing heat treatment at 300 ° C. for 1 hour, an SiO ₂ film is deposited as an interlayer insulating film 11 to a thickness of 5000 Å or more, contact holes are formed in the source / drain regions 10, and source / drain regions 10 are formed. The electrode 16 is formed of Al, ITO or the like in the drain region. According to the present invention, a thin film transistor having an LDD structure is manufactured by
It is possible to manufacture stably at a low temperature of about ℃.

FIG. 6 shows a thin film transistor manufactured according to the present invention, in which V _DS is 4 V and V _G is 10 V, drain current 17 and V _DS are 4 V and V _G is −10.
It is a figure which shows the correlation of the drain current 18 when V is set, and the implantation amount of phosphorus. From FIG. 6, the above-mentioned phosphorus implantation amount is in the range of 3 × 10 ¹³ pieces / cm ² or more and 1 × 10 ¹⁴ pieces / cm ² or less, and more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10.
^In the range of ¹³ pieces / cm ² or less, that is, when the maximum concentration of phosphorus in the polycrystalline silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, 1 × 10 ¹⁹ pieces / c
m ³ or less, more preferably 3 × 10 ¹⁸ pieces / cm ³ or more and 7 ×
It is understood that in the range of 10 ¹⁸ cells / cm ³ or less, the electric field between the gate electrode and the drain region of the thin film transistor is relaxed, and the leak current of the thin film transistor can be reduced.

Example 3 FIG. 7 is a sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, film thickness 5 to be the channel part of the thin film transistor
Polycrystalline silicon film 7 of about 00Å, SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film, T
a, a gate electrode 9 made of Al, Cr, an n ⁻ type source / drain region 10 of the thin film transistor, an n ⁺ layer 19 provided immediately below a contact hole of the thin film transistor,
An interlayer insulating film 11 made of SiO ₂ , a source electrode 12 made of Al, and a drain electrode 13 made of Al or ITO are shown. The embodiment of FIG. 7 will be described with reference to the process chart of FIG. First, as shown in FIG. 8A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, the polycrystalline silicon film 7 containing no impurities is formed into 50
Deposit and pattern with a thickness of 0Å. The crystallization rate of the polycrystalline silicon is 75% or more, preferably 90%
The above film is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, Al, C
600 with low resistance metal such as r and Ta by sputtering method
The gate electrode 9 is formed by depositing with a thickness of about 0Å and patterning. Next, as shown in FIG. 8 (b), the ion implantation apparatus without mass spectrometry shown in FIG.
₃ 10% or less than 0%, preferably 5% than 0.01% or less, more preferably comprises less than 1% concentration exceeds 0.1%, all generated from a doping gas balance being helium the ion 14, P ⁺ implantation of ions 3 × 10 ¹³ / cm ² or more at 1 × 10 ¹⁴ / cm ² or less in the range, more preferably 3 × 10 ¹³ / cm ² or more at 7 × 1
Implantation is performed with energy of about 80 keV so as to be a range of 0 ¹³ pieces / cm ² or less. Further, at this time, the maximum concentration of helium simultaneously implanted in the silicon film is 3 × 10 5.
^{Although it is 18} pieces / cm ³ or more, helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 8 (c), all ions 15 generated with pure hydrogen as a doping gas are converted to 20 ke
1 × 1 with energy of V about 1 × 10 ¹⁴ pieces / cm ² or more
0 ^{1 5} / cm ² or less in the range, more preferably implanted at 3 × 10 ¹⁴ / cm ² or more at 7 × 10 ¹⁴ / cm ² or less in the range,
An n ⁻ type source / drain region 10 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment.
According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 8D, a SiO ₂ film is formed as an interlayer insulating film 11 at a thickness of 5000 Å.
PH ₃ is deposited to the above thickness, then contact holes are formed in the source / drain regions 10, and PH ₃ is more than 0% and 10% or less, preferably 0 by using the above ion implantation apparatus without mass separation. All the ions 20 which are contained at a concentration of more than 0.01% and 5% or less and the balance is H ₂ or helium, and the implantation amount of P ⁺ ions is 1 × 10 ¹⁵ / cm ² or more, The n ⁺ layer 19 is formed by implanting with an energy of 30 keV so that the concentration peak of the impurity phosphorus is near the center of the polycrystalline silicon film below the contact hole. In the formation of the n ⁺ layer, any of H _{2 and} helium can be used as the doping gas for the doping gas used for implantation. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Finally, as shown in FIG. 8E, the impurities in the source / drain regions are heat-treated at 300 ° C. for 1 hour to be activated,
Al or IT in the contact hole of the source / drain region
The electrode 16 is formed of O or the like. In this embodiment, since a polycrystalline silicon layer having a high concentration of impurities is present at the contact portion between the source / drain region of the thin film transistor and the electrode such as Al or ITO, the electrode and the source / drain region are It is possible to reduce the contact resistance with. Further, no special mask is required to provide the polycrystalline silicon layer in which the above impurities are implanted in high concentration.

Example 4 FIG. 9 is a sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, film thickness 5 to be the channel part of the thin film transistor
Polycrystalline silicon film 7 of about 00Å, SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film, T
a, a gate electrode 9 made of Al, Cr, an n ⁻ type source / drain region 10 of a thin film transistor, an n ⁺ type source / drain region 19 of a thin film transistor, an interlayer insulating film 11 made of SiO ₂ , and Al Source electrode 12 and drain electrode 1 formed of Al or ITO
3 is shown. The embodiment of FIG. 9 will be described with reference to the process chart of FIG. First, as shown in FIG. 10A, the glass substrate 5
A SiO ₂ film 6 as an insulating film is deposited thereon with a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, Al, Cr and Ta
A low resistance metal such as is deposited to a thickness of about 6000 Å by sputtering or the like, and is patterned to form the gate electrode 9. Next, as shown in FIG. 10 (b), PH ₃ was set to 0% by using the ion implantation apparatus without mass spectrometry shown in FIG.
To 10% or less, preferably 0.01% to 5% or less, more preferably 0.1% to 1% or less, with the balance being all ions 14 generated from the doping gas consisting of helium. , P ⁺ ion implantation amount is 3 ×
A range of 10 ¹³ pieces / cm ² or more and 1 × 10 ¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / c
Implant with an energy of about 80 keV so that the range is m ² or less. In addition, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 3 × 10 ¹⁸ pieces / cm ³
As described above, helium is electrically inactive and does not affect the electrical characteristics of thin film transistors.
Next, as shown in FIG. 10 (c), by using the above-mentioned ion implantation apparatus without mass spectrometry, 1 × 10 ¹⁴ ions 15 are generated with an energy of about 20 keV as pure ions 15 generated as a doping gas. / Cm ² or more 1 × 10 ¹⁵ pieces / c
The n ⁻ -type source / drain region 10 is formed by implanting in the range of m ² or less, more preferably in the range of 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG.
A part of the thin film transistor including the gate electrode is a resist or an organic material such as polyimide or a gate electrode,
An inorganic material that is selectively etched away from the gate insulating film, such as Al or C when Ta is used for the gate electrode
masked with r or the like and using the above-mentioned ion implantation device without mass separation, containing PH ₃ in a concentration of more than 0% and 10% or less, preferably more than 0.01% and 5% or less, All the ions 20 generated from the doping gas whose balance consists of H ₂ or helium are set to 80 ke so that the implantation amount of P ⁺ ions is 1 × 10 ¹⁵ ions / cm ² or more.
Implanting with an energy of about V forms an n ⁺ layer in the source / drain regions of the thin film transistor. In the formation of the n ⁺ layer, any of H _{2 and} helium can be used as the doping gas for the doping gas used for implantation. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Next, as shown in FIG. 10E, the interlayer insulating film 11
As a SiO ₂ film, a thickness of 5000 Å or more is deposited, and then contact holes are formed in the source / drain regions 10. Finally, the impurities in the source / drain region are set to 300
Heat treatment is performed at 1 ° C. for 1 hour to activate the electrodes, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al or ITO. In this embodiment, since a polycrystalline silicon layer having a high concentration of impurities is present at the contact portion between the source / drain region of the thin film transistor and the electrode such as Al or ITO, the electrode and the source / drain region are It is possible to reduce the contact resistance with. In addition, since the implantation energy for forming the n ⁺ layer can be increased, the ion beam current can be increased and the productivity can be improved.

Embodiment 5 FIG. 11 is a sectional view of another embodiment of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
An O ₂ film 6, a polycrystalline silicon film 21 having a film thickness of about 1000 Å which becomes a part of the source / drain of a thin film transistor, a polycrystalline silicon film 7 having a film thickness of about 500 Å which becomes a channel part of a thin film transistor, and a gate insulating film were formed. 1
SiO ₂ film 8 with a film thickness of 200Å, Ta, Al, C
a gate electrode 9 made of r, an n ⁻ type source / drain region 10 of a thin film transistor, an interlayer insulating film 11 made of SiO ₂ , a source electrode 12 made of Al, and a drain electrode 13 made of Al or ITO. Show. The embodiment of FIG. 11 will be described with reference to the process chart of FIG. First, as shown in FIG. 12A, a SiO ₂ film 6 is deposited as an insulating film on the glass substrate 5 to a thickness of 2000 Å, and then a polycrystalline silicon film 21 is deposited to a thickness of 1000 Å and then patterned. To do. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, the polycrystalline silicon film 7 containing no impurities is formed into 50
Deposit and pattern with a thickness of 0Å. The polycrystalline silicon films 7 and 21 have a crystallization rate of 75% or more, preferably 90% or more. Next, the SiO ₂ film 1
The gate insulating film 8 is formed by depositing it with a thickness of about 200Å. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 6000 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 12 (b), using an ion implantation apparatus shown in FIG. 3 which does not use mass spectrometry, PH ₃ exceeds 0% and 10% or less, preferably 0.01% and 5% or less. , And more preferably 0.1%
Of all the ions 14 generated from the doping gas containing helium with a concentration of more than 1% and less than 1%, P ⁺
1 × 1 when the ion implantation amount is 3 × 10 ¹³ ions / cm ² or more
The implantation is performed with an energy of about 80 keV so as to be a range of 0 ¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / cm ² or less. Further, at this time, the maximum concentration of helium implanted at the same time in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. It has no effect. Next, as shown in FIG. 12C, all the ions 15 generated by using pure hydrogen as a doping gas are subjected to 1 × 10 ¹⁴ at an energy of about 20 keV by using the ion implantation apparatus which does not use the mass spectrometry. pieces / cm ² or more at 1 × 10 ¹⁵ / cm ² or less in the range, more preferably implanted at 3 × 10 ¹⁴ / cm ² or more at 7 × 10 ¹⁴ / cm ² or less in the range of n ^- -type source Form the drain region 10. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 12D, the impurities in the source / drain regions are activated by performing a heat treatment at 300 ° C. for 1 hour in a nitrogen atmosphere, and an SiO ₂ film is formed as an interlayer insulating film 11 by etching.
Source / drain region 1 deposited with a thickness of 000Å or more
A contact hole is formed at 0, and an electrode 16 is formed in the source / drain region with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick, and therefore the resistance value of the source / drain region can be reduced. Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

Example 6 FIG. 13 is a cross-sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
An O ₂ film 6, a polycrystalline silicon film 21 having a film thickness of about 1000 Å which becomes a part of the source / drain of a thin film transistor, a polycrystalline silicon film 7 having a film thickness of about 500 Å which becomes a channel part of a thin film transistor, and a gate insulating film were formed. 1
SiO ₂ film 8 with a film thickness of 200Å, Ta, Al, C
a gate electrode 9 made of r, an n ⁻ type source / drain region 10 of the thin film transistor, an n ⁺ type source / drain region 19 of the thin film transistor, an interlayer insulating film 11 made of SiO ₂ , and a source electrode 12 made of Al. , Al
Alternatively, the drain electrode 13 formed of ITO is shown.
The embodiment of FIG. 13 will be described with reference to the process chart of FIG.
First, as shown in FIG. 14A, a SiO ₂ film 6 as an insulating film is deposited to a thickness of 2000 Å on a glass substrate 5, and then a polycrystalline silicon film 21 is deposited to a thickness of 1000 Å.
Pattern. The SiO ₂ film 6 is for the purpose of preventing heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and the purity of the substrate need not be sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is formed to 500
Å Deposit with a thickness of about Å and pattern. The polycrystalline silicon films 7 and 21 have a crystallization rate of 75% or more, preferably 90% or more. Next, the SiO ₂ film 12
The gate insulating film 8 is formed by depositing it to a thickness of about 00Å.
Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, as shown in FIG. 14 (b), using the ion implantation apparatus shown in FIG. 3, which does not use mass spectrometry, PH ₃ exceeds 0% and 10% or less, preferably 0.01% and 5% or less. More preferably, the concentration of all ions 14 generated from the doping gas containing 0.1% or more and more than 0.1% with the balance being helium has a P ⁺ ion implantation amount of 3 × 10 ¹³ ions / cm ² or more. 1 x 10
¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / c
8 to be in the range of 7 × 10 ¹³ pieces / cm ² or less at m ² or more
Implant with energy of about 0 keV. Further, at this time, the maximum concentration of helium implanted at the same time in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. It has no effect. Next, as shown in FIG. 14 (c), using the ion implantation apparatus that does not use the mass spectrometry described above, 1 × 10 ¹⁴ ions 15 are generated at an energy of about 20 keV with respect to all the ions 15 that generate pure hydrogen as a doping gas. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less, and n ⁻ type source. The drain region 10 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 14D, Si is used as the interlayer insulating film 11.
Deposit an O ₂ film with a thickness of 5000 Å or more, then
A contact hole is formed in the drain region 10 and PH ₃ is more than 0% and less than 10%, preferably more than 0.01% by using the above ion implantation apparatus without mass separation.
% Of all the ions 20 produced from the doping gas containing H ₂ or helium in the balance,
The implantation amount of P ⁺ ions is 1 × 10 ¹⁵ / cm ² or more, and the concentration of the impurity phosphorus is 30 k so that the peak of the impurity phosphorus concentration is near the center of the polycrystalline silicon film below the contact hole.
Drive with eV energy. In the formation of the n ⁺ layer, any of H _{2 and} helium can be used as the doping gas for the doping gas used for implantation. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Finally Figure 1
As shown in FIG. 4E, the impurities in the source / drain regions are heat-treated at 300 ° C. for 1 hour to be activated, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor has a large film thickness, so that the resistance value of the source / drain region can be further reduced. Also n ⁺ type source
No special mask is required to form the drain region.

Example 7 FIG. 15 is a sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
An O ₂ film 6, a polycrystalline silicon film 21 having a film thickness of about 1000 Å which becomes a part of the source / drain of a thin film transistor, a polycrystalline silicon film 7 having a film thickness of about 500 Å which becomes a channel part of a thin film transistor, and a gate insulating film were formed. 1
SiO ₂ film 8 with a film thickness of 200Å, Ta, Al, C
a gate electrode 9 made of r, an n ⁻ type source / drain region 10 of the thin film transistor, an n ⁺ type source / drain region 19 of the thin film transistor, an interlayer insulating film 11 made of SiO ₂ , and a source electrode 12 made of Al. , Al
Alternatively, the drain electrode 13 formed of ITO is shown.
The embodiment of FIG. 15 will be described with reference to the process chart of FIG.
First, as shown in FIG. 16A, a SiO ₂ film 6 is deposited as an insulating film on the glass substrate 5 to a thickness of 2000 Å, and then a polycrystalline silicon film 21 is deposited to a thickness of 1000 Å,
Pattern. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, the polycrystalline silicon film 7 containing no impurities is formed into 5
Deposit with a thickness of about 00Å and pattern. The crystallization rate of the polycrystalline silicon films 7 and 21 is 75% or more,
Preferably, 90% or more of the film is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, as shown in FIG. 16 (b), using the ion implantation apparatus shown in FIG. 3, which does not use mass spectrometry, PH ₃ exceeds 0% and 10% or less, preferably 0.01% and 5% or less. , And more preferably 0.1%
Of all the ions 14 generated from the doping gas containing helium with a concentration of more than 1% and less than 1%, P ⁺
1 × 1 when the ion implantation amount is 3 × 10 ¹³ ions / cm ² or more
The implantation is performed with an energy of about 80 keV so as to be a range of 0 ¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / cm ² or less. Further, at this time, the maximum concentration of helium implanted at the same time in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. It has no effect. Next, as shown in FIG. 16 (c), using the ion implantation apparatus that does not use the mass spectrometry, 1 × 10 ^{14 of} all the ions 15 that generate pure hydrogen as a doping gas with an energy of about 20 keV are produced. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less, and n ⁻ type source. The drain region 10 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 16D, a part of the thin film transistor including the gate electrode is an organic material such as resist or polyimide, or an inorganic material such as Ta that is selectively removed by etching with the gate electrode and the gate insulating film. When is used for the gate electrode, mask with Al or Cr,
Using the ion implanter without mass separation described above, P
All ions 2 produced from a doping gas containing H ₃ in a concentration of more than 0% and less than 10%, preferably more than 0.01% and less than 5% and the balance H ₂ or helium.
0 is implanted with energy of about 80 keV so that the amount of P ⁺ ions implanted is 1 × 10 ¹⁵ ions / cm ² or more,
In the source / drain region of the thin film transistor, n ⁺
Form the layers. In the formation of the n ⁺ layer, any of H _{2 and} helium can be used as the doping gas for the doping gas used for implantation. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Next, as shown in FIG. 16E, a SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, and then contact holes are formed in the source / drain regions 10. Finally, the impurities in the source / drain regions are activated by heat treatment at 300 ° C. for 1 hour in a nitrogen atmosphere, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor has a large film thickness, so that the resistance value of the source / drain region can be further reduced. Further, since the implantation energy can be increased when forming the n ⁺ type source / drain regions, there is an advantage that the ion beam current can be increased and the productivity is improved.

(Embodiment 8) FIG. 17 is a schematic cross-sectional view of an embodiment of the present invention in which an impurity boron of 300 is implanted into a polycrystalline silicon film having a thickness of 500 Å formed on an insulating substrate.
It is another example showing the sheet resistance value with respect to the H ⁺ ion implantation amount when the heat treatment is performed for one hour at ℃. The heat treatment temperature is preferably 300 ° C. or higher and 600 ° C.
Or less, more preferably 300 ° C or higher and 450 ° C or lower,
More preferably, the temperature is 300 ° C. or higher and 350 ° C. or lower. As a matter of course, if the activation temperature is lowered, the number of glass substrates that can be used is increased, and a cheaper substrate can be used. In addition, the expansion and contraction of the substrate are reduced, and there is an advantage that an alignment error in manufacturing a thin film transistor can be reduced. As the polycrystalline silicon film, a film having a crystallization rate of 75% or more, preferably 90% or more is used. The method for producing the polycrystalline silicon film in the first period is not particularly limited, but a method using laser irradiation, a low pressure chemical vapor deposition method (LPCVD method), a plasma chemical vapor deposition method (PCVD method), or the like can be used. FIG. 17
In the case of impurities, B ₂ H ₆ exceeds 10% by more than 10% by using the ion implantation apparatus without mass separation shown in FIG.
% Or less, preferably more than 0.01% and less than 5%, more preferably more than 0.1% and less than 1%, and the ions generated from a mixed gas with the balance being helium are converted into B ⁺ ions at an energy of 80 keV. Then, the polycrystal silicon film is implanted through the SiO ₂ film having a thickness of 1200Å deposited on the polycrystal silicon film so as to be 1 × 10 ¹⁴ pieces / cm ² . If the concentration of impurities exceeds 10%,
Accumulation of impurities in the plasma generation chamber increases, which requires frequent maintenance of the apparatus. When the concentration of impurities to be implanted is 1 × 10 ¹⁴ / cm ² or less as in the present invention, the amount of impurity ions per unit time of implantation is 1 × 10 ¹² / cm ² · sec or less, In order to improve the controllability of the amount of impurities in the implantation, the concentration of the gas that becomes impurities is preferably 1% or less. At this time, the maximum concentration of implanted B ⁺ ions in the polycrystalline silicon film is 1 × 10 ¹⁹ / cm ³ . At the same time, the maximum concentration of helium ions in the silicon film was 2 × 1.
Although more than 0 ¹⁹ ions / cm ³ are implanted, helium ions are electrically inactive and have no effect on the silicon film. Hydrogen ions generated from 100% hydrogen gas are continuously implanted with an energy of 20 keV by using the ion implantation apparatus that does not use the mass separation. The energy at the time of implantation can be appropriately adjusted by the thickness and type of the gate insulating film and the type of implanted ions, as in the case of the ion implantation apparatus generally used for manufacturing semiconductor devices. It is not limited to. For example, in the case of using the ion implantation apparatus shown in FIG. 3, which does not use mass separation, most of the ions ionized from 100% hydrogen gas are H ₂ ⁺ , and in order to carry out hydrogenation efficiently, 20 k so that the maximum concentration of ₂ ^{+ in} the depth direction comes to the interface between the polycrystalline silicon film and the SiO ₂ film of the previous period.
The eV implantation energy is set. However, H ⁺
When is generated as the main ion, the same effect can be obtained by setting the energy at the time of implantation to about 10 keV. Similarly, in the case of using the above-mentioned ion implanter without mass separation, B ₂ H ₆ is more than 0% and 10% or less, preferably more than 0.01% and 5% or less, further preferably 0.1% or more. %, The ions generated from the mixed gas containing 1% or less and the balance being helium are implanted with the energy of 80 keV because B ₂ H _x ⁺ ions are the main. However, when B ⁺ ions are mainly produced, the energy of 40 keV is sufficient. Further, in the present embodiment, when the impurity ions and hydrogen ions are implanted, the implantation energy is set so that the peak concentration of the implanted ions becomes the maximum concentration, but the maximum concentration is not necessarily the same. It does not have to match the peak concentration that was implanted. Since the distribution of the implanted ions shows a normal distribution, for example, setting the implantation energy so that the peak concentration of the ions implanted in the SiO ₂ film comes and using the tail of the broadened distribution, This is an easy analogy. That is, it is obvious that the present invention does not limit the implantation energy. As can be seen from this example, a polycrystalline silicon film implanted traces of impurities are implanted amount of the implanted H ⁺ ion amount is 1 × 10 ^{1 4} / cm ² or more at 1 × 10 ¹⁵
Range / piece ² / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ²
When the implantation amount is 7 × 10 ¹⁴ pieces / cm ² or less, that is, the maximum concentration in the polycrystalline silicon film is 6 × 10 ^18.
1 × 10 ²⁰ / cm ³ or less in the range in number / cm ³ or more, still low preferably when in the range of 4.2 × 10 ¹⁹ atoms / cm ³ or less 1.8 × 10 ¹⁹ atoms / cm ³ or more To resist. This is due to the effect of termination of asymmetric bonds in the polycrystalline silicon film by the implanted hydrogen ions and competition with the defects caused by the implanted hydrogen ions. FIG.
Is a 500 Å formed on an insulating substrate using the present invention.
2 is an example showing a sheet resistance value with respect to an implantation amount of boron ions when an impurity boron implanted into a polycrystalline silicon film having a thickness of 3 is subjected to a heat treatment at 300 ° C. for one hour. The heat treatment temperature is preferably 30
It is preferably 0 ° C or higher and 600 ° C or lower, more preferably 300 ° C or higher and 450 ° C or lower, and particularly preferably 300 ° C or higher and 350 ° C or lower. As the polycrystalline silicon film, a film having a crystallization rate of 75% or more, preferably 90% or more is used. In FIG. 18, impurities are B ₂ H ₆ exceeding 0% and 10% or less, preferably 0.01% and 5% or less, by using the ion implantation apparatus without mass separation shown in FIG. 3. , More preferably more than 0.1% and less than 1%, and the balance is 8 ions generated from a mixed gas consisting of helium.
The polycrystalline silicon film was deposited on the polycrystalline silicon film so as to have a B ⁺ ion conversion of 5 × 10 ¹² / cm ² to 1.5 × 10 ¹⁴ / cm ² at an energy of ⁰ keV. Implant through a SiO ₂ film having a thickness of 1200Å. At this time, the maximum concentration of implanted boron in the polycrystalline silicon film is 4.5 × 10 ¹⁷ pieces / cm ³ to 1.3.
× 10 ¹⁹ pieces / cm ³ Further, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 1 × 1.
Although it is above 0 ¹⁸ pieces / cm ³ , helium is electrically inactive and has no electrical effect on the silicon film. Using the ion implantation apparatus without using the above mass separation, hydrogen ions produced from 100% hydrogen gas at an energy of 20 keV and the maximum concentration of the implanted H ⁺ ions in the polycrystalline silicon film were obtained. Is 6 × 10
²⁰ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less, more preferably 1.8 × 10 ¹⁹ pieces / cm ³ or more and 4.2 × 10 ¹⁹
1 × 10 ¹⁴ pieces / cm ² to 1 × 10 ¹⁵ pieces / cm ² , more preferably 3 × 10 so that the number of pieces / cm ³ or less is obtained.
An amount in the range of ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less is implanted. The energy at the time of implantation can be adjusted at any time depending on the thickness and type of the gate insulating film and the type of implanted ions, and is not limited to this embodiment. As shown in FIG. 18, the trace amount of impurities implanted in the polycrystalline silicon film causes 3
It is activated by heat treatment at 00 ° C. As is apparent from FIGS. 17 and 18, the present invention can manufacture a thin film transistor having a p-type LDD structure in addition to the thin film transistor having an n-type LDD structure. According to the present invention, since helium is used as the diluent gas, the plasma is stabilized, and the controllability of the amount of implanted impurities is increased. In addition, helium ions do not etch the oxide film, have less damage to the silicon film, and do not cause unnecessary characteristic changes that occur due to the implantation of a large amount of hydrogen.

(Embodiment 9) FIG. 19 is a sectional view of an embodiment of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, film thickness 5 to be the channel part of the thin film transistor
Polycrystalline silicon film 7 of about 00Å, SiO ₂ film having a film thickness of 1200Å formed as the gate insulating film 8, T
a, a gate electrode 9 made of Al, Cr, a p ⁻ type source / drain region 22 of a thin film transistor, an interlayer insulating film 11 made of SiO ₂ , a source electrode 1 made of Al
2. Drain electrode 13 made of Al or ITO
Indicates. The embodiment of FIG. 19 will be described with reference to the process chart of FIG. First, as shown in FIG. 20A, the glass substrate 5
A SiO ₂ film 6 as an insulating film is deposited thereon with a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, Al, Cr and Ta
A low resistance metal such as is deposited to a thickness of about 6000 Å by a sputtering method or the like, and patterned to form the gate electrode 9. Next, as shown in FIG. 20B, B ₂ H ₆ was reduced to 0% by using the ion implantation apparatus shown in FIG.
More than 10%, preferably more than 0.01% and less than 5%, more preferably more than 0.1% and less than 1%, with the balance being all ions 23 generated from the doping gas consisting of helium. , B ⁺ ion implantation amount is 3 ×
A range of 10 ¹³ pieces / cm ² or more and 1 × 10 ¹⁴ pieces / cm ² or less,
More preferably, the implantation is performed with an energy of about 80 keV so that the range is 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / cm ² or less. Further, the maximum concentration of helium implanted simultaneously at this time in the silicon film is 3 × 10 ¹⁸ /
helium is electrically inactive, even though it is over cm ³ .
It has no effect on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 20 (c), all ions 15 generated with pure hydrogen as a doping gas are converted to 20 k
1 × 10 ¹⁴ pieces / cm ² or more with energy of about eV
10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴
Pieces / cm ² or more at 7 × 10 ¹⁴ pieces / cm ² implant in the range, p ^- -type source-drain regions 22. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, FIG. 20 (d)
As shown in FIG.
Activated by heat treatment at 1 ° C. for 1 hour, a SiO ₂ film is deposited as an interlayer insulating film 11 to a thickness of 5000 Å or more, contact holes are formed in the source / drain regions 10, and Al or ITO is formed in the source / drain regions. The electrode 16 is formed by, for example. According to the present invention, a thin film transistor having a p-type LDD structure can be stably manufactured at a low temperature of about 300 ° C.

FIG. 21 shows a thin film transistor manufactured according to the present invention, in which V _DS is -4V and V _G is -10V.
Drain current 24 and V _DS at −4V, V _G
It is a figure which shows the correlation of the drain current 25 and the implantation amount of boron when it is set to 10V. From FIG. 21, it can be seen that the boron implantation amount is 3 × 10 ¹³ pieces / cm ² or more and 1 × 10.
¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / c
The range of m ² or more and 7 × 10 ¹³ pieces / cm ² or less, that is, the maximum concentration of boron in the polycrystalline silicon film is 3 × 10 ¹⁸ pieces / cm ³
In the range of 1 × 10 ¹⁹ pieces / cm ³ or less, more preferably in the range of 3 × 10 ¹⁸ pieces / cm ³ or more and 7 × 10 ¹⁸ pieces / cm ³ or less, between the gate electrode and the drain region of the thin film transistor. It can be seen that the electric field is relaxed and the leak current of the thin film transistor can be reduced.

(Embodiment 10) FIG. 22 is a sectional view of another embodiment of a thin film transistor manufactured by using the present invention. S that prevents the diffusion of heavy metals from the glass substrate 5
an iO ₂ film 6, a polycrystalline silicon film 7 having a film thickness of about 500Å to be a channel portion of a thin film transistor, a SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film,
The gate electrode 9 made of Ta, Al, or Cr, the p ⁻ type source / drain region 22 of the thin film transistor, and the p ⁺ layer 2 provided immediately below the contact hole of the thin film transistor.
6, an interlayer insulating film 11 made of SiO ₂ , a source electrode 12 made of Al, and a drain electrode 13 made of Al or ITO are shown. Using the process chart of FIG.
The embodiment of FIG. 22 will be described. First, as shown in FIG. 23 (a), a SiO ₂ film 6 is formed as an insulating film on the glass substrate 5.
Deposit with a thickness of 000Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, the SiO ₂ film 12
The gate insulating film 8 is formed by depositing it to a thickness of about 00Å.
Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, as shown in FIG. 23 (b), B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% by using the ion implantation apparatus shown in FIG. % Or less, more preferably more than 0.1% and 1% or less, and all the ions 23 generated from the doping gas with the balance being helium have a B ⁺ ion implantation amount of 3 × 10 ¹³ ions / cm 3. 1 x 10 for ² or more
¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / c
8 to be in the range of 7 × 10 ¹³ pieces / cm ² or less at m ² or more
Implant with energy of about 0 keV. Further, at this time, the maximum concentration of helium implanted at the same time in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. It has no effect. Next, as shown in FIG. 23 (c), using the ion implantation apparatus that does not use the mass spectrometry, 1 × 10 ¹⁴ ions 15 are generated at an energy of about 20 keV with respect to all ions 15 that are produced by using pure hydrogen as a doping gas. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less, and p ⁻ type source The drain region 22 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 23D, Si is used as the interlayer insulating film 11.
Deposit an O ₂ film with a thickness of 5000 Å or more, then
A contact hole is formed in the drain region 10 and B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% by using the ion implantation apparatus without the mass separation described above.
% Of all the ions 27 generated from the doping gas whose balance is H ₂ or helium.
When the implantation amount of B ⁺ ions is 1 × 10 ¹⁵ ions / cm ² or more, the impurity boron concentration peak should be near the center of the polycrystalline silicon film below the contact hole.
Implanting with an energy of 0 keV forms the p ⁺ layer 26. In the formation of the p ⁺ layer, the doping gas used for implantation may be either H ₂ or helium. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Finally, as shown in FIG. 23E, the impurities in the source / drain regions are heat-treated at 300 ° C. for 1 hour to be activated, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al, ITO or the like.
In this embodiment, since a polycrystalline silicon layer having a high concentration of impurities is present at the contact portion between the source / drain region of the thin film transistor and the electrode such as Al or ITO, the electrode and the source / drain region are It is possible to reduce the contact resistance with. Further, no special mask is required to provide the polycrystalline silicon layer in which the above impurities are implanted in high concentration.

(Embodiment 11) FIG. 24 is a sectional view of another embodiment of a thin film transistor manufactured by using the present invention. S that prevents the diffusion of heavy metals from the glass substrate 5
an iO ₂ film 6, a polycrystalline silicon film 7 having a film thickness of about 500Å to be a channel portion of a thin film transistor, a SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film,
The gate electrode 9 is made of Ta, Al or Cr, the p ⁻ type source / drain region 22 of the thin film transistor, the p ⁺ type source / drain region 26 of the thin film transistor, the interlayer insulating film 11 made of SiO ₂ , and Al. A source electrode 12 and a drain electrode 13 formed of Al or ITO are shown. The embodiment of FIG. 24 will be described with reference to the process chart of FIG. First, as shown in FIG. 25A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, a polycrystalline silicon film 7 containing no impurities is formed to 500
Å Deposit with a thickness of about Å and pattern. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, Al, Cr
6000 with low resistance metal such as Ta and Ta by sputtering method
Deposited to a thickness of about Å and patterned to form the gate electrode 9
To form. Next, as shown in FIG. 25B, B ₂ H ₆ was formed by using the ion implantation apparatus shown in FIG.
In a concentration of more than 0% and less than 10%, preferably more than 0.01% and less than 5%, more preferably more than 0.1% and less than 1%, with the balance being helium. The amount of ions 23 implanted with B ⁺ ions is in the range of 3 × 10 ¹³ / cm ² or more and 1 × 10 ¹⁴ / cm ² or less, and more preferably 3 × 10 ¹³ / cm ² or more and 7 × 10.
Implant with energy of about 80 keV so that the range is ¹³ pieces / cm ² or less. Further, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 3 × 10 ^18.
Although the number of particles per cm ³ or more, helium is electrically inactive and does not affect the electrical characteristics of the thin film transistor. Next, as shown in FIG. 25 (c), all ions 15 generated with pure hydrogen as a doping gas are converted to 20 ke
1 × 1 with energy of V about 1 × 10 ¹⁴ pieces / cm ² or more
Implanting in the range of 0 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less,
A p ⁻ type source / drain region 22 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment.
According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 25D, a part of the thin film transistor including the gate electrode is an organic material such as resist or polyimide, or an inorganic material such as Ta, which is selectively removed by etching with the gate electrode and the gate insulating film. Is used as a gate electrode, Al and Cr are used as a mask, and B ₂ H ₆ is more than 0% and less than 10%, preferably 0% by using the ion implantation apparatus without mass separation. at a concentration of 5% or less exceed .01%, the balance being all ions 27 generated from a doping gas composed of H _2, or helium, applying amount B ⁺ ions 1 × 10 ^{1 5} / cm ² or more and To be 8
Implanting with an energy of about 0 keV forms the p ⁺ layer 26 in the source / drain regions of the thin film transistor. In the formation of the p ⁺ layer, the doping gas used for implantation may be either H ₂ or helium. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Next, as shown in FIG. 25E, a SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, and then contact holes are formed in the source / drain regions 10. Finally, the impurities in the source / drain regions are activated by heat treatment at 300 ° C. for 1 hour, and Al or ITO is added to the contact holes in the source / drain regions.
The electrode 16 is formed by, for example. In this embodiment, since a polycrystalline silicon layer having a high concentration of impurities is present at the contact portion between the source / drain region of the thin film transistor and the electrode such as Al or ITO, the electrode and the source / drain region are It is possible to reduce the contact resistance with. In addition, since the implantation energy for forming the p ⁺ layer can be increased, the ion beam current can be increased and the productivity can be improved.

(Embodiment 12) FIG. 26 is a sectional view of another embodiment of a thin film transistor manufactured by using the present invention. S that prevents the diffusion of heavy metals from the glass substrate 5
an iO ₂ film 6, a polycrystalline silicon film 20 having a film thickness of about 1000 Å which becomes a part of a source / drain of a thin film transistor,
A polycrystalline silicon film 7 having a film thickness of about 500 Å to be a channel portion of a thin film transistor, a SiO ₂ film 8 having a film thickness of 1200 Å formed as a gate insulating film, Ta and Al,
A gate electrode 9 made of Cr, a p ⁻ type source / drain region 22 of a thin film transistor, an interlayer insulating film 11 made of SiO ₂ , a source electrode 12 made of Al, Al
Alternatively, the drain electrode 13 formed of ITO is shown.
The embodiment of FIG. 26 will be described with reference to the process chart of FIG.
First, as shown in FIG. 27A, a SiO ₂ film 6 as an insulating film is deposited to a thickness of 2000 Å on a glass substrate 5, and then a polycrystalline silicon film 20 is deposited to a thickness of 1000 Å.
Pattern. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, the polycrystalline silicon film 7 containing no impurities is formed into 5
Deposit with a thickness of about 00Å and pattern. The crystallization rate of the polycrystalline silicon films 7 and 20 is 75% or more,
Preferably, 90% or more of the film is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, as shown in FIG. 27 (b), B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% by using the ion implantation apparatus shown in FIG. % Or less, more preferably 0.1%
Of all the ions 23 generated from the doping gas containing helium with a concentration of more than 1% and less than B ⁺
1 × 1 when the ion implantation amount is 3 × 10 ¹³ ions / cm ² or more
The implantation is performed with an energy of about 80 keV so as to be a range of 0 ¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³ pieces / cm ² or more and 7 × 10 ¹³ pieces / cm ² or less. Further, at this time, the maximum concentration of helium simultaneously implanted in the silicon film is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no effect. Next, as shown in FIG. 27 (c), by using the above-mentioned ion implantation apparatus without mass spectrometry, 1 × 10 ^{14 of} all ions 15 generated with pure hydrogen as a doping gas with an energy of about 20 keV are used. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7
The p ⁻ type source / drain regions 22 are formed by implanting within a range of × 10 ¹⁴ / cm ² or less. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 27 (d),
Impurities in the source / drain region are set to 300 in a nitrogen atmosphere.
Activated by heat treatment at 1 ° C. for 1 hour, a SiO ₂ film is deposited as an interlayer insulating film 11 to a thickness of 5000 Å or more, contact holes are formed in the source / drain regions 10, and Al or ITO is formed in the source / drain regions. The electrode 16 is formed by, for example. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick,
Therefore, the resistance value of the source / drain region can be reduced. Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

Example 13 FIG. 28 is a sectional view of another example of a thin film transistor manufactured by using the present invention. S that prevents the diffusion of heavy metals from the glass substrate 5
an iO ₂ film 6, a polycrystalline silicon film 20 having a film thickness of about 1000 Å which becomes a part of a source / drain of a thin film transistor,
A polycrystalline silicon film 7 having a film thickness of about 500 Å to be a channel portion of a thin film transistor, a SiO ₂ film 8 having a film thickness of 1200 Å formed as a gate insulating film, Ta and Al,
The gate electrode 9 made of Cr, the p ⁻ type source / drain region 22 of the thin film transistor, the p ^{+ of the} thin film transistor.
Type source / drain region 26, interlayer insulating film 11 made of SiO ₂ , source electrode 12 made of Al, A
1 shows the drain electrode 13 made of ITO. 28 will be described with reference to the process chart of FIG. First, as shown in FIG. 29A, a SiO ₂ film 6 is deposited as an insulating film on the glass substrate 5 to a thickness of 2000 Å, and then a polycrystalline silicon film 20 is deposited to a thickness of 1000 Å and then patterned. To do. The SiO ₂ film 6 is for the purpose of preventing heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and the purity of the substrate need not be sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. The polycrystalline silicon films 7 and 20 have a crystallization rate of 75% or more, preferably 90% or more. Next, SiO ₂
The film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, FIG. 29 (b)
As shown in FIG. 3, B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% and less than 5%, and more preferably 0 by using the ion implantation apparatus shown in FIG. ．
All ions 23 generated from a doping gas containing helium in a concentration of more than 1% and less than or equal to 1%,
1 × when the implantation amount of B ⁺ ions is 3 × 10 ¹³ / cm ² or more
10 ¹⁴ pieces / cm ² or less, more preferably 3 × 10 ¹³
The energy is set to about 80 keV so that the number of particles per cm ² is 7 × 10 ¹³ per cm ² or less. In addition, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 3 × 10 ¹⁸ pieces / cm ³ or more, but helium is electrically inactive and has no influence on the electrical characteristics of the thin film transistor. Does not bring. Next, as shown in FIG. 29 (c), using the ion implantation apparatus that does not use the mass spectrometry, 1 × 10 ¹⁴ ions 15 are generated at an energy of about 20 keV, with all the ions 15 generated using pure hydrogen as a doping gas. / Cm ² or more and 1 × 10 ¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / cm ² or more and 7 × 10 ¹⁴ pieces / cm ² or less, p ⁻ type source The drain region 22 is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 29D, Si is used as the interlayer insulating film 11.
Deposit an O ₂ film with a thickness of 5000 Å or more, then
A contact hole is formed in the drain region 10 and B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% by using the ion implantation apparatus without the mass separation described above.
% Of all the ions 27 generated from the doping gas whose balance is H ₂ or helium.
The implantation amount of B ⁺ ions is 1 × 10 ¹⁵ / cm ² or more, and the maximum concentration of the impurity boron is 30 k so that it is near the center of the polycrystalline silicon film below the contact hole.
Drive with eV energy. In the formation of the p ⁺ layer, the doping gas used for implantation may be either H ₂ or helium. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Finally Figure 2
As shown in FIG. 9E, the impurities in the source / drain regions are heat-treated at 300 ° C. for 1 hour to be activated, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al, ITO or the like. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor has a large film thickness, so that the resistance value of the source / drain region can be further reduced. Also p ⁺ type source
It has the advantage that no special mask is required to form the drain region.

(Embodiment 14) FIG. 30 is a sectional view of another embodiment of a thin film transistor manufactured by using the present invention. S that prevents the diffusion of heavy metals from the glass substrate 5
an iO ₂ film 6, a polycrystalline silicon film 20 having a film thickness of about 1000 Å which becomes a part of a source / drain of a thin film transistor,
A polycrystalline silicon film 7 having a film thickness of about 500 Å to be a channel portion of a thin film transistor, a SiO ₂ film 8 having a film thickness of 1200 Å formed as a gate insulating film, Ta and Al,
The gate electrode 9 made of Cr, the p ⁻ type source / drain region 22 of the thin film transistor, the p ^{+ of the} thin film transistor.
Type source / drain region 26, interlayer insulating film 11 made of SiO ₂ , source electrode 12 made of Al, A
1 shows the drain electrode 13 made of ITO. The embodiment of FIG. 30 will be described with reference to the process chart of FIG. First, as shown in FIG. 31A, a SiO ₂ film 6 is deposited as an insulating film on the glass substrate 5 to a thickness of 2000 Å, and then a polycrystalline silicon film 20 is deposited to a thickness of 1000 Å and then patterned. To do. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and is not necessary if the substrate has a sufficiently high purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned.
The crystallization rate of the polycrystalline silicon films 7 and 20 is 75%.
Above, preferably 90% or more of the film is used. Then SiO
_Two films are deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low-resistance metal such as Al, Cr, or Ta is deposited to a thickness of about 6000 Å by sputtering or the like, and patterned to form the gate electrode 9. Next, FIG.
As shown in (b), B ₂ H ₆ is more than 0% and less than 10%, preferably more than 0.01% and less than 5% by using the ion implantation apparatus shown in FIG. Preferably, all the ions 23 generated from the doping gas containing 0.1% or more and more than 0.1% and the balance being helium are used when the implantation amount of B ⁺ ions is 3 × 10 ¹³ ions / cm ² or more. × 10 ¹⁴ pieces / cm ² or less, more preferably 3
× 10 ¹³ / cm ² or more at 7 × 10 ¹³ / cm ² are implanted at 80keV about energy so that the range. Further, the maximum concentration of helium simultaneously implanted in the silicon film at this time is 3 × 10 ¹⁸ pieces / cm ³ or more,
Helium is electrically inert and has no effect. Next, as shown in FIG. 31 (c), all ions 15 generated with pure hydrogen as a doping gas are converted to 20 keV
1 × 10 with energy of about 1 × 10 ¹⁴ pieces / cm ² or more
¹⁵ pieces / cm ² or less, more preferably 3 × 10 ¹⁴ pieces / c
Implanted in the range of 7 × 10 ¹⁴ pieces / cm ² or less with m ² or more, p ⁻
A source / drain region 22 of the mold is formed. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 31 (d), a part of the thin film transistor including the gate electrode is an organic material such as resist or polyimide, or an inorganic material such as Ta that is selectively removed by etching with the gate electrode and the gate insulating film. Is used for the gate electrode, Al
A mask by using a and Cr, by using an ion implantation apparatus that does not use the mass separation of the, B ₂ and H ₆ exceed 0% 10
% Or less, preferably more than 0.01% and 5% or less, and the total amount of all ions 27 generated from the doping gas whose balance is H ₂ or helium is 1 × 10 ¹⁵ B ⁺ ions. 80k so that it is more than / cm ²
The p ⁺ layer 26 is formed in the source / drain regions of the thin film transistor by implanting with an energy of about eV.
In the formation of the p ⁺ layer, the doping gas used for implantation may be either H ₂ or helium. Further, it is desirable that the concentration of the doping gas is as high as possible for short-time injection. Next, as shown in FIG. 31E, a SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, and then contact holes are formed in the source / drain regions 10. Finally, the impurities in the source / drain regions are activated by heat treatment at 300 ° C. for 1 hour in a nitrogen atmosphere, and the electrodes 16 are formed in the contact holes in the source / drain regions with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor has a large film thickness, so that the resistance value of the source / drain region can be further reduced. Further, since the implantation energy can be increased when the p ⁺ type source / drain regions are formed, there is an advantage that the ion beam current can be increased and the productivity is improved.

Example 15 FIG. 32 shows a liquid crystal display device in which a thin film transistor having an n-type or p-type LDD structure formed by using the present invention is used as a pixel driving thin film transistor of a liquid crystal display device. FIG.
Reference numeral 28 is an insulating substrate on which thin film transistors are formed, 29 is a counter substrate, and 30 is a liquid crystal. In FIG. 32, as the thin film transistor for a pixel, a thin film transistor having an LDD structure described in this specification or a similar thin film transistor which can be easily analogized is used. FIG. 33 shows an equivalent circuit diagram. The auxiliary capacitance in FIG. 33 can be formed by a method of providing a capacitance line, a method of providing a capacitance between the gate line one stage before driving, or the like.

[0022]

The present invention has the following effects.

(1). It is possible to activate impurity ions in an amount of 1 × 10 ¹⁴ / cm ² or less at a low temperature of about 300 ° C. to 450 ° C. by using an ion implantation apparatus that does not use mass spectrometry.

(2). It becomes possible to manufacture a thin film transistor having an LDD structure at a low temperature of about 300 ° C. to 450 ° C., and it is possible to reduce the leak current of the thin film transistor.

(3). By reducing the leak current of the thin film transistor, the storage capacity of the liquid crystal display device can be reduced, and the aperture ratio of the liquid crystal display device can be improved.

(4). An inexpensive glass substrate can be used.

(5). It is possible to use a metal having a low resistance for the gate wiring, and the delay of the gate signal can be reduced. Therefore, the image quality is improved.

(6). n ^- or p ^- by using a diluted gas of impurities in helium formation region, n ^-
Alternatively, it becomes easy to control the amount of hydrogen required for forming the p ⁻ region.

(7). Since helium ions are inactive, even if the thickness of the gate electrode is reduced, the TFT characteristics are not affected and the element can be flattened.

[Brief description of drawings]

FIG. 1 is a diagram showing a sheet resistance value of a polycrystalline silicon film in which phosphorus is implanted with respect to an amount of H ⁺ ions implanted.

FIG. 2 is a diagram showing a sheet resistance value with respect to an implantation amount of P ⁺ ions.

FIG. 3 is a cross-sectional view showing an example of an ion implantation apparatus that does not use mass spectrometry.

FIG. 4 is a cross-sectional view showing an example of a thin film transistor manufactured by using the present invention.

FIG. 5 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 6 is a diagram showing a correlation of a drain current with respect to a P ⁺ implantation amount.

FIG. 7 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 8 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 9 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 10 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 11 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 12 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 13 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 14 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 15 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 16 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 17 is a diagram showing a sheet resistance value of a polycrystalline silicon film in which boron is implanted with respect to the amount of H ⁺ ion implantation.

FIG. 18 is a diagram showing a sheet resistance value with respect to an implantation amount of B ⁺ ions.

FIG. 19 is a cross-sectional view showing an example of a thin film transistor manufactured by using the present invention.

FIG. 20 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 21 is a diagram showing the correlation of drain current with respect to the amount of implantation of B ⁺ .

FIG. 22 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 23 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 24 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 25 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 26 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 27 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 28 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 29 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 30 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 31 is a process drawing showing another example of the thin film transistor manufactured by using the present invention.

FIG. 32 is a cross-sectional view showing an example of a liquid crystal display device manufactured using the thin film transistor of the invention.

FIG. 33 is an equivalent circuit diagram showing an example of a liquid crystal display device manufactured using the thin film transistor of the invention.

[Explanation of symbols]

1 Plasma Source 2 Impurity Ion 3 Extraction Electrode 4 Acceleration Electrode 5 Substrate 6 SiO ₂ Film 7 Polycrystalline Silicon Film 8 Gate Insulation Film 9 Gate Electrode 10 n ^- Type Source / Drain Region 11 Interlayer Insulation Film 12 Source Electrode 13 Drain Electrode 14 All ions including PH ₃ generated from the doping gas with the balance being helium 15 All ions generated from pure hydrogen as the doping gas 16 Electrodes 17 Drain current when V _{DS of the} thin film transistor is 4V and V _G is 10V 18 The thin film transistor V _DS is 4V and V _G is -10V.
Drain current 19 n ⁺ layer 20 PH ₃ and the rest is all ions generated from the doping gas consisting of H ₂ or helium 21 Polycrystalline silicon with a film thickness of about 1000 Å which becomes a part of the source / drain of the thin film transistor All ions generated from a doping gas consisting of the film 22 p ^- layer 23 B ₂ H ₆ with the balance being helium 24 V _{DS of the} thin film transistor −4 V and V _G −10
Drain current when V 25 V _{DS of} thin film transistor is -4V and V _G is 10V
Drain current 26 p ⁺ layer 27 B ₂ H ₆ and all the ions generated from the doping gas composed of H ₂ or helium at the balance 28 Insulating substrate on which thin film transistors are formed 29 Counter substrate 30 Liquid crystal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/265 H01L 21/265 H

Claims (33)

[Claims] 1. A polycrystalline silicon film formed on an insulating substrate and an insulating film deposited on the polycrystalline silicon film, using an ion implantation apparatus that does not use mass separation.
All the ions generated from the mixed gas containing ₃ to 0% and more than 0% and the rest being helium are implanted into the polycrystalline silicon film through the insulating film, and then the mass separation is not used. Implanting hydrogen ions generated from pure hydrogen gas into the polycrystalline silicon film through the insulating film using an ion implantation device, and then heating the insulating substrate to 300 ° C. or higher and 600 ° C. or lower. And a method for activating impurities. 2. The maximum impurity concentration of phosphorus in the polycrystalline silicon film, which is implanted by using the ion implantation apparatus without mass separation, is 1.1 × 10 ¹⁷ / cm ³ or more.
The maximum concentration of helium implanted at the same time in the polycrystalline silicon film is 1 × 10 ¹⁹ pieces / cm ³ or less.
10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of the hydrogen to be implanted next in the polycrystalline silicon film is 6 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less. The method for activating impurities according to claim 1, wherein the method for activating impurities is present. 3. In a thin film transistor formed on an insulating substrate, a polycrystalline silicon film which becomes a channel, a gate insulating film formed on the polycrystalline silicon film, and a gate electrode formed on the gate insulating film. The source / drain regions are formed in a self-aligned manner with respect to the gate electrode, and the maximum concentration of phosphorus contained in the source / drain regions is 3 × 10 ¹⁸ pieces / cm ³ or more and 1 ×. The maximum concentration of helium contained in the source / drain region is 3 × 10 ¹⁸ pieces / cm ^{3 in} the range of 10 ¹⁹ pieces / cm ³ or less.
Within the above range, and then the maximum concentration of hydrogen contained in the source / drain regions is 6 × 10 ¹⁸ / cm ³ or more, 1
A thin film transistor characterized by being in the range of × 10 ²⁰ pieces / cm ³ or less. 4. In a thin film transistor formed on an insulating substrate, (1) a step of forming a polycrystalline silicon film on the insulating substrate, (2) a step of forming an insulating film on the polycrystalline silicon film, 3) a step of forming a gate electrode on the insulating film, and (4) using an ion implanter that does not use mass separation, containing PH ₃ in an amount of more than 0% and 10% or less, and the balance being helium. All the generated ions are implanted into the polycrystalline silicon film through the insulating film using the gate electrode as a mask, and then generated from pure hydrogen gas by using the ion implantation apparatus that does not use the mass separation. Implanting hydrogen ions into the polycrystalline silicon film through the insulating film to form the source / drain regions of the thin film transistor in a self-aligned manner,
(5) A method of manufacturing a thin film transistor, including the step of heating the insulating substrate to 300 ° C. or higher and 600 ° C. or lower to activate impurities. 5. The maximum concentration of impurities in the source / drain regions of phosphorus implanted by using an ion implanter without mass separation is 3 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ¹⁹ pieces / cm ³ or less. And the maximum concentration of helium that is simultaneously implanted in the source / drain region is 3 × 10 ^18.
The number of hydrogen atoms is not less than 6 / cm ³ and the maximum concentration of hydrogen to be implanted next in the source / drain regions is 6 × 10 ¹⁸ pieces / cm 3.
Method of manufacturing a thin film transistor according to claim 4, characterized in that ³ or more in the range of 1 × 10 ^{2 0} / cm ³ or less. 6. In a thin film transistor formed on an insulating substrate, a polycrystalline silicon film which becomes a channel, a gate insulating film formed on the polycrystalline silicon film, and a gate electrode formed on the gate insulating film. A first source / drain region formed in self-alignment with the gate electrode, the first source / drain region and a second source / drain region in contact with the source / drain electrode, If the maximum concentration of phosphorus contained in the first source / drain region is 3 × 10 ¹⁸ pieces / cm ³ or more, 1 ×
10 ¹⁹ / cm ³ is in the range, the maximum concentration of helium is in the 3 × 10 ¹⁸ atoms / cm ³ or more ranges, 1 × 10 at the maximum concentration of hydrogen 6 × 10 ¹⁸ atoms / cm ³ or more A thin film transistor containing ²⁰ or less / cm ³ or less, and the maximum concentration of phosphorus contained in the second source / drain region is 1 × 10 ²⁰ or less / cm ³ or more. 7. In a thin film transistor formed on an insulating substrate, (1) a step of forming a polycrystalline silicon film on the insulating substrate, (2) a step of forming an insulating film on the polycrystalline silicon film, 3) a step of forming a gate electrode on the insulating film, and (4) using an ion implanter that does not use mass separation, containing PH ₃ in an amount of more than 0% and 10% or less, and the balance being helium. All the generated ions are implanted into the polycrystalline silicon film through the insulating film using the gate electrode as a mask, and then generated from pure hydrogen gas by using the ion implantation apparatus that does not use the mass separation. Implanting hydrogen ions into the polycrystalline silicon film through the insulating film to form the first source / drain regions of the thin film transistor in a self-aligned manner, (5) The gate Masking a portion of the thin film transistors including electrodes, using an ion implantation apparatus that does not use the mass separation of said, a PH ₃ includes at 10% or less than 0%
A step of implanting all ions generated from a mixed gas whose balance is hydrogen or helium into a part of the first source / drain region to form a second source / drain region, (6) the insulating substrate 60 above 300 ° C
A method of manufacturing a thin film transistor, comprising the step of activating the impurities by heating to 0 ° C. or lower. 8. The step (4) according to claim 7, wherein the maximum concentration of impurities in the first source / drain region of phosphorus implanted using an ion implantation apparatus without mass separation is 3 × 10. 1 × 10 ¹⁹ pieces / cm ^{3 for 18} pieces / cm ³ or more
Within the following range, the maximum concentration of helium that is simultaneously implanted in the first source / drain region is 3 × 10 ^18.
The maximum concentration of hydrogen to be implanted next in the first source / drain region is 6 × / cm ³ or more.
The method of manufacturing a thin film transistor according to claim 7, wherein the number is in the range of 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less. 9. The step (5) according to claim 7, wherein the maximum concentration of impurities in the second source / drain region of phosphorus implanted using an ion implantation apparatus without mass separation is 1 × 10. ^The method for manufacturing a thin film transistor according to claim 7, wherein the number is ²⁰ / cm ³ or more. 10. In a thin film transistor formed on an insulating substrate, an island-shaped first polycrystalline silicon film to be a source / drain region and a part or all of the first polycrystalline silicon film are formed. A part of the source / drain region of the thin film transistor formed so as to cover and a second polycrystalline silicon film to be a channel, the gate insulating film formed on the first and second polycrystalline silicon films,
A gate electrode formed on the second polycrystalline silicon film and the gate insulating film between the first polycrystalline silicon film, and source / drain formed in self-alignment with the gate electrode And the maximum concentration of phosphorus contained in the source / drain region is 3 × 10 ¹⁸ pieces / cm ³
The above is in the range of 1 × 10 ¹⁹ pieces / cm ³ or less, and the maximum concentration of helium is in the range of 3 × 10 ¹⁸ pieces / cm ³ or more,
Maximum concentration of hydrogen is 6 × 10 ¹⁸ pieces / cm ³ or more, 1 × 10 ²⁰
A thin film transistor characterized in that it is contained in the range of not more than 1 / cm ³ . 11. In a thin film transistor formed on an insulating substrate, (1) a step of forming a first polycrystalline silicon film to be source / drain regions in an island shape on the insulating substrate, (2) the first Forming part of the source / drain region of the thin film transistor and a second polycrystalline silicon film to be a channel so as to cover a part or all of the polycrystalline silicon film of (3) The above first and second Forming an insulating film on the polycrystalline silicon film, (4) forming a gate electrode on the insulating film and the second polycrystalline silicon film between the first polycrystalline silicon films,
(5) PH using an ion implanter without mass separation
The first and second polycrystalline silicon films containing ₃ in an amount of more than 0% and 10% or less, with the balance being helium, and all ions generated through the insulating film through the gate electrode as a mask. And then implanting hydrogen ions generated from pure hydrogen gas through the insulating film into the first and second polycrystalline silicon films by using the ion implantation apparatus without using the mass separation. A step of forming source / drain regions of the thin film transistor in a self-aligning manner, and (6) heating the insulating substrate at 300 ° C. or higher to 600 ° C. or lower to activate the impurities. Method of manufacturing thin film transistor. 12. The maximum concentration of impurities in the source / drain regions of phosphorus implanted by using an ion implanter without mass separation is 1 × 10 ^{19 when the} concentration is 3 × 10 ¹⁸ / cm ³ or more.
Located pieces / cm ³ or less of the range, the maximum concentration of the source and drain regions of helium implanted simultaneously, 3 × 10
¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the source / drain regions is 6 × 10 ¹⁸ pieces / cm 3.
Method of manufacturing a thin film transistor according to claim 11, characterized in that ³ or more in the range of 1 × 10 ^{2 0} / cm ³ or less. 13. A thin film transistor formed on an insulating substrate, comprising: a first polycrystalline silicon film formed in an island shape to be a source / drain region; and a part or all of the first polycrystalline silicon film. A part of the source / drain region of the thin film transistor formed so as to cover and a second polycrystalline silicon film to be a channel, the gate insulating film formed on the first and second polycrystalline silicon films,
A gate electrode formed on the second polycrystalline silicon film and the gate insulating film between the first polycrystalline silicon film, and a first electrode formed in self-alignment with the gate electrode. Source / drain regions, the first source /
The second source / drain region is in contact with the drain region and the source / drain electrode, and the maximum concentration of phosphorus contained in the first source / drain region is 3 × 10 ^18.
It is in the range of 1 × 10 ¹⁹ pieces / cm ³ or less at the number of pieces / cm ³ or more, the maximum concentration of helium is in the range of 3 × 10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen is 6 × 10 ¹⁸ pieces. 1 × above / cm ³
10. A thin film transistor, characterized in that it is contained in the range of 10 ²⁰ pieces / cm ³ or less and the maximum concentration of phosphorus contained in the second source / drain region is in the range of 1 × 10 ²⁰ pieces / cm ³ or more. 14. In a thin film transistor formed on an insulating substrate, (1) a step of forming a first polycrystalline silicon film to be source / drain regions in an island shape on the insulating substrate, (2) the first Forming part of the source / drain region of the thin film transistor and a second polycrystalline silicon film to be a channel so as to cover a part or all of the polycrystalline silicon film of (3) The above first and second Forming an insulating film on the polycrystalline silicon film, (4) forming a gate electrode on the insulating film and the second polycrystalline silicon film between the first polycrystalline silicon films,
(5) PH using an ion implanter without mass separation
The first and second polycrystalline silicon films containing ₃ in an amount of more than 0% and 10% or less, with the balance being helium, and all ions generated through the insulating film through the gate electrode as a mask. And then implanting hydrogen ions generated from pure hydrogen gas through the insulating film into the first and second polycrystalline silicon films by using the ion implantation apparatus without using the mass separation. A step of forming first source / drain regions of the thin film transistor in a self-aligning manner, (6) using a part of the thin film transistor including the gate electrode as a mask, and using the ion implantation apparatus without mass separation, ₃ over 0% and 1
Forming a second source / drain region by implanting into the part of the first source / drain region all ions generated from a mixed gas containing 0% or less and the balance being hydrogen or helium; 7) Replace the insulating substrate
A method of manufacturing a thin film transistor, comprising a step of activating the impurities by heating at a temperature of 00 ° C. or higher and 600 ° C. or lower. 15. In the step (5) according to claim 14, the maximum impurity concentration of phosphorus in the first source / drain region is 3 × 10 5 which is implanted by using an ion implantation apparatus without mass separation. 1 × 10 ¹⁹ pieces / c at ¹⁸ pieces / cm ³ or more
The maximum concentration of helium that is simultaneously implanted within the range of m ³ or less is 3 × 10 3.
¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the first source / drain region is 6 × 10.
15. The method of manufacturing a thin film transistor according to claim 14, wherein the number is in the range of ¹⁸ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. 16. The step (6) according to claim 14, wherein the maximum concentration of impurities in the second source / drain region of phosphorus implanted using an ion implantation device without mass separation is 1 or less. 15. The method for producing a thin film transistor according to claim 14, wherein the number is × 10 ²⁰ pieces / cm ³ or more. 17. A polycrystalline silicon film formed on an insulating substrate and an insulating film deposited on the polycrystalline silicon film, using an ion implantation apparatus that does not use mass separation.
All ions generated from a mixed gas containing ₂ H ₆ in an amount of more than 0% and 10% or less and the balance being helium are implanted into the polycrystalline silicon film through the insulating film, and then the mass separation is performed. Using an ion implantation device not used, hydrogen ions generated from pure hydrogen gas are implanted into the polycrystalline silicon film through the insulating film, and then the insulating substrate is heated to 300 ° C. or higher and 600 ° C. or lower. A method for activating impurities, comprising: 18. The maximum concentration of impurities in the polycrystalline silicon film of boron implanted using the ion implantation system without mass separation is 4.5 × 10 ¹⁷ pieces / cm ³ or more and 1.3 ×. The maximum concentration of helium that is simultaneously implanted in the polycrystalline silicon film is 10 ¹⁹ pieces / cm ³ or less, and the maximum concentration of helium that is simultaneously implanted is 1 × 10 ¹⁸ pieces / cm ³ or more. Maximum concentration in crystalline silicon film is 6
× 10 ¹⁸ / cm ³ or more at 1 × 10 ²⁰ / cm ³ activation method of the impurity of claim 17, characterized in that in the following range. 19. In a thin film transistor formed on an insulating substrate, a polycrystalline silicon film serving as a channel, a gate insulating film formed on the polycrystalline silicon film, and a gate electrode formed on the gate insulating film. The source / drain regions are formed in self-alignment with the gate electrode, and the maximum concentration of boron contained in the source / drain regions is 3 × 10 ¹⁸ / cm ³ or more and 1 × 1
0 ¹⁹ pieces / cm ³ or less, and the maximum concentration of helium contained in the source / drain region is 3 × 10 ¹⁸ pieces / cm ³ or more. A thin film transistor characterized in that the maximum concentration of hydrogen contained is in the range of 6 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less. 20. In a thin film transistor formed on an insulating substrate, (1) a step of forming a polycrystalline silicon film on the insulating substrate, (2) a step of forming an insulating film on the polycrystalline silicon film, 3) A step of forming a gate electrode on the insulating film, and (4) a mixture containing B ₂ H ₆ in an amount of more than 0% and 10% or less and a balance of helium by using an ion implantation apparatus without mass separation. All ions generated from the gas are implanted into the polycrystalline silicon film through the insulating film using the gate electrode as a mask, and then from the pure hydrogen gas by using the ion implantation device without mass separation. Implanting generated hydrogen ions into the polycrystalline silicon film through the insulating film to form source / drain regions of the thin film transistor in a self-aligned manner;
(5) A method of manufacturing a thin film transistor, including the step of heating the insulating substrate to 300 ° C. or higher and 600 ° C. or lower to activate impurities. 21. The maximum concentration of impurities in the source / drain regions of boron implanted by using an ion implanter without mass separation is 3 × 10 ¹⁸ / cm ³ or more and 1 × 1.
0 ¹⁹ / cm ³ is in the range, the maximum concentration of the source and drain regions of helium implanted simultaneously, 3 ×
10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the source / drain regions is 6 × 10 ^18.
21. The method for producing a thin film transistor according to claim ^{20, wherein the} number is in the range of 1/10 ³ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less. 22. In a thin film transistor formed on an insulating substrate, a polycrystalline silicon film to be a channel, a gate insulating film formed on the polycrystalline silicon film, and a gate electrode formed on the gate insulating film. , A first source formed in self-alignment with the gate electrode
A drain region and a second source / drain region in contact with the first source / drain region and the source / drain electrode, and the maximum concentration of boron contained in the first source / drain region is 3 × It is in the range of 1 × 10 ¹⁹ pieces / cm ³ or less at 10 ¹⁸ pieces / cm ³ or more, the maximum concentration of helium is 3 × 10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen is 6 × 10 5. 1 × 10 ²⁰ pieces / c at ¹⁸ pieces / cm ³ or more
A thin film transistor, which comprises m ³ or less and has a maximum concentration of boron contained in the second source / drain region of 1 × 10 ²⁰ / cm ³ or more. 23. In a thin film transistor formed on an insulating substrate, (1) a step of forming a polycrystalline silicon film on the insulating substrate, (2) a step of forming an insulating film on the polycrystalline silicon film, 3) a step of forming a gate electrode on the insulating film, and (4) a mixture containing B ₂ H ₆ in an amount of more than 0% and 10% or less and a balance of helium by using an ion implantation apparatus without mass separation. All the ions generated from the gas are implanted into the polycrystalline silicon film through the insulating film using the gate electrode as a mask, and then from the pure hydrogen gas by using the ion implantation apparatus that does not use the mass separation. Implanting the generated hydrogen ions into the polycrystalline silicon film through the insulating film to form the first source / drain regions of the thin film transistor in a self-aligned manner, (5) above Masking a portion of the thin film transistor including over gate electrode using an ion implantation apparatus that does not use the mass separation of said, a B ₂ H ₆ comprises at 10% or less than 0%
A step of implanting all ions generated from a mixed gas whose balance is hydrogen or helium into a part of the first source / drain region to form a second source / drain region, (6) the insulating substrate 60 above 300 ° C
A method of manufacturing a thin film transistor, comprising the step of activating the impurities by heating to 0 ° C. or lower. 24. In the step (4) according to claim 23, the maximum impurity concentration of the first source / drain region of boron implanted using an ion implantation apparatus without mass separation is 3 × 10. 1 × 10 ¹⁹ with ¹⁸ pieces / cm ³ or more
The maximum concentration of helium implanted at the same time in the first source / drain region is ³ / cm ³ or less.
× 10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the first source / drain region is 6
× 10 ¹⁸ / cm ³ or more at 1 × 10 ²⁰ / cm ³ method of manufacturing a thin film transistor according to claim 23, characterized in that in the following range. 25. In the step (5) according to claim 23, the maximum impurity concentration of the second source / drain region of boron implanted using an ion implantation apparatus without mass separation is 1 × 10. ^The method of manufacturing a thin film transistor according to claim 23, wherein the number is ²⁰ / cm ³ or more. 26. In a thin film transistor formed on an insulating substrate, an island-shaped first polycrystalline silicon film to be a source / drain region, and a part or all of the first polycrystalline silicon film. A part of the source / drain region of the thin film transistor formed so as to cover and a second polycrystalline silicon film to be a channel, the gate insulating film formed on the first and second polycrystalline silicon films,
A gate electrode formed on the second polycrystalline silicon film and the gate insulating film between the first polycrystalline silicon film, and source / drain formed in self-alignment with the gate electrode And the maximum concentration of boron contained in the source / drain region is 3 × 10 ¹⁸ /
Located 1 × 10 ¹⁹ / cm ³ or less in the range in cm ³ or more, the maximum concentration of helium, 3 × a ^10-18 / cm ³ or more ranges, the maximum concentration of hydrogen 6 × 10 ¹⁸ / cm 1 x 1 for ³ or more
A thin film transistor characterized in that it is contained in a range of 0 ²⁰ pieces / cm ³ or less. 27. In a thin film transistor formed on an insulating substrate, (1) a step of forming a first polycrystalline silicon film to be source / drain regions in an island shape on the insulating substrate, (2) the first Forming part of the source / drain region of the thin film transistor and a second polycrystalline silicon film to be a channel so as to cover a part or all of the polycrystalline silicon film of (3) The above first and second Forming an insulating film on the polycrystalline silicon film, (4) forming a gate electrode on the insulating film and the second polycrystalline silicon film between the first polycrystalline silicon films,
(5) B ₂ using an ion implanter without mass separation
The first and second polycrystalline silicon containing H ₆ in an amount of more than 0% and 10% or less and the rest of which is generated from a mixed gas of helium through the insulating film using the gate electrode as a mask. Then, the hydrogen ions generated from pure hydrogen gas are injected into the film and then into the first and second polycrystalline silicon films through the insulating film by using the ion implantation apparatus without using the mass separation. A step of forming source / drain regions of the thin film transistor by implantation self-alignment, and (6) heating the insulating substrate at 300 ° C. or higher to 600 ° C. or lower to activate the impurities. Method of manufacturing thin film transistor. 28. 1 × 1 when the maximum concentration of impurities in the source / drain regions of boron implanted by using an ion implanter without mass separation is 3 × 10 ¹⁸ pieces / cm ³ or more.
0 ¹⁹ / cm ³ is in the range, the maximum concentration of the source and drain regions of helium implanted simultaneously, 3 ×
10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the source / drain regions is 6 × 10 ^18.
28. The method of manufacturing a thin film transistor according to claim 27, wherein the number is in the range of 1 / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less. 29. In a thin film transistor formed on an insulating substrate, an island-shaped first polycrystalline silicon film to be a source / drain region, and a part or all of the first polycrystalline silicon film. A part of the source / drain region of the thin film transistor formed so as to cover and a second polycrystalline silicon film to be a channel, the gate insulating film formed on the first and second polycrystalline silicon films,
A gate electrode formed on the second polycrystalline silicon film and the gate insulating film between the first polycrystalline silicon film, and a first electrode formed in self-alignment with the gate electrode. Source / drain regions, the first source /
The second source / drain region is in contact with the drain region and the source / drain electrode, and the maximum concentration of boron contained in the first source / drain region is 3 × 1.
0 ¹⁸ pieces / cm ³ or more and 1 × 10 ¹⁹ pieces / cm ³ or less, the maximum concentration of helium is 3 × 10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen is 6 × 10 The maximum concentration of boron contained in the second source / drain region is 1 in the range of ¹⁸ pieces / cm ³ or more and 1 × 10 ²⁰ pieces / cm ³ or less.
A thin film transistor characterized by being in the range of × 10 ²⁰ pieces / cm ³ or more. 30. In a thin film transistor formed on an insulating substrate, (1) a step of forming a first polycrystalline silicon film to be source / drain regions in an island shape on the insulating substrate, (2) the first Forming part of the source / drain region of the thin film transistor and a second polycrystalline silicon film to be a channel so as to cover a part or all of the polycrystalline silicon film of (3) The above first and second Forming an insulating film on the polycrystalline silicon film, (4) forming a gate electrode on the insulating film and the second polycrystalline silicon film between the first polycrystalline silicon films,
(5) B ₂ using an ion implanter without mass separation
The first and second polycrystalline silicon containing H ₆ in an amount of more than 0% and 10% or less and the rest of which is generated from a mixed gas of helium through the insulating film using the gate electrode as a mask. Then, the hydrogen ions generated from pure hydrogen gas are injected into the film and then into the first and second polycrystalline silicon films through the insulating film by using the ion implantation apparatus without using the mass separation. Forming a first source / drain region of the thin film transistor by implanting self-alignment; All ions generated from a mixed gas containing B ₂ H ₆ in an amount of more than 0% and 10% or less and the balance of hydrogen or helium are included in the first source / drain region. Drive into a part of the area, the second source
A method of manufacturing a thin film transistor, comprising: a step of forming a drain region; and (7) a step of heating the insulating substrate at 300 ° C. or higher to 600 ° C. or lower to activate the impurities. 31. In the step (5) according to claim 30, the maximum impurity concentration of the first source / drain region of boron implanted using an ion implantation apparatus without mass separation is 3 × 10. 1 × 10 ¹⁹ with ¹⁸ pieces / cm ³ or more
The maximum concentration of helium implanted at the same time in the first source / drain region is ³ / cm ³ or less.
× 10 ¹⁸ pieces / cm ³ or more, and the maximum concentration of hydrogen to be implanted next in the first source / drain region is 6
× 10 ¹⁸ / cm ³ or more at 1 × 10 ²⁰ / cm ³ method of manufacturing a thin film transistor according to claim 30, characterized in that in the following range. 32. In the step (6) according to claim 30, the maximum impurity concentration of the second source / drain region of boron implanted using an ion implantation apparatus without mass separation is 1 ×. The method of manufacturing a thin film transistor according to claim 30, wherein the number is 10 ²⁰ pieces / cm ³ or more. 33. A substrate on which a thin film transistor is formed, a substrate on which a transparent electrode is formed, and a liquid crystal sandwiched between the substrate on which the thin film transistor is formed and the substrate on which the transparent electrode is formed. In a liquid crystal display device in which the liquid crystal is driven to display the liquid crystal, the thin film transistor is used in any one of claims 3 or 6, claim 10, claim 13 or claim 19, claim 22 or claim. Two
A thin film transistor according to claim 6 or claim 29.