JPH07322292A - Discriminating circuit for reproduction mode of vtr - Google Patents

Discriminating circuit for reproduction mode of vtr

Info

Publication number
JPH07322292A
JPH07322292A JP6111123A JP11112394A JPH07322292A JP H07322292 A JPH07322292 A JP H07322292A JP 6111123 A JP6111123 A JP 6111123A JP 11112394 A JP11112394 A JP 11112394A JP H07322292 A JPH07322292 A JP H07322292A
Authority
JP
Japan
Prior art keywords
signal
frequency
circuit
output
vco
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6111123A
Other languages
Japanese (ja)
Other versions
JP3157382B2 (en
Inventor
Hideo Satomi
英雄 里見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11112394A priority Critical patent/JP3157382B2/en
Publication of JPH07322292A publication Critical patent/JPH07322292A/en
Application granted granted Critical
Publication of JP3157382B2 publication Critical patent/JP3157382B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To select the mode in response to a reproduction signal of a VTR by smoothing an output signal of a frequency identification circuit identifying an oscillated frequency of a frequency conversion VCO of a chroma signal so as to discriminate the reproduction mode depending on the smoothed output. CONSTITUTION:When a PAL signal is reproduced, a chroma signal is shifted by 90 deg. at an interval of one field. The phase of an NTSC signal is shifted at all times and the phase shift direction is inverted by each field. Thus, m an error component is generated from an APC detection circuit 4. A detection output is fed to a VCO 8 via an LPF 13 and an adder circuit 14 and its oscillated frequency is changed. When the frequency change changes up to a prescribed range 1284+ or -3 or over, a signal from an error output circuit 11 is rectified by a rectifier smoothing circuit 16 and a stable DC voltage is obtained. A microcomputer 15 is set to the mode reproducing the NTSC signal. The operation control of the frequency of the VXO 3, the count K of the discrimination circuit 10 and the phase rotation of a frequency divider 5 is switched to that for the NTSC signal. Thus, the reproduction mode is discriminated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、種々の放送方式のビデ
オ信号を再生するVTRの再生モード判別回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR reproduction mode discriminating circuit for reproducing video signals of various broadcasting systems.

【0002】[0002]

【従来の技術】南米地方では、NTSC方式の他にPA
L/M方式と呼ばれるビデオ信号を1台で記録・再生す
るVTRが用いられている。両者の同期信号の周波数
は、等しい。両者のクロマ信号の周波数は、わずかに異
なっている。NTSC方式のクロマ信号の周波数は、
3.579545MHzであり、PAL/M方式のそれ
は3.57561149MHzである。両者の周波数
は、非常に近いので、例えば再生モードを判別する為に
両者を判別するのは難しい。両者を判別するには例え
ば、NTSC方式のバースト信号は常に一定位相で到来
するのに対して、PAL/M方式のバースト信号は、1
H(Hは1水平同期信号周期)毎に位相交番するのを利
用して、位相検波器により行うことが考えられる。
2. Description of the Related Art In South America, PA is used in addition to the NTSC system.
A VTR called an L / M system that records and reproduces a video signal by one unit is used. Both sync signals have the same frequency. The frequencies of both chroma signals are slightly different. The frequency of the NTSC chroma signal is
It is 3.579545 MHz, and that of the PAL / M system is 3.57561149 MHz. Since the frequencies of both are very close to each other, it is difficult to discriminate them, for example, in order to determine the reproduction mode. To distinguish between the two, for example, the burst signal of the NTSC system always arrives at a constant phase, whereas the burst signal of the PAL / M system is 1
It is conceivable that the phase detector is used by utilizing the phase alternation every H (H is one horizontal synchronizing signal period).

【0003】該位相検波器により、再生モードを識別し
たならば、その識別内容に応じてVTRの再生モードを
再生信号の種類に応じたモードに切換えれば良い。
When the reproduction mode is identified by the phase detector, the VTR reproduction mode may be switched to the mode corresponding to the type of the reproduction signal according to the identification content.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、位相検
波器は、多くの素子数(コンデンサを含む)を必要とす
る、という問題があった。
However, there is a problem that the phase detector requires a large number of elements (including capacitors).

【0005】[0005]

【課題を解決するための手段】本発明は上述の点に鑑み
成されたもので、水平同期信号周波数に応じた周波数で
発振するVCOと、該VCOの発振出力信号周波数が所
望値から変動するのを識別する周波数識別回路と、該周
波数識別回路の出力信号を平滑する平滑回路と、を有
し、前記平滑回路の出力信号に応じて再生モードの判別
を行うようにしたことを特徴とする。
The present invention has been made in view of the above points, and a VCO that oscillates at a frequency corresponding to a horizontal synchronizing signal frequency, and an oscillation output signal frequency of the VCO fluctuates from a desired value. And a smoothing circuit for smoothing the output signal of the frequency identifying circuit, and the reproduction mode is determined according to the output signal of the smoothing circuit. .

【0006】[0006]

【作用】本発明に依れば、VTRのクロマ信号の周波数
変換に用いられるVCOの発振出力信号周波数を識別す
る周波数識別回路の出力信号を平滑し、その平滑出力に
より再生モードを判別している。
According to the present invention, the output signal of the frequency discriminating circuit for discriminating the oscillation output signal frequency of the VCO used for frequency conversion of the chroma signal of the VTR is smoothed, and the reproduction mode is discriminated by the smoothed output. .

【0007】[0007]

【実施例】図1は、本発明の一実施例を示す回路図で、
PAL方式のクロマ信号を再生する場合である。(1)
はVTRの再生ヘッド(図示せず)から、低域変換され
た信号(周波数40 1/8fH 但し、fHは水平同期
信号周波数)が印加され、BPF(19)から周波数
(fSC+40 1/8fH、但し、fSCはクロマ信号周波
数)の信号が印加され、周波数fSCの信号を発生するメ
インコンバータ、(3)は周波数fSCで発振するVX
O、(4)はBPF(2)からの信号をVXO(3)か
らの信号の位相にロックさせる為の制御信号を発生する
APC検波回路、(21)は端子(6)からの再生水平
同期信号(図2(a))を1/8分周して、図2(b)
のパルスを作成する分周回路、(7)は、図2(b)の
パルスの「H」レベル期間中、閉じて、321fHで発
振しているVCO(8)の発振出力信号を通過させるス
イッチ、(9)は図2(b)のパルス「H」レベル期間
(4H)中、321fHのパルスをカウントするカウン
タ、(10)は、カウンタ(9)のカウント値Kが所定
範囲内(1284±3)であるか、所定範囲以上(12
84+3<K)であるか所定範囲以下(1284−3>
K)であるかを判別する判別回路、(11)は、前記所
定範囲以上の場合には図3(b)を、前記所定範囲以下
の場合には図3(a)を、前記所定範囲内の場合には3
(c)の信号を発生するエラー出力回路、(14)は、
エラー出力回路(11)の出力信号をLPF(12)で
直流に変換した信号と、APC検波回路(4)の出力信
号をLPF(13)で直流に変換した信号とを加算し
て、VCO(8)の周波数を制御する加算回路、(1
5)はエラー出力回路(11)の出力信号を整流平滑回
路(16)で整流及び平滑した電圧に応じて、再生モー
ド信号を判別するマイコン(マイクロコンピュータ)で
ある。
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
This is a case of reproducing a PAL system chroma signal. (1)
Is applied with a low-frequency converted signal (frequency 40 1 / 8f H, where f H is a horizontal synchronizing signal frequency) from a VTR reproducing head (not shown), and a frequency (f SC +40 1 is applied from BPF (19). / 8f H, however, f SC is a signal of the chroma signal frequency) is applied, the main converter for generating a signal of a frequency f SC, (3) is VX which oscillates at a frequency f SC
O and (4) are APC detection circuits that generate a control signal for locking the signal from the BPF (2) to the phase of the signal from the VXO (3), and (21) is the reproduction horizontal synchronization from the terminal (6). The signal (Fig. 2 (a)) is divided by 1/8,
The frequency dividing circuit (7) for generating the pulse of (7) is closed during the “H” level period of the pulse of FIG. 2B, and the oscillation output signal of the VCO (8) oscillating at 321 f H is passed. The switch (9) is a counter for counting 321f H pulses during the pulse “H” level period (4H) of FIG. 2B, and (10) is the count value K of the counter (9) within a predetermined range ( 1284 ± 3) or more than a predetermined range (12
84 + 3 <K) or less than a predetermined range (1284-3>)
The determination circuit (11) for determining whether or not K) is within the predetermined range is shown in FIG. 3B when the predetermined range or more, and FIG. 3A when the predetermined range or less. In case of 3
An error output circuit for generating the signal of (c), (14) is
A signal obtained by converting the output signal of the error output circuit (11) into a direct current by the LPF (12) and a signal obtained by converting the output signal of the APC detection circuit (4) into a direct current by the LPF (13) are added to obtain VCO ( 8) Adder circuit for controlling frequency, (1
5) is a microcomputer (microcomputer) that discriminates the reproduction mode signal according to the voltage obtained by rectifying and smoothing the output signal of the error output circuit (11) by the rectifying and smoothing circuit (16).

【0008】まず、図1の信号処理回路の再生モード
と、再生信号のモードとが一致している場合について説
明する。今、入力端子(17)にPAL/M方式である
周波数40 1/8fHの信号が、印加されるとする。そ
して、周波数がNTSC方式のクロマ信号周波数と、P
AL/M方式のそれとに切換わるVXO(3)の周波数
がPAL/M方式のそれになっている。又、周波数がN
TSC時の周波数320fHと、PAL時の321fH
切換わるVCO(8)の周波数が321fHになってい
るとする。VCO(8)の321fHの出力信号は、分
周回路(5)で周波数40(1/8)fHの信号に分周
され、サブコンバータ(18)に印加される。サブコン
バータ(18)にはVXO(3)から周波数fSCの信号
が印加され、周波数掛算が行われて、BPF(19)か
ら周波数(fSC+40(1/8)fH)の信号が発生す
る。すると、メインコンバータ(1)における周波数掛
算に応じてBPF(2)から周波数fSCに戻されたクロ
マ信号が得られる。
First, the case where the reproduction mode of the signal processing circuit of FIG. 1 and the mode of the reproduction signal match will be described. Now, it is assumed that a signal of frequency 40 1 / 8f H of the PAL / M system is applied to the input terminal (17). Then, the frequency is the chroma signal frequency of the NTSC system and P
The frequency of the VXO (3) switched to that of the AL / M system is that of the PAL / M system. The frequency is N
A frequency 320f H when TSC, the frequency of the VCO switched to 321f H when PAL (8) is to have become 321f H. The 321f H output signal of the VCO (8) is divided into a signal having a frequency of 40 (1/8) f H by the frequency dividing circuit (5) and applied to the sub converter (18). A signal of frequency f SC is applied from the VXO (3) to the sub converter (18), frequency multiplication is performed, and a signal of frequency (f SC +40 (1/8) f H ) is generated from the BPF (19). To do. Then, the chroma signal returned to the frequency f SC from the BPF (2) is obtained according to the frequency multiplication in the main converter (1).

【0009】一方、前記クロマ信号は、APS検波回路
(4)で検波され、そのエラー信号がLPF(13)及
び加算回路(14)を介してVCO(8)に印加され
る。その結果、出力端子(20)に得られるクロマ信号
の位相は、VXO(3)のそれに同期する。入力端子
(17)のクロマ信号と同期している図2(a)の水平
同期信号を分周回路(21)で分周した図2(b)の信
号に基づき、4H期間、スイッチ(7)が閉じると周波
数321fHの信号がカウンタ(9)でカウントされ
る。図2(b)に示す如く、4H期間直後にカウント値
の判別が判別回路(10)で行われる。今、判別回路
(10)がPAL/M方式の信号を受けるモードであれ
ば、エラー出力回路(11)の出力信号は、図3(c)
の如くなる。すると、LPF(12)の出力信号は、元
の値から変わらず、VCO(8)は321fHの周波数
を維持する。
On the other hand, the chroma signal is detected by the APS detection circuit (4), and its error signal is applied to the VCO (8) via the LPF (13) and the addition circuit (14). As a result, the phase of the chroma signal obtained at the output terminal (20) is synchronized with that of VXO (3). The horizontal synchronizing signal of FIG. 2 (a) synchronized with the chroma signal of the input terminal (17) is divided by the frequency dividing circuit (21) based on the signal of FIG. 2 (b), and the switch (7) is operated for 4H period. When is closed, the signal of frequency 321f H is counted by the counter (9). As shown in FIG. 2B, the determination circuit (10) determines the count value immediately after the 4H period. Now, if the discrimination circuit (10) is in the mode for receiving the PAL / M type signal, the output signal of the error output circuit (11) is as shown in FIG.
It becomes like. Then, the output signal of the LPF (12) does not change from the original value, and the VCO (8) maintains the frequency of 321f H.

【0010】一方、整流平滑回路(16)の出力信号の
値も変化せず、マイコン(15)は、VTRがPAL/
M方式の信号を再生しているモードであると、判別し続
ける。この状態から再生信号がNTSC方式の信号に切
変わったとする。この時、図1の装置は、PAL信号を
処理するモードなので次の不具合が起こる。
On the other hand, the value of the output signal of the rectifying / smoothing circuit (16) does not change, and the microcomputer (15) outputs VTR of PAL /
It continues to be discriminated that the mode is reproducing the signal of the M system. It is assumed that the reproduction signal is switched to the NTSC system signal from this state. At this time, since the apparatus of FIG. 1 is in the mode for processing the PAL signal, the following problems occur.

【0011】図4に示すようにPAL信号を再生する場
合、1フィールドおきにクロマ信号の90度位相シフト
(図1では省略)が行われる。ところが、NTSC信号
は、常に90度位相シフトを行い、1フイールド毎にそ
の位相方向が反転している。その為、単純に上述の再生
を行うと、この位相関係に起因しても誤差成分がAPC
検波回路(4)から図4(c)の如く発生する。図4
(C)の検波出力は、LPF(13)、加算回路(1
4)を介してVCO(8)に印加され、VCO(8)の
発振周波数は、図4(d)の通り変化する。ここで、V
CO(8)の周波数変化が所定範囲(1284±3)以
上まで変化すると、エラー出力回路(11)から図4
(e)の如き出力が発生する。図4(e)の信号は、整
流平滑回路(16)で図4(f)の如く整流され、図4
(f)の信号を平滑することにより安定した直流電圧を
得ることができる。
When the PAL signal is reproduced as shown in FIG. 4, a 90-degree phase shift (omitted in FIG. 1) of the chroma signal is performed every other field. However, the NTSC signal is always phase-shifted by 90 degrees, and its phase direction is inverted for each field. Therefore, if the above-mentioned reproduction is simply performed, the error component is APC even if it is caused by this phase relationship.
It is generated from the detection circuit (4) as shown in FIG. Figure 4
The detection output of (C) is the LPF (13) and the addition circuit (1
4) is applied to the VCO (8), and the oscillation frequency of the VCO (8) changes as shown in FIG. Where V
When the frequency change of CO (8) changes to a predetermined range (1284 ± 3) or more, the error output circuit (11) outputs the signal shown in FIG.
An output as shown in (e) is generated. The signal of FIG. 4 (e) is rectified by the rectifying / smoothing circuit (16) as shown in FIG.
A stable DC voltage can be obtained by smoothing the signal of (f).

【0012】該直流電圧に応じてマイコン(15)は、
図1の装置がNTSCの信号を再生するモードに切換え
る。VXO(3)の周波数、判別回路(10)のカウン
ト値K、分周回路(5)の位相ローテーションの動作制
御がNTSC用のそれに切換わる。従って、図1の装置
によれば再生モードを判別することができる。
According to the DC voltage, the microcomputer (15)
The apparatus of FIG. 1 switches to a mode for reproducing NTSC signals. The operation control of the frequency of the VXO (3), the count value K of the discriminating circuit (10), and the phase rotation of the frequency dividing circuit (5) is switched to that for NTSC. Therefore, according to the apparatus of FIG. 1, it is possible to determine the reproduction mode.

【0013】[0013]

【発明の効果】以上述べた如く、本発明に依ればVTR
の再生モードを簡単に判別することができる。特に本発
明に依れば、判別に際して、素子数を多く必要としな
い、という効果を有する。
As described above, according to the present invention, the VTR
The playback mode of can be easily identified. Particularly, according to the present invention, there is an effect that a large number of elements are not required for the discrimination.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は、本発明のVTRの再生モード判別回路
を示すブロック図である。
FIG. 1 is a block diagram showing a reproduction mode discrimination circuit of a VTR of the present invention.

【図2】図2は、図1の説明に供する為の波形図であ
る。
FIG. 2 is a waveform diagram for use in explaining FIG.

【図3】図3は、図1の説明に供する為の波形図であ
る。
FIG. 3 is a waveform diagram for use in explaining FIG.

【図4】図4は、図1の説明に供する為の波形図であ
る。
FIG. 4 is a waveform diagram for use in explaining FIG.

【符号の説明】[Explanation of symbols]

(8) VCO (9) カウンタ (10) 判別回路 (11) エラー出力回路 (8) VCO (9) Counter (10) Discrimination circuit (11) Error output circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 水平同期信号周波数に応じた周波数で発
振するVCOと、 該VCOの発振出力信号周波数が所望値から変動するの
を識別する周波数識別回路と、 該周波数識別回路の出力信号を平滑する平滑回路と、を
有し、前記平滑回路の出力信号に応じて再生モードの判
別を行うようにしたことを特徴とするVTRの再生モー
ド判別回路。
1. A VCO that oscillates at a frequency according to a horizontal synchronizing signal frequency, a frequency identification circuit that identifies that the oscillation output signal frequency of the VCO fluctuates from a desired value, and an output signal of the frequency identification circuit is smoothed. And a smoothing circuit for performing the determination of the reproduction mode according to the output signal of the smoothing circuit.
【請求項2】 前記周波数識別回路は、 水平同期信号周期に応じた一定期間、前記VCOの発振
出力信号の周波数をカウントするカウンタと、 該カウンタのカウント値が所望範囲内にあるか、それ以
外であるかを判別する判別回路と、 該判別回路の判別出力に応じてパルスを発生するエラー
出力回路と、から成ることを特徴とする請求項1記載の
VTRの再生モード判別回路。
2. The frequency discriminating circuit includes a counter for counting the frequency of the oscillation output signal of the VCO for a certain period according to a horizontal synchronizing signal period, and a count value of the counter is within a desired range or otherwise. 2. The VTR reproduction mode discriminating circuit according to claim 1, further comprising a discriminating circuit for discriminating whether or not the discriminating circuit and an error output circuit for generating a pulse in accordance with a discriminative output of the discriminating circuit.
JP11112394A 1994-05-25 1994-05-25 VTR playback mode determination circuit Expired - Fee Related JP3157382B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11112394A JP3157382B2 (en) 1994-05-25 1994-05-25 VTR playback mode determination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11112394A JP3157382B2 (en) 1994-05-25 1994-05-25 VTR playback mode determination circuit

Publications (2)

Publication Number Publication Date
JPH07322292A true JPH07322292A (en) 1995-12-08
JP3157382B2 JP3157382B2 (en) 2001-04-16

Family

ID=14553025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11112394A Expired - Fee Related JP3157382B2 (en) 1994-05-25 1994-05-25 VTR playback mode determination circuit

Country Status (1)

Country Link
JP (1) JP3157382B2 (en)

Also Published As

Publication number Publication date
JP3157382B2 (en) 2001-04-16

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