GB2160054A - PAL system colour processor - Google Patents

Abstract

In a PAL colour signal processor a phase shifter 4 shifts, at every horizontal scanning interval, the phase of the colour burst component of the PAL colour video signals. A phase locked loop circuit 9 generates a signal at a frequency equal to the frequency of the colour burst component output from the phase shifter; and a time axis corrector 2 carries out time axis correction of the PAL colour video signals according to the difference between the phase of the signal generated by the phase locked loop circuit 9 and the phase of the colour component output from the phase shifter. A phase inverter 12 uses the signal generated by the phase locked loop circuit for inversion of the PAL phase of the PAL colour video signal; and a detector 23 detects the presence or absence of synchronization between the respective colour burst components as output by the phase shifter 4 at the respective horizontal scanning intervals. <IMAGE>

Description

SPECIFICATION PAL system colour processor -i nis invention relates to a device for time axis correction of PAL colour video signals.

The colour video signal Ep in a PAL system is given by the equation: Ep = Y + (B - Y)Sin Ojst + (R - Y)Cos o)St ... (1 ) where Y is the brightness signal, B and R, respectively, the blue and the red signals, and ws the angular frequency of the colour subcarrier, this being about 4.43 MHz.The '+' sign in equation (1) signifies that phase inversion takes place at each horizontal scanning line, the (R - Y) component of the carrier colour signal being issued forthe respective horizontal scanning lines after amplitude modification as I Cosy'sot subcarrier signals at a mutual phase difference of 180 . For each line, therefore, information must be added for inversion of the phase of the subcarriers for demodulation of the (R - Y) component of the colour burst signal at the image receiver.

Accordingly, in succession,forthe respective line, the phase of the colour burst signal in inverted by switching it from + 135 to - 135 with respect to the (B - Y) axis.

Thus, when in the PAL method, colourvideo signals are reproduced from recording media like video disks by using a playback unit in one of the special playback modes like the still picture playback or the double speed playback, that is, by executing jumps from one information detection pointto another across specific numbers of tracks, the regularity of phase inversion is disturbed for the (R Y) component of the colour playback video signals and the colour burst signals. To regularise phase inversion in the PAL method, therefore, the colour video signals must be processed. Also, at the same time, the signals played back from the recording media always undergo variation along the time axis.

To deal with this, the variation component along the time axis must be detected and a correction applied along the time axis for the playback colour video signals.

The following method is applied for PAL phase correction, namely, correcting and regularising phase inversion for the (R - Y) component and the colour burst. A phase locked loop (PLL) circuit is used to generate subcarrier Cos cost at the same frequency as that of the colour burst signal. Subcarrier Coswst is then multiplied twofold after which it is multiplied with the carrier colour signal containing the colour burst component, thereby forming the carrier colour signal with inverted colour burst component and inverted (R - Y) component. The carrier colour signal obtained is then used to regularise the inversion of the colour burst signal and the (R - Y) component.In the method for timing axis correction, the 3.75 MHz pilot burst signal to be inserted in the PAL colour video signal during recording is sampled from the playback signals, after which this pilot burst signal is supplied to the PLL circuit which is formed in such a way as to generate a signal having a frequency equal to the frequency of the pilot burst signal. The resultant phase detection output is used as the time axis error signal.

A PAL colour signal processor built to perform the PAL phase correction and time axis correction as above will call for the use of two PLL circuits for two mutually different frequencies, namely, 3.75MHz and 4.43 MHz. This will create the disadvantage of making the unit complicated, increasing the number of components, and requiring several adjustments.

In order to overcome this problem, the phase detection output from the PLL circuit for PAL phase correction may be used also as the time axis error signal and time axis correction may be applied by using it. This makes it possible to make common use of the PLL circuit for PAL phase correction and time axis correction. However, in this approach, the quality of the playback screen is affected because, in the PAL method, the phase of the colour burst component of the colour video signal is inverted at each H (horizontal scanning interval), and it is difficult to carry out time axis correction for every H.

Because of this, it is necessary that the colour burst component be in the same phase at each H. To make the phases of the colour burst component identical, the phase of the colour burst component may be shifted by 90 at every alternate H. This makes it necessary to select the lines at which the colour burst components to be shifted by 90 exist.

However, since the number of tracks across which a jump must be executed from one information detection point is another is not constant in the scan operation mode, that is, the mode for retrieval of the desired frame, colour burst component phases cannot be made identical after scanning, so that time axis correction and PAL phase correction cannot be performed and the playback screen quality us likely to be affected.

As described above, the PAL colour video signals, when reproduced from the recording media, as for example, from video disks, are usually accompanied by time axis variations, making time axis correction necessary for the playback colour video signals after detecting the variation along time axis. Accordingly, the colour burst component of the playback colour video signals is sampled and variation in the phase of this burst signal can be detected by detecting the said time axis variation. Complete time axis correction becomes difficult and playback screen quality is affected if an attempt is made to detect the phase variation at every alternate horizontal scan time in view of the above described phase inversion of the colour burst component of the PAL colour signals at each H (horizontal scan time).For this reason, it is necessary to detect the time axis variation component at each H and correct the time axis for the playback signals at each H.

A system is known for detecting the time axis variation component at each H, in which the colour burst component is supplied to a phase locked loop (PLL) circuit whereas, to the signal detecting the phase difference between the colour burst and the output of the voltage control oscillator (VCO) in the PLL circuit is added the signal obtained by dividing into two, for example, the horizontal synchronizing signal to eliminate the 900 offset given rise to by phase inversion of the PAL colour burst component at each H, and treating the resultant signal as time axis error signal.However, in this method, the PLL circuit is locked to a phase that is the average of the t135" colour burst phase and -135" colour burst phase, and the phase detector in the PLL circuit is always supplied with two signals which differ in phasefrom each other by 900. Accordingly, the timing range of the phase comparator is shortened, and, when the phase error is large, proper time axis correction may not be possible.

According to the invention a PAL colour signal processor comprises a phase shifter to shift the phase of the colour burst component of PAL colour video signals, at every horizontal scanning integral, by a specific angle; and a phase locked loop circuit to generate signals of frequency the same as the frequency of the colour burst signal output from the phase shifter; and a time axis corrector using, for time axis correction of the PAL colour video signals, the difference in phase between the signal generated by the phase locked loop circuit and the colour burst output of the phase shifter.

Thus there can be provided a PAL colour signal processor which supplies a PLL circuit with colour burst signals the phases of which are synchronized alike for each of the respective horizontal scan times, and treats the phase error detection signal from the PLL circuit as time axis error signals so that time axis error detection is possible, assuring the necessary time axis correction effect. Also, at the same time, the timing range of the phase detector in the PLL circuit is not shortened so that, even if the time axis variation is large, proper time axis correction is assured.

A phase inverter may be provided to utilize the signal generated by the phase locked loop circuit to invert the phase of one of the colour carrier signals corresponding to the PAL colour video signals and the colour burst signal.

Thus a PAL colour signal processor can be provided which includes, for PAL phase correction and time axis correction, a single PLLcircuit generating signals of a frequency identical to the frequency of colour burst signals; which allows the circuitry to be small in size, reduces the number of components, and decreases the number of requirements of adjustments; and, at the same time, eliminates the errors due to interference between oscillators that is anticipated where two or more PLL circuits are used, generating singals of varying frequencies.

Advantageously there is provided a detector to detect the presence or absence of synchronization between the respective colour burst components as output by the phase shifter at the respective horizon tal scanning intervals.

It may also be necessary to align the phases of the colour bursts at the respective Hs. For this, the phases of the respective colour burst components may be shifted at every alternate H by 90" to align them. It is necessary in this instance -o select the horizontal scan times at which the colour burst components to be shifted by 90" in their phases exist. For the selection of the horizontal scan times, use of the playback horizontal synchronizing signal may be considered. Such use, however, will generate dropout causing the playback horizontal synchronizing signal to be false and, in the special playback mode, lead to jump operation that will affect the regularity of colour burst phase inversion, in either instance leading to selection of wrong horizontal scan time.As a result, the phases of the colour burst components cannot be aligned nor time axis correction or PAL phase correction applied, so that the quality of the picture will be affected.

Preferably therefore a controller is provided to issue a control signal which changes in state at the generation of a reference horizontal synchronizing signal and also with the change in state of the output signal from the detector; the control signal being used for selection of the horizontal scan time at which the colour burst component with its phase to be shifted by the above phase shifter exists.

Such a PAL colour signal controller may have an exclusive 'OR' gate which takes as its input any two of three signals, namely, a jump signal changing in state each time a jump operation command is issued, a dividing signal changing in state each time the reference horizontal synchronizing signal is generated, and the output signal from the detector; and a second exclusive 'OR' gate 2 which takes as its input the output of the exclusive 'OR' gate 1 and the remaining one of the above three signals, and gives as its output the exclusive 'OR' result of these two signals.

Thus a control signal is generated that changes in state when a jump command is issued, or when a reference horizontal synchronizing signal is generated, or when it is detected that the colour burst components given as output by the phase shifter at the respective horizontal scanning times do not agree with each other in phase. Thus, even if the playback horizontal synchronizing signal goes false because of a dropout, a wrong horizontal scanning time is not selected and, therefore, the screen quality at playback time is not disturbed.Furthermore, the state of the control signals for selection of horizontal scanning changes every time a jump command is issued in the playback mode at which no disturbance, as for example, still picture playback or double speed playback, should be present so that the colour burst signals supplied to the PLL circuit are synchronized to the same phase, and no disturbance occurs in the screen quality at playback time. Again, at playback time, disturbance in screen quality can be avoided because of the change in the state of the control signals for the selection of the horizontal scanning time after detection of an error by the phase detection output of the PLL circuit at the scan mode or when a wrong horizontal scan time is selected because of a disturbance. Even though time is required for error detection in this instance no problem occurs in respect of the visual quality because the scan mode agrees with the screen disturbance.

In the drawings: Figure 1 is a circuit block diagram showing an embodiment of the invention; and, Figures 2 to 6 are waveform drawings indicating the operation of the respective components of the device illustrated in Figure 1.

In Figure 1, an RF signal obtained from a recording disc (not shown), on which the PAL colour video signals are recorded, is supplied to FM demodulator 1. The PAL colour video signal demodulated by FM demodulator 1 is supplied to phase modulator 2.

This colour video signal becomes a first input at switch 3 and, at the same time, is shifted 90" in its phase by 90" phase shifter 4 after which it is supplied to the other input of switch 3. The selective output given by switch 3 is supplied to burst gate 5 for sampling of the colour burst component. The sampled colour burst component is supplied to PLL circuit 9 consisting of phase comparator 6, loop filter 7, and voltge control oscillator (VCO) 8 where the phase variation component is detected. Phase comparator 6 includes a sampling circuit to hold the phase comparator output after sampling it at each H.

The hold output from the sample hold circuit is applied, as an error signal, at the control input terminal of phase modulator 2 whereby this phase modulator performs time axis correction of the colour video signal output from FM demodulator 1.

The colour video signals after time axis correction at phase modulator 2, is supplied into Y-C (luminance-chrominance) separator 10 where it is resolved into the Y component and the C (carrier colour signal) component including the colour burst.

The C component becomes a first input of switch 11 and, at the same time, is supplied also to PAL phase inverter 12. PAL phase inverter 12 comprises multiplier 13, band pass filter 14taking as its input the output of multiplier 13, phase shifter 15 shifting the phase of the output from VCO 8 and giving as its own output subcarrier Cosost, and multiplier 16 which doubles the subcarrier signal frequency. Multiplier 13 multiplies the C components and output Coswst from multiplier 16. The C component obtained by PAL phase inversion ofthe output of BPF 14 becomes the other input for switch 11.

The output selected by switch 11 is added by adder 17 to the Y component, the resultant signal being fed as the first input to switch 18. The other input to switch 18 is the colour video signal after time axis correction. The output selected by switch 18, after PAL phase correction, becomes the colour video signal.

Controller 19 is provided to control switches 11 and 18. Controller 19 gives as its output a jump signal a changing its state every time a jump command is issued and playback mode signal b changing its state according to the playback mode, and supplies these two signals respectively, to switch 11 and switch 18. Jump signal a given as output by controller 19 is supplied also to lines selection signal generator 20. In line selection signal generator 20, jump signal a is applied to one input terminal of exclusive "OR" gate G1. To the other input terminal of exclusive "OR" gate G1 is applied output c of divider 22 which divides the reference horizontal synchronization signal as output by the reference horizontal synchronization signal generator 21. Output of exclusive "OR" gate G1 is applied to one input terminal of exclusive "OR" gate G2.To the other input terminal of exclusive "OR" gate G2 is applied output d of PAL phase detector 23. Output of exclusive "OR" gate G2 is control input e for switch 3.

PAL phase detector 23 is supplied with output error signal ffrom the phase comparator 6. In PAL phase detector 23, error signal fwhich is supplied to comparator 24 is compared with reference voltage Vrl. Output from comparator 24 is applied to trigger input terminal of retriggerable monomultivibrator (RMMV) 25. Output Q from RMMV 25 is supplied to comparator 27 via time constant circuit 26 and is compared there with reference voltage Vr2. Output of comparator 27 is applied to one of the input terminals of NAND gate G3. To the other input terminal of NAND gate G3 is applied output c of divider 22. Output of T flip-flop is the output of PAL phase detector 23.

The circuit configuration described above is intended to suppress time axis error of RF signal supplied to FM demodulator 1 by, say, tangentail mirror servo of the playback unit to a few +n sec (p-p) Colour subcarrier of PAL colour video signal has the frequency 4.43 MHz, namely, (284 - (114)) fH + 25 [Hzl (where fH is the horizontal synchronizing frequency), so that the interval corresponding to a picture does not work out to an integer multiple of the colour subcarrier wave period. For this reason a phase transition is generated in the colour subcarrier wave if a jump operation changes the playback sequence for the recorded pictures.However, an offset is added to the tangential servo, etc., of the playback unit at every change of the playback sequence so that a phase transition is not generated at jumps, etc., in the colour subcarrier of the colour video signal given as output from FM demodulator 1.

Accordingly, as shown in Figure 2(A), PAL phase, i.e., colour burst phase, of the PAL colour video signal given as output from FM demodulator 1 is inverted with respect to the B-Y axis at every H. As shown in Figure 2(b), therefore, the colour burst phase of the colour video signals, shifted by 90" phase shifter 4 becomes a signal inverted with respect to R-Y. Since output C of divider 22 is inverted at every alternate H, control input e for switch 3, obtained as output from exclusive "OR" gate G2 becomes a signal that is inverted at every H as shown in Figure 2 (C) unless the state of, respectively, jump signal a obtained as output from controller 19 and output dfrom phase detector 23 changes. For this reason the colourvideo signal output from FM demodulator 1 and the colour signal of which the phase is shifted by 90" phase shifter 4 are supplied to burst gate 5 at the alternate Hs. In this way, all the colour burst output from burst gate 5 is phased uniformly at +135 as shown in Figure 2(D).

It is also possible to change the direction of phase in 90" phase shifter 4 and phase all the colour burst output from burst gate 5 uniformly at -135".

Next, the colour burst of the colour video signal outputs from FM demodulator 1 respectively before and after jump command issue time t1 is synchronized to the same phase as shown in Figure 3(A).

Accordingly, the colour burst of colour video signal shifted by 90" phase shifter 4 is synchronized to the same phase before and after time t1. As for output c from divider 22 it is inverted alternately at the respective Hs as shown in Figure 3(C). Furthermore, jump signal a given to output controller 17 is inverted at time t1 as shown in Figure 3(D). Thus, as shown in Figure 3(E), the state of control input e to switch 3 does not change at time t1 unless the state of output d from PAL phase detector 23 changes so that, at time t1, switch 3 does not perform the switching function.As a result, immediately after time t1, the phase of the colour burst output from burst gate 5, as shown in Figure 3(F), is synchronized to +135 , remaining at the same phase at each respective H irrespective of the presence or absence ofjump operation.

Again, in the scan mode, that is, the mode for retrieval of the frames, the number of tracks through which jumps must be executed from one information detection point to the next is not constant. For this reason, the regularity of the colour burst phases in the colour video signal output of FM demodulator 1 is distrubed and, as shown in Figure 4(A), the colour burst is synchronized to the same phase before and after time t2. Accordingly, colour burst of colour video signal shifted by 90" phase shifter 4 also are synchronized to the same phase before and after time t2 as shown in Figure 4(B).However even in this instance, outputcfrom divider 22 is inverted atthe alternate Hs as shown in Figure 4(D), and the states of, respectively, jump signal a and output dfrom PAL phase detector 23 do not change and, therefore, control inputeto switch 3 is inverted also at time t2 as shown in Figure 4(f). Thus, as shown in Figure 4(C), the phase of colour burst output from burst gate 5 is synchronized from time t2 onwards at intervals of 1 H alternately to -135 and +45This causes output of a pulse generated at every 2H from phase comparator 9 to which this colour burst is supplied.The pulse given as output by phase comparator 9 is detected by PLL phase detector 23, the state of output dfrom which changes (time t3) as shown in Figure 4(E). As a result, from time t3 onwards, phase of control input e to switch 3 becomes a single opposite in phase to output cfrom divider 22. Thus, the phase of the colour burst forming part of the output selected by switch 3 is phased uniformly at +135', and from time t3 onwards, output from burst gate 5 and the colour burst become identical in phase.

The following is a description of the operations of PAL phase detector 23. A bit component is generated in error signal fgiven as output by phase comparator 6 because, when the phase of the colour burst output from burst gate 5 alternates between -135" and +45 at the successive Hs, PLL circuit 9 is not locked.

Furthermore, as shown in Figure 5, error signal f output from phase comparator 6 is like a signal formed by the pulse generated at every 2H since the signal supplied to phase comparator 6 for the successive Hs differs by 1800. The enveloping broken line in Figure 5 shows the waveform o: the bit component.

Accordingly, as Figure 6(A) shows, when the phase of the colour burst output from burst gate 5 alternates between - 135 and +45 at the successive Hs from time t4 onwards, a pulsating error signal fis issued by phase comparator 6. When the peak level of error signal freaches or exceeds reference voltage Vrl, positive pulse g issues from comparator 24 as shown in Figure 6(B). RMMV 25 is triggered when pulse g is generated, and Q output h goes low, as shown in Figure 6(C). When Q output h goes low, output voltage ifrom time constant circuit 26 rises as shown in Figure 6(D) with time constant T. Outputj from comparator 27 goes high (time t5) as shown in Figure 6(E) when output voltage i reaches or exceeds reference voltage Vr2.Output of comparator 27 is applied to one of the input terminals of NAND gate G3, whereas, to the other input terminal of NAND gate G3 is applied output c of divider 22, which in inverted, as shown in Figure 6(F), at every interval H.

As a result as shown in Figure 6(G), load pulse k (time t6) is issued as output by NAND gate G3. Load pulse kcauses inversion ofT flip-flop 28 the output from which, as shown in Figure 6(H), is inverted at time t6 and becomes output d of PAL phase detector 23. This causes inversion of control input e to switch 3 whereby the phase of the colour burst output from burst gate 5 is uniformly synchronized to +135 .

As a result of this, from time t6 onwards, PLL circuit 9 is locked decreasing the variation in the level of error signal foutput by phase comparator 6 whereby pulse g stops being given as output by comparator 24. On account of this, Q output kfrom RMMV 25 is fed back to the high level after a time T, equal to the inversion time of RMMV 25 (T =3H) from the time of last generation of pulse g. This leads to lowering of output voltage ifrom time constant circuit 26 at time constant T. Outputjfrom comparator 27 goes low when output voltage ifrom time constant circuit 26 reaches reference voltage Vr2 or less (time t7). As a result, pulse kstops being given as output by NAND gate G3 from time t7 onwards.

Erroneous inversion of output dfrom PAL phase detector 23 can be prevented by setting a time constants such that output voltage ifrom time constant circuit 26 cannot reach or exceed reference voltage Vr2 even if RMMV 25 is erroneously triggered because of, for example, a noise momentarily raising the peak level or error signal fgiven as output by phase comparator 6 to reach or exceed reference voltage Vr1.

The following describes the operation of PAL phase inverter 12. Let Sin(o)st + +)represent the component including the colour burst and Coseost represent the output from phase shifter 15 where o,st = 2Trfs (fs = 4.43 MHz). Under this assumption, output M from multiplier 13 is given by the following relation: M = Cos 20vSt. Sin(st + 4) = 1/2 Sin(3cost + 4) - Sin(st - ..... (2) From output M, component Sin(ost- ) is obtained by sampling the fundamental harmonic component only in BPF14.

Since 4 = 0 for component B-Y of the colour carrier signal the output from BPF14 becomes Sin ost and does not undergo phase inversion. Similarly, since 4 = Tor/2 for the R-Y component, the output from BPF14 becomes Sin (st - marl2, and phase inversion is received for the input Sin (cost + rr/2).

Furthermore, since 4) = 135 for the colour burst signal, BPF14 output becomes Sin (cost + 135 ) corresponding to input Sin (ost + 135 ), undergoing phase inversion. This makes PAL phase inversion possible.

In the normal playback mode, switch 18, in response to playback mode signal b supplied by controller 19, directly derives time-axis corrected colour video signals, bypassing PAL phase inverter 12, etc. In the special playback mode, it derives the colour video signal via PAL phase shifter 12, etc.

Regularity of PAL phase inversion can be assured even after the jump operation if, at the sametirne, switch 11 is assumed to be able to derive alternately the C component in response to jump signal a given as output by controller 19 and the C component undergoing PAL phase inversion in PAL phase inverter 12.

Atime axis error is contained in the C component output from Y/C separator 10 and the output from phase shifter 15. If + AO is assumed to be the time axis error, then the C component output from Y/C separator 10 and the output of phase shifter 15 will be represented by, respectively, Sin (cost + + + A0) and Cos (ost + At)). Accordingly, in this instance, output M of multiplier 13 will be given by the following expression: M = (2 cost + 2 Ae). Sin (cost + 4) + AO) = ,Sin (3cost + 4+3 A()) - Sin (cost + 4 +at)...(3) The component Sin (cost + 4+ A())is obtained here as in the instance where the time axis error was not taken into consideration, so that, despite the presence of time axis error AO, that is, the so-called residual jitter, PAL phase inversion is possible.

Claims (6)

1. A PAL phase signal processor comprising a phase shifter to shift the phase of the colour burst component of PAL colour video signals, at every horizontal scanning integral, by a specific angle; and a phase locked loop circuit to generate signals of frequency the same as the frequency of the colour burst signal output from the phase shifter; and a time axis corrector using, for time axis correction of the above PAL colour video signals, the difference in phase between the signal generated by the phase locked loop circuit and the colour burst output of the phase shifter.

2. A processor according to claim 1, further comprising a phase inverter utilizing the signal generated by the phase locked loop circuit to invert the phase of one of the colour carrier signals corresponding to the PAL colour video signals and the colour burst signal.

3. A processor according to claim 1 or claim 2, including a detector to detect the presence or absence of synchronization between the respective colour burst components as output by the phase shifter at the respective horizontal scanning intervals.

4. A processor according to any of claims 1 to 3, including a controller for issuing a control signal which changes in state at the generation of a reference horizontal synchronizing signal and also with the change in state of the output signal from the detector; the control signal being used for selection of the horizontal scan time at which the colour burst component with its phase to be shifted by the above phase shifter exists.

5. A processor according to claim 4, wherein the controller includes an exclusive 'OR' gate which takes as its input any two of three signals, namely, a jump signal changing in state each time a jump operation command is issued, a dividing signal changing in state each time the reference horizontal synchronizing signal is generated, and the output signal from the detector; and a second exclusive 'OR' gate 2 which takes as its input the output of the exclusive first 'OR' gate 2 and the remaining one of the above three signals, and gives as its output the exclusive 'OR' result of these two signals.

6. A PAL colour signal processor, substantially as described with reference to the accompanying drawings.