JPH0732041B2 - Multi-terminal hybrid IC terminal mounting structure - Google Patents

Multi-terminal hybrid IC terminal mounting structure

Info

Publication number
JPH0732041B2
JPH0732041B2 JP63140552A JP14055288A JPH0732041B2 JP H0732041 B2 JPH0732041 B2 JP H0732041B2 JP 63140552 A JP63140552 A JP 63140552A JP 14055288 A JP14055288 A JP 14055288A JP H0732041 B2 JPH0732041 B2 JP H0732041B2
Authority
JP
Japan
Prior art keywords
terminal
hybrid
terminals
mounting structure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63140552A
Other languages
Japanese (ja)
Other versions
JPH01311576A (en
Inventor
次郎 宇都宮
三郎 飯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP63140552A priority Critical patent/JPH0732041B2/en
Priority to US07/361,658 priority patent/US4985747A/en
Priority to DE68917798T priority patent/DE68917798T2/en
Priority to EP89305629A priority patent/EP0346035B1/en
Priority to EP93202116A priority patent/EP0577223A1/en
Publication of JPH01311576A publication Critical patent/JPH01311576A/en
Priority to US07/486,611 priority patent/US4989318A/en
Priority to US07/563,320 priority patent/US5081764A/en
Publication of JPH0732041B2 publication Critical patent/JPH0732041B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は入出力用に多くの端子を必要とするハイブリッ
ドICの製造方法及び端子構造に関する。
The present invention relates to a manufacturing method and a terminal structure of a hybrid IC which requires many terminals for input and output.

〔従来技術〕[Prior art]

従来この種のハイブリッドICは、基板上に部品のリフロ
ーによる半田付けと同時に入出力端子の半田接続も行っ
ている。このためリード71の一端を第4図(a)に示す
如く逆字形に折り返し曲がり部73を設け、リード71の
先端部72を半田付けパッド75に略垂直に当接し、リフロ
ーによる半田付け76を行っていた(実願昭61−134856号
参照)。
Conventionally, this type of hybrid IC has soldered by reflowing components on the board and soldering input / output terminals at the same time. For this reason, one end of the lead 71 is provided with an inverted bent portion 73 as shown in FIG. 4 (a), the tip end 72 of the lead 71 is brought into contact with the soldering pad 75 substantially perpendicularly, and soldering 76 by reflow is performed. Had been done (see Japanese Utility Model Application No. 61-134856).

又基板の片面に入出力端子を形成する他の方法は第4図
(b)のようにリードフレーム81を略ハット形に形成
し、ハットの1部にノッチ84を入れ、前記基板を挟持可
能な構造とし、半田デップにより半田付けし、後で連結
部83を取り除くことによってリード端子を構成していた
(特開昭62−266856号公報参照)。
Another method of forming the input / output terminals on one side of the board is to form the lead frame 81 in a substantially hat shape as shown in FIG. 4 (b), and insert a notch 84 in a part of the hat to sandwich the board. In this structure, a lead terminal is formed by soldering with a solder dip and then removing the connecting portion 83 (see Japanese Patent Laid-Open No. 62-266856).

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

ハイブリッドICの入出力端子が多数必要となってくる
と、基板の片面だけの接続では端子数が不足し、基板の
両面から入出力端子を設ける必要が生ずる。又ハイブリ
ッドICを搭載するマザーボードのスルーホールピッチは
強度、作業性等の理由から通常2.54mmピッチとなってい
る。このためある長さの実装範囲内で入出力端子の接続
を得るには、多列化する必要がある。しかしながら従来
の端子構造では基板の両面に多数の端子をリフロー又は
半田ディップにより固着することが非常に難かしいと云
う問題があった。
If a hybrid IC requires a large number of input / output terminals, the number of terminals will be insufficient if only one side of the board is connected, and it becomes necessary to provide input / output terminals from both sides of the board. Also, the through-hole pitch of the motherboard on which the hybrid IC is mounted is usually 2.54 mm pitch due to reasons such as strength and workability. Therefore, in order to obtain the connection of the input / output terminals within the mounting range of a certain length, it is necessary to use multiple rows. However, the conventional terminal structure has a problem that it is very difficult to fix a large number of terminals to both surfaces of the substrate by reflow or solder dipping.

本発明は前述の問題点に鑑みなされたもので、ハイブリ
ッドICの基板両面へ多端子を取付けリフローによって固
着することを目的とする。
The present invention has been made in view of the above problems, and an object thereof is to attach multiple terminals to both surfaces of a substrate of a hybrid IC and fix them by reflow.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明は多端子ハイブリッドICに端子を固定するに際
し、交互に曲げ位置を変え連鎖部で連結したくし状の多
端子を2枚1組とし互に向い合せ、基板の表、裏面に設
けた端子用パッド部を挟持するように固定し、リフロー
後にくし状の多端子から連鎖部を切断する。これにより
ハイブリッドICに千鳥格子のくし状多端子を形成する。
The present invention, when fixing a terminal to a multi-terminal hybrid IC, forms a pair of two comb-shaped multi-terminals, which are alternately bent at different bending positions and connected by a chain portion, and face each other. The pad portion is fixed so as to be sandwiched, and after reflow, the chain portion is cut from the comb-shaped multi-terminal. This forms a zigzag comb-shaped multi-terminal in the hybrid IC.

〔作用〕[Action]

本発明によれば、ハイブリッドICの入出力用端子を多数
設けるため、くし状の多端子を階段状に折り曲げる時に
交互に折り曲げ位置を変えることによって千鳥格子のく
し状多端子を実現した。この千鳥格子の多端子を形成し
たことによりマザーボードのスルーホールピッチ2.54mm
を維持し、更に強度や作業性を損うことなく端子の多列
化を図り、多端子構造を実現するものである。
According to the present invention, since a large number of input / output terminals of the hybrid IC are provided, the zigzag lattice multi-terminals are realized by alternately changing the folding positions when the comb-shaped multi-terminals are bent in a stepwise manner. Through-hole pitch of the motherboard is 2.54mm due to the multi-terminal of this houndstooth pattern.
It is intended to realize a multi-terminal structure by maintaining the above-mentioned characteristics and further increasing the number of rows of terminals without impairing the strength and workability.

〔実施例〕〔Example〕

第1図は本発明の実施例を示す斜視図である。これは金
属板の連続打抜き曲げ加工によりくし状の多端子とし、
階段状に折り曲げる時に交互に曲げ位置を変えて端子1
2,13を形成する。該端子12,13の一方は連鎖部11により
連結されている。
FIG. 1 is a perspective view showing an embodiment of the present invention. This is a comb-shaped multiple terminal made by continuous punching and bending of a metal plate,
Alternately change the bending position when bending in a staircase. Terminal 1
Form 2,13. One of the terminals 12 and 13 is connected by the chain portion 11.

基板の端子用パッドへ固着する半田付部18は連鎖部11の
反対の端に形成される。端子12は連鎖部11から直線に伸
び必要な端子長を形成した後、第1の曲げ14(山折り)
及び第2の曲げ15(谷折り)を行い先端に半田付部18を
形成する。ここで第1の曲げ14と第2の曲げ15の段差が
マザーボードの列方向スルーホールピッチとなる。
The soldering portion 18 fixed to the terminal pad of the board is formed at the opposite end of the chain portion 11. The terminal 12 extends straight from the chain portion 11 to form the required terminal length, and then the first bend 14 (mountain fold)
Then, the second bending 15 (valley fold) is performed to form the soldering portion 18 at the tip. Here, the step difference between the first bend 14 and the second bend 15 becomes the through hole pitch in the column direction of the motherboard.

次に端子13は連鎖部11からすぐに第1の曲げ16(山折
り)と第2の曲げ17(谷折り)を行い連鎖部を略平行に
必要な端子長を形成した後半田付部18を設ける。
Next, the terminal 13 is subjected to the first bending 16 (mountain fold) and the second bending 17 (valley fold) immediately from the chain portion 11 to form the necessary terminal length substantially parallel to the chain portion, and then the soldering portion 18 is formed. Set up.

次に本発明に係る多端子1を基板2にセットした時の説
明図を第2図に示す。
Next, FIG. 2 shows an explanatory view when the multi-terminal 1 according to the present invention is set on the substrate 2.

2枚の多端子1を1組とし互に向に合わせにしてクラン
プ治具4の固定部43と挟持部41,42との間に挟み込む。
この状態で基板2の端子用パッド21,22に多端子1の半
田付部12が合うようにセットする。クランプ治具4の押
えばね44の弾力によって基板2と多端子1とクランプ治
具4が保持される。従ってこのままの状態でリフロー装
置に流すことが可能となり基板2の端子用パッド21,22
と多端子1の半田付部18とが半田3によって固着、接続
される。
Two sets of the multi-terminals 1 are set as one set and face each other, and are sandwiched between the fixing portion 43 and the holding portions 41, 42 of the clamp jig 4.
In this state, the solder pads 12 of the multi-terminal 1 are set so as to fit the terminal pads 21 and 22 of the substrate 2. The substrate 2, the multi-terminal 1, and the clamp jig 4 are held by the elastic force of the pressing spring 44 of the clamp jig 4. Therefore, it becomes possible to flow into the reflow device as it is, and the terminal pads 21 and 22 of the substrate 2
And the soldered portion 18 of the multi-terminal 1 are fixed and connected by the solder 3.

第3図は本発明に係る端子組立工程図である。同図に基
づき本発明の端子組立工程を説明する。
FIG. 3 is a terminal assembly process diagram according to the present invention. The terminal assembling process of the present invention will be described with reference to FIG.

まず第3図(a)は裏面半田ペーストの印刷工程であ
る。通常基板2の端子用パッド21のみ半田ペースト3の
印刷が行われる。第3図(b)は部品搭載面(表面)の
半田ペースト印刷工程である。この工程は端子用パッド
22、部品用パッド23、24に半田ペースト3の印刷を行
う。第3図(c)は部品搭載工程であり、部品5,6を搭
載する。第3図(d)は多端子1の挿着工程であり、第
2図で説明したクランプ治具4に保持された多端子1の
半田付部18を多少ひらきぎみにして基板2の端子用パッ
ド21,22にセットする。前述の工程完了後リフロー装置
に流し、部品5,6と多端子1を同時に半田付する。第3
図(e)は最終工程で多端子1の中央部(第2図X−
X′線)にて連鎖部11を取り除くため切断を行い4列千
鳥格子の多端子1が完成する。
First, FIG. 3A shows a printing process of the back surface solder paste. Normally, the solder paste 3 is printed only on the terminal pads 21 of the substrate 2. FIG. 3B is a solder paste printing process on the component mounting surface (front surface). This step is for terminal pad
22. The solder paste 3 is printed on the component pads 23, 24. FIG. 3C shows a component mounting process, in which the components 5 and 6 are mounted. FIG. 3 (d) shows a process of inserting the multi-terminal 1, in which the soldering portion 18 of the multi-terminal 1 held by the clamp jig 4 described in FIG. Set on pads 21 and 22. After the above steps are completed, the components 5 and 6 and the multi-terminal 1 are soldered at the same time by flowing them into a reflow device. Third
The figure (e) shows the central part of the multi-terminal 1 (Fig. 2 X-
The multi-terminal 1 of the 4-row zigzag lattice is completed by cutting to remove the chain portion 11 at the X'line).

〔発明の効果〕〔The invention's effect〕

以上詳細に説明した如く本発明によればハイブリッドIC
の入出力端子を千鳥格子化することが容易で高密度実装
が可能となる。多端子は隣接端子共同様な第1曲げ第2
曲げが行われるため連続打抜き、曲げ加工の地取りサイ
ズを最小にでき、しかも高い寸法精度を得ることが容易
である。又端子組立は、搭載部品と共に同時リフローさ
れるため多端子接続のコストは非常に安価ですみ、高密
度実装に適した低コストの多端子ハイブリッドICを提供
することができる。
As described in detail above, according to the present invention, the hybrid IC
It is easy to form the input and output terminals in a zigzag pattern, which enables high-density mounting. Multiple terminals have the same first bending second
Since bending is performed, the ground cutting size for continuous punching and bending can be minimized, and it is easy to obtain high dimensional accuracy. Further, since the terminal assembly is simultaneously reflowed together with the mounted components, the cost of multi-terminal connection is very low, and it is possible to provide a low-cost multi-terminal hybrid IC suitable for high-density mounting.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る端子の斜視図、第2図は本発明に
係るリフロー時の端子取付構造図、第3図は本発明に係
る端子組立工程図、第4図は従来の端子組立図。 1……多端子、2,7,8……基板、3……半田ペースト、
4……クランプ治具、11……連鎖部、12,13……端子、1
8……半田付部、21,22……端子用パッド。
FIG. 1 is a perspective view of a terminal according to the present invention, FIG. 2 is a terminal mounting structure diagram during reflow according to the present invention, FIG. 3 is a terminal assembly process diagram according to the present invention, and FIG. 4 is a conventional terminal assembly. Fig. 1 ... Multi-terminal, 2,7,8 ... Board, 3 ... Solder paste,
4 ... Clamping jig, 11 ... Chain part, 12, 13 ... Terminal, 1
8 …… Soldering part, 21,22 …… Terminal pad.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ハイブリッドICの端子取付構造において 表裏面にパッドを有する基板と、先端に半田付部を設け
たくし状の端子を交互に階段状に曲げて千鳥格子を形成
した多端子と、該多端子を互に向い合わせて組となし前
記基板の表裏パッドに半田付部を固着したことを特徴と
する多端子ハイブリッドICの端子取付構造。
1. A terminal mounting structure for a hybrid IC, comprising: a substrate having pads on the front and back surfaces; and a multi-terminal in which a comb-shaped terminal provided with a soldering portion at its tip is alternately bent in a staircase pattern to form a houndstooth check pattern. A terminal mounting structure for a multi-terminal hybrid IC, characterized in that the multi-terminals are faced to each other to form a set, and soldering portions are fixed to front and back pads of the substrate.
JP63140552A 1988-06-09 1988-06-09 Multi-terminal hybrid IC terminal mounting structure Expired - Lifetime JPH0732041B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP63140552A JPH0732041B2 (en) 1988-06-09 1988-06-09 Multi-terminal hybrid IC terminal mounting structure
US07/361,658 US4985747A (en) 1988-06-09 1989-06-02 Terminal structure and process of fabricating the same
DE68917798T DE68917798T2 (en) 1988-06-09 1989-06-05 Connection structure and method for their production.
EP89305629A EP0346035B1 (en) 1988-06-09 1989-06-05 Terminal structure and process of fabricating the same
EP93202116A EP0577223A1 (en) 1988-06-09 1989-06-05 Mounting structure for a terminal
US07/486,611 US4989318A (en) 1988-06-09 1990-02-28 Process of assembling terminal structure
US07/563,320 US5081764A (en) 1988-06-09 1990-07-26 Terminal structure and process of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63140552A JPH0732041B2 (en) 1988-06-09 1988-06-09 Multi-terminal hybrid IC terminal mounting structure

Publications (2)

Publication Number Publication Date
JPH01311576A JPH01311576A (en) 1989-12-15
JPH0732041B2 true JPH0732041B2 (en) 1995-04-10

Family

ID=15271328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63140552A Expired - Lifetime JPH0732041B2 (en) 1988-06-09 1988-06-09 Multi-terminal hybrid IC terminal mounting structure

Country Status (1)

Country Link
JP (1) JPH0732041B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4600141B2 (en) * 2005-05-09 2010-12-15 Nok株式会社 Method for manufacturing FPC with connector

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63138673A (en) * 1986-11-29 1988-06-10 東芝ライテック株式会社 Lead frmane for circuit substrate

Also Published As

Publication number Publication date
JPH01311576A (en) 1989-12-15

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