JP2855309B2 - Lead frame for semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame of a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a lead frame of a surface mount type semiconductor device excellent in mass productivity and a surface mount using the lead frame. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 58-216448 and Japanese Patent Application Laid-Open No.
27679, JP-A-63-281451,
JP-A-52-86067 and JP-A-55-2765.
No. 5, JP-A-60-74459, and the like. Each of these prior arts has a structure in which a lead frame is aligned by holes and holes or holes and protrusions.

[0003] However, there is a structure which does not correspond to a structure in which a semiconductor chip is sandwiched between upper and lower lead frames, and even if such a structure is employed, sufficient consideration is not given to making the thickness of the brazing material uniform. .

[0004]

In a surface-mount type semiconductor device having a structure in which a semiconductor chip is sandwiched between upper and lower lead frames, the thickness of the brazing material is reduced by the power cycle of the semiconductor device when the semiconductor device is operated by being incorporated in an actual circuit. It is directly related to proof strength. Therefore, in order to manufacture a more uniform and highly reliable surface mount type semiconductor device, it is necessary to maintain the space between the upper and lower lead frames and the semiconductor chip within a predetermined range by some method.

In the above prior art, a dedicated jig is used to make the thickness of the brazing material or the like between the upper and lower lead frames and the semiconductor chip uniform. This dedicated jig cannot be removed until the semiconductor chip is fixed to the lead frame with a brazing material or the like, which has been a factor in lowering mass productivity.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a lead frame for a semiconductor device and a semiconductor device excellent in mass productivity, in which the thickness of a brazing material or the like between the upper and lower lead frames and the semiconductor chip can be made uniform without using a dedicated jig. It is to provide a method of manufacturing the device.

[0007]

In order to achieve the above object, the present invention has a first center bar which is partially connected by a tie bar and a frame at the center of the left and right frame frames and is parallel to the frame frame. A lower frame having a plurality of pairs of semiconductor chip mounting portions that are line-symmetric with respect to the first center bar on an axis perpendicular to the longitudinal direction of the frame frame and are integral with the frame frame, and a first center bar and a tie bar of the lower frame. Having a second center bar shaped to fit
A semiconductor comprising a second center bar and an upper frame which is disposed at a position corresponding to the semiconductor chip mounting portion of the lower frame on an axis perpendicular to the second center bar and has a plurality of pairs of semiconductor chip connection terminals each integral with the second center bar; A lead frame for the device is proposed.

The longitudinal end of the second center bar of the upper frame is cut into a length that abuts against the end surface of the tie bar of the lower frame to determine the longitudinal position of the upper frame.

In order to achieve the above object, the present invention also has a first center bar which is partially connected to the frame frame at the center of the left and right frame frames by a tie bar and is parallel to the frame frame. First on the axis perpendicular to the longitudinal direction
A lower frame having a plurality of pairs of semiconductor chip mounting portions which are line-symmetric with respect to the center bar and respectively integrated with the frame, and a second frame having a shape which goes over the first center bar and the tie bar of the lower frame and fits with the first center bar and the tie bar; A center bar, and a plurality of pairs of semiconductor chip connection terminals which are arranged at positions corresponding to the semiconductor chip mounting portions of the lower frame on an axis perpendicular to the second center bar and are respectively integral with the second center bar. A lead frame of a semiconductor device including a long upper frame is proposed.

In order to achieve the above object, the present invention further comprises a tie bar for partially connecting the left and right frame frames, and the right and left frame frames are respectively provided on an axis perpendicular to the longitudinal direction of the frame frame. A lower frame having a plurality of pairs of integrated semiconductor chip mounting portions, and a second center bar shaped to fit with the tie bar of the lower frame, and the semiconductor chip of the lower frame on an axis perpendicular to the second center bar. A lead frame for a semiconductor device comprising a second center bar disposed at a position corresponding to a mounting portion and an upper frame having a plurality of pairs of semiconductor chip connection terminals each integrated therewith is proposed.

Also in this case, the longitudinal end of the second center bar of the upper frame can be cut into a length that abuts the tie bar of the lower frame to determine the longitudinal position of the upper frame.

In order to achieve the above object, the present invention has a tie bar that partially connects the left and right frame frames, and is integrated with the left and right frame frames on an axis perpendicular to the longitudinal direction of the frame frame. A lower frame having a plurality of pairs of semiconductor chip mounting portions, and a second center bar shaped to fit over the tie bar of the lower frame and fit with the tie bar;
A second upper bar is provided at a position corresponding to the semiconductor chip mounting portion of the lower frame on an axis perpendicular to the center bar and has a long upper frame having a plurality of pairs of semiconductor chip connection terminals each integrated with the second center bar. A lead frame for a semiconductor device is proposed.

In any of the lead frames of the semiconductor device, the lower frame and the upper frame include at least three semiconductor chip mounting portions and semiconductor chip connection terminals on an axis perpendicular to the longitudinal direction of the left and right frame frames. be able to.

According to the present invention, in order to achieve the above object, a brazing material is set on a semiconductor chip mounting portion of a lower frame, a semiconductor chip is set, a brazing material is set thereon, and a center of the upper frame is set. The upper frame is set by combining the bar with the center bar of the lower frame and the tie bar or only the tie bar, and the center bar or the tie bar of the lower frame and the center bar of the upper frame are point-welded, and the brazing material is melted to melt the semiconductor chip. A method of manufacturing a semiconductor device in which a mounting portion, a semiconductor chip, and a semiconductor chip connection terminal are soldered is proposed.

If a passive element is arranged between the chip mounting portion of the lead frame and the chip connection terminal instead of the semiconductor element, a surface-mounted passive component can be manufactured.

[0016]

According to the present invention, the center bar and the tie bar of the lower frame are aligned with the center bar, for example, of the upper frame, and the upper and lower frames are fixed by point welding or the like. As a result, at the stage of brazing the semiconductor chip, a jig for positioning the upper and lower frames and the semiconductor chip is no longer necessary. In addition, since the lead frame has a line-symmetric structure with respect to the center bar per axis, the load of the upper frame is applied in a well-balanced manner, and the thickness of the brazing material is made uniform. In addition, at least twice as many semiconductor elements can be manufactured at one time as compared with the related art. That is, a lead frame of a highly reliable surface mount semiconductor device excellent in mass productivity and a method of manufacturing the surface mount semiconductor device can be obtained.

[0017]

1 to 12, a description will be given of an embodiment of a lead frame of a surface mount type semiconductor device and a method of manufacturing the surface mount type semiconductor device according to the present invention.

FIG. 1 is a plan view showing an example of the structure of a lower frame in a lead frame of a surface mount type semiconductor device according to the present invention. The lower frame 1 serving as an anode (or cathode) electrode includes frame frames 2 and 3 and a tie bar 4.
A center bar 5 integrally connected to the frame frames 2 and 3 and a semiconductor chip mounting portion 6 forming a pair with each other.
7 The semiconductor chip mounting parts 6 and 7 are frame-symmetrically mounted on the frame
From the right angle.

FIG. 2 is a plan view showing an example of the structure of the upper frame of the lead frame of the surface mount type semiconductor device according to the present invention. The upper frame 8 serving as a cathode (or anode) electrode is used in combination with the lower frame 1 in FIG. The upper frame 8 has a ∩-shaped center bar 9
And semiconductor chip connection terminals 10 and 11 forming a pair with each other. The ∩-shaped center bar 9 is combined with the center bar 5 and the tie bar 4 of the lower frame 1 and plays a role of alignment when manufacturing a semiconductor device. The connection terminals 10 and 11 for connecting to the semiconductor chip are arranged at right angles to the ∩-shaped center bar 9 so as to be located at positions corresponding to the semiconductor chip mounting portions 6 and 7 of the lower frame 1.

The upper frame 8 and the lower frame 1
Is generally manufactured by pressing or the like using a copper or iron plate material having a thickness of about 0.2 mm.

FIG. 3 is a perspective view showing an assembled state of the surface mount type semiconductor device using the lower frame 1 of FIG. 1 and the upper frame 8 of FIG. 2 in the course of manufacture, and FIG. FIG. 5 is a plan view showing a state after the alignment between the frame 1 and the upper frame 8, and FIG.
FIG. 6 is a view showing a cross section taken along the line A, FIG. 6 is a plan view showing an example of the structure of the manufactured surface-mount type semiconductor device, and FIG.
FIG. 3 is a view showing a cross section of the surface-mounted semiconductor device taken along line BB.

The lower frame 1 of FIG. 1 and the upper frame 8 of FIG.
In order to manufacture a surface-mount type semiconductor device by using FIG.
As shown in FIG.
7, the brazing material 13 is set, the semiconductor chip 12 is set, and the paste solder 14 is set thereon. Next, as shown in FIGS. 4 and 5, the upper frame 8 is set by combining the ∩-shaped center bar 9 of the upper frame 8 with the center bar 5 and the tie bar 4 of the lower frame 1.

Further, in order to fix the center bar 5 of the lower frame 1 and the セ ン タ ー -shaped center bar 9 of the upper frame 8, the center bar 5 and the ∩-shaped center bar 9 are, for example, point-welded at two points. After that, let it pass through the heating furnace,
The brazing material 13 and the paste solder 14 are melted, and the semiconductor chip mounting portions 6 and 7, the semiconductor chip 12, and the semiconductor chip connection terminals 10 and 11 are soldered. Next, the periphery of the semiconductor chip 12 is sealed with a resin 15 such as an epoxy resin.

Finally, the center bar 5 of the lower frame 1
The tie bars 4, the frame frames 2, 3 are cut off, and the セ ン タ ー -shaped center bar 9 of the upper frame 8 is also cut off, and the terminal portions protruding from the semiconductor chip mounting portions 6, 7 to the outside of the resin 15 are formed into a predetermined shape. Then, as shown in FIGS. 6 and 7, the surface-mounted semiconductor device according to the present invention is completed.

FIG. 8 is a view showing a modification of the shape of the alignment portions of the center bar 5 and the center bar 9 which are structural features of the lower frame 1 and the upper frame 8 of the embodiment shown in FIG. In this embodiment, the cross-sections of the center bar 5 and the center bar 9 are ∧-shaped.
Also in this embodiment, the same effects as those of the embodiment shown in FIGS. 1 to 3 can be obtained with respect to the alignment and the equalization of the thickness of the brazing material.

FIG. 9 is a view showing a modification of the shape of the center bar 5 and the alignment of the center bar 9 which are structural features of the lower frame 1 and the upper frame 8 of the embodiment of FIG. In the present embodiment, the cross sections of the center bar 5 and the center bar 9 are semicircular.
Also in this embodiment, the same effects as those of the embodiment shown in FIGS. 1 to 3 can be obtained with respect to the alignment and the equalization of the thickness of the brazing material.

FIG. 10 is a perspective view showing a structure of an alignment portion between the upper frame 8 and the lower frame 1 in the embodiment in which the upper frame 8 is continuously formed as a long object. The ∩-shaped center bar 9 of the upper frame 8 is the tie bar 4 of the lower frame 1
The present invention can be applied to a case where the upper frame 8 is continuously formed as a long object by making only a portion intersecting with a flat surface. Also in this embodiment, the same effects as those of the embodiment shown in FIGS. 1 to 3 can be obtained with respect to the alignment and the equalization of the thickness of the brazing material.

FIG. 11 is a perspective view showing the structure of an alignment portion between the upper frame 8 and the lower frame 1 in another embodiment in which the upper frame 8 is continuously formed as a long object. In this embodiment, the alignment portion between the center bar 9 of the upper frame 8 and the tie bar 4 of the lower frame 1 has a structure in which they are fitted to each other, and the center bar 5 of the lower frame 1 is omitted. Thus, even if the center bar 5 of the lower frame 1 is not provided, the same effects as those of the embodiment of FIGS. 1 to 3 can be obtained with respect to the alignment and the uniform thickness of the brazing material.

The embodiment shown in FIG. 11 is a case where the center bar 9 is a long object, but the center bar 9 is cut at a portion intersecting with the tie bar 4, that is, at the center of the ∩-shaped portion, and is similar to the embodiment of FIG. In this case, the same effect as in the embodiment of FIG. 11 can be obtained.

In each of the above embodiments, two shafts
This is an example in which a plurality of surface mount semiconductor devices are manufactured. On the other hand, FIG. 12 is a diagram showing an embodiment in which four surface mount semiconductor devices are manufactured per axis.

Conventionally, since the lead frame per axis is not axisymmetric, the load on the upper frame is poorly balanced, the thickness of the brazing material is not uniform, and it has been difficult to secure the flatness as a whole. Therefore, it was substantially impossible to manufacture a plurality of surface mount semiconductor devices per axis.

On the other hand, in this embodiment, the center bar 5 and the tie bar 4 of the lower frame 1 are aligned with the center bar 9 of the upper frame 8, and the upper and lower frames 8 and 1 are fixed by point welding or the like. At the stage of brazing the semiconductor chip 12, the upper and lower frames 8
And jigs for positioning the semiconductor chip 12 with 1 and 1
No longer needed. Moreover, since the lead frame has a line-symmetrical structure with respect to the center bars 5 and 9 per axis, the load of the upper frame 8 is applied in a well-balanced manner, and the thickness of the brazing material is made uniform. Therefore, a highly reliable surface mount semiconductor device can be mass-produced.

Also in this embodiment, the center bar 5 and the ∩
When the point-shaped center bar 9 is point-welded, the same effects as those of the embodiment shown in FIGS. 1 to 3 can be obtained with respect to the alignment and the equalization of the thickness of the brazing material.

It should be noted that, from the embodiment of FIG.
Modifications for manufacturing individual surface-mounted semiconductor devices can be easily imagined.

The above embodiment relates to the structure of the surface mount type semiconductor device. However, instead of mounting the semiconductor chip on the semiconductor chip mounting portion, passive elements such as resistors and capacitors are mounted. It goes without saying that the present invention is also effective when manufacturing passive components described above.

[0036]

According to the present invention, the upper and lower frames can be fixed by point welding or the like by aligning the center bar and tie bar of the lower frame with the center bar of the upper frame. The jig for positioning the upper and lower frames and the semiconductor chip is no longer necessary. In addition, since the lead frame has a line-symmetric structure with respect to the center bar per axis, the load of the upper frame is applied in a well-balanced manner, and the thickness of the brazing material is made uniform. Therefore, it is possible to obtain a lead frame of a highly reliable surface mount semiconductor device and a method of manufacturing the surface mount semiconductor device which are excellent in mass productivity.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a structure of a lower frame among lead frames of a surface mount semiconductor device according to the present invention.

FIG. 2 is a plan view showing an example of the structure of an upper frame among the lead frames of the surface mount semiconductor device according to the present invention.

FIG. 3 is a perspective view showing an assembled state of the surface-mount type semiconductor device using the lower frame of FIG. 1 and the upper frame of FIG. 2 during manufacture;

FIG. 4 is a plan view showing a state after alignment between a lower frame and an upper frame in FIG. 3;

FIG. 5 is a view showing a cross section of the lower frame and the upper frame of FIG. 4 taken along line AA.

FIG. 6 is a plan view showing an example of the structure of the manufactured surface-mount type semiconductor device.

FIG. 7 is a diagram showing a cross section along the line BB of the surface mount semiconductor device of FIG. 6;

FIG. 8 is a view showing a modified example relating to the shape of the center bar and the alignment portion of the center bar, which are structural features of the lower frame and the upper frame of the embodiment of FIG. 1;

FIG. 9 is a view showing a modified example relating to the shape of the center bar and the alignment portion of the center bar, which are structural features of the lower frame and the upper frame of the embodiment of FIG. 1;

FIG. 10 is a perspective view showing a structure of an alignment portion between the upper frame and the lower frame in the embodiment in which the upper frame is continuously formed as a long object.

FIG. 11 is a perspective view showing a structure of an alignment portion between an upper frame and a lower frame in another embodiment in which the upper frame is continuously formed as a long object.

FIG. 12 is a diagram showing an example of manufacturing four surface mount semiconductor devices per axis.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lower frame 2 Frame frame 3 Frame frame 4 Tie bar 5 Center bar 6 Semiconductor chip mounting part 7 Semiconductor chip mounting part 8 Upper frame 9 Center bar 10 Semiconductor chip connection terminal 11 Semiconductor chip connection terminal 12 Semiconductor chip 13 Brazing material 14 Paste solder 15 resin

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Yoneyama 3- 10-2 Bentencho, Hitachi City, Ibaraki Prefecture Inside Tachihara-cho Electronic Industry Co., Ltd. (72) Inventor Minoru Sugano 3-chome Bentencho, Hitachi City, Ibaraki Prefecture No. 2 Sun Tachiharacho Electronics Co., Ltd. (72) Inventor Atsushi Tsuruoka 3- 10-2 Bentencho, Hitachi City, Ibaraki Prefecture Sun Tachiharacho Electronics Co., Ltd. (72) Inventor Tomohide Hashimoto Benten, Hitachi City, Ibaraki Prefecture 3-10-2, Machi Tachiharacho Electronics Co., Ltd. (72) Inventor Kazutomo Narita 3-1-1, Kochimachi, Hitachi-shi, Ibaraki Pref.Hitachi, Ltd.Hitachi Plant (56) References JP 58 -216448 (JP, A) JP-A-2-33955 (JP, A)

Claims (7)

(57) [Claims] 1. A frame having a first center bar which is partially connected to the frame by a tie bar at the center of the left and right frame and is parallel to the frame, and is provided on an axis perpendicular to the longitudinal direction of the frame. A lower frame having a plurality of pairs of a plurality of semiconductor chip mounting portions which are line-symmetric with respect to the first center bar and respectively integrated with the frame, a second center having a shape fitted with the first center bar and the tie bar of the lower frame; A plurality of pairs of semiconductor chip connection terminals which are disposed at positions corresponding to the semiconductor chip mounting portions of the lower frame on an axis perpendicular to the second center bar and are respectively integral with the second center bar. A lead frame for a semiconductor device comprising: 2. The lead frame of the semiconductor device according to claim 1, wherein a longitudinal end of the second center bar of the upper frame contacts an end surface of the tie bar of the lower frame. A lead frame for a semiconductor device, which is cut to a length that determines a position in a longitudinal direction. 3. A frame having a first center bar which is partially connected to the frame by a tie bar at the center of the left and right frame and is parallel to the frame, and is provided on an axis perpendicular to the longitudinal direction of the frame. A lower frame having a plurality of pairs of semiconductor chip mounting portions that are line-symmetric with respect to the first center bar and are respectively integrated with the frame, and the first center bar and the tie bar of the lower frame, A second center bar having a shape fitted with the tie bar;
A center bar and a long upper frame having a plurality of pairs of semiconductor chip connection terminals, each of which is disposed at a position corresponding to the semiconductor chip mounting portion of the lower frame on the axis perpendicular to the center bar and has a plurality of semiconductor chip connection terminals each integrated with the second center bar; Semiconductor device lead frame. 4. A pair of a plurality of semiconductor chip mounting portions each having a tie bar for partially connecting the left and right frame frames, and being integrated with the left and right frame frames on an axis perpendicular to a longitudinal direction of the frame frame. A lower frame having a second center bar shaped to fit the tie bar of the lower frame, at a position corresponding to the semiconductor chip mounting portion of the lower frame on an axis perpendicular to the second center bar. A lead frame for a semiconductor device, comprising: an upper frame disposed and having a plurality of pairs of semiconductor chip connection terminals each being integrated with the second center bar. 5. The lead frame of the semiconductor device according to claim 4, wherein a longitudinal end of the second center bar of the upper frame abuts on the tie bar of the lower frame, and a longitudinal direction of the upper frame. A lead frame for a semiconductor device, which is cut to a length that determines the position of the semiconductor device. 6. A pair of a plurality of semiconductor chip mounting portions each having a tie bar for partially connecting the left and right frame frames, and being integrated with the left and right frame frames on an axis perpendicular to the longitudinal direction of the frame frame. A lower frame having a second center bar shaped to fit over the tie bar of the lower frame and to be fitted to the tie bar, and to be mounted on the semiconductor chip mounting portion of the lower frame on an axis perpendicular to the second center bar. A lead frame for a semiconductor device comprising: a second upper bar disposed at a corresponding position; and a long upper frame having a plurality of pairs of semiconductor chip connection terminals each integrated with the second center bar. 7. The lead frame of a semiconductor device according to claim 1, wherein said lower frame and said upper frame are on an axis perpendicular to a longitudinal direction of said left and right frame frames. At least 3
A lead frame for a semiconductor device, comprising: a plurality of semiconductor chip mounting portions and semiconductor chip connection terminals.