JPH07319694A - Processor controller - Google Patents

Abstract

PURPOSE:To set the integer instruction execution mode of a processor which is not controlled by a floating-point instruction execution mode by individually setting the execution modes of an integer instruction and a floating-point instruction and dynamically changing the setting during the operations of the respective instructions CONSTITUTION:Flags F1 and F2 for setting the instruction execution modes are written by a write part 1 and the states of the flags F1 and F2 are read by a read part 2. For instance, the flag Fl indicates the integer instruction execution mode and an instruction processing part for executing the integer instruction is operated in a scalar mode when the flag F1 is '0' and is operated in a single mode when the flag F1 is '1.' Also, the flag F2 indicates the floating point instruction execution mode and the instruction processing part for executing the floating point instruction is operated in the scalar mode when the flag F2 is '0' and is operated in the single mode when the flag F2 is '1'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor controller, and more particularly to a processor controller capable of simultaneously executing floating point instructions and integer instructions.

[0002]

2. Description of the Related Art In a conventional processor control device, a floating point instruction in which a numerical value handled by an instruction has a form having an exponent part and a mantissa part, and an integer instruction and an instruction having only integers in a form having no distinction between the exponent part and the mantissa part The execution modes were not distinguished. Further, the instruction execution mode is set to either a scalar mode in which a plurality of instructions are executed at the same time or a single mode in which one instruction is executed at the time of activation, and the setting cannot be changed thereafter. For example, it was not possible to change the setting from scalar mode to single mode during instruction execution.

That is, as shown in FIG. 4A, a coprocessor 11 for processing floating point instructions is connected to a processor 10 for processing integer instructions. And coprocessor 11
Is controlled by the processor control unit provided in the processor 10. The whole processor 10 and coprocessor 11 process integer instructions and floating point instructions. Further, as shown in FIG. 4B, one processor may process an integer instruction and a floating point instruction. Both were set to either scalar mode or single mode, and this mode could not be changed during operation.

[0004]

As described above, when the coprocessor 11 for floating point instruction processing is externally attached to the processor 10, the integer instruction execution mode of the processor 10 must match the instruction execution mode of the coprocessor 11. I have to. Therefore, even if the processor 10 can operate in both the scalar mode and the single mode, if the coprocessor 11 can operate only in the single mode,
Only single mode can operate as a whole.

In addition, the execution modes must be matched even when an integer instruction and a floating point instruction are processed by one processor. Further, when the instruction execution mode is fixed to the scalar mode, there is a problem that the debugging work of the program becomes complicated. That is, when a plurality of instructions are executed at the same time, or when the execution of a specific instruction is finished, it may be desired to check the execution state, but the operation confirmation process becomes complicated as compared with the case of executing one instruction at a time. Moreover, in the scalar mode, a plurality of exceptions (interrupts) may occur at the same time during the execution of a plurality of instructions, and the hardware for handling the exceptions becomes complicated.

In order to solve these problems, an object of the present invention is to make it possible to individually set the execution mode of an integer instruction and a floating point instruction of a processor (and a coprocessor), and set this operation for each instruction. (EN) Provided is a processor control device capable of setting an integer instruction execution mode of a processor which is not influenced by a floating point instruction execution mode by dynamically changing the inside.

[0007]

In order to achieve the above object, the present invention according to claim 1 provides a first processor for executing a first instruction and a second processor for executing a second instruction. In a processor control device for controlling a processor according to an operating state of a processor, flags F1 and F2 for instructing whether the first processor and the second processor operate in a scalar mode or a single mode, respectively. And these flags F1, F2
In addition, a writing means for writing the operating state of the processor and a reading means for reading the operating state of the processor from these flags F1 and F2 are provided.

According to a second aspect of the present invention, in the processor control device for controlling the processor executing the first instruction and the second instruction according to the operating state of the processor, when executing the first instruction, Whether the processor operates in the scalar mode or the single mode, the first flag F1 that indicates the operating state of the processor and the second instruction when the processor operates in the scalar mode or in the single mode. A second flag F2 for instructing whether the processor is operating or not, a writing means for writing the operating state of the processor to the first and second flags F1, F2, and the first and second flags F1, It is characterized in that a reading means for reading the operating state of the processor from F2 is provided.

According to a third aspect of the present invention, the first instruction is an integer instruction and the second instruction is a floating point instruction. In the present invention according to claim 4, a decoding unit is provided, and when an exception occurs when the instruction execution mode is the scalar mode, the value of the flag for the processor executing the scalar mode is changed to the value of the single mode instruction. The feature is that the instruction in which the exception occurs is re-executed from the beginning in the single mode to reproduce the exception, and after the exception is processed, the instruction execution mode is returned to the scalar mode.

In the present invention, as shown in FIG. 1A, flags F1 and F2 for setting the instruction execution mode by the writing section 1 are set.
And the reading unit 2 reads the states of the flags F1 and F2. In this example, the flag F1 indicates the integer instruction execution mode. As shown in FIG. 1B, when the flag F1 is "0", the instruction processing unit that executes the integer instruction operates in the scalar mode and the flag F1 indicates "1". In this case, it operates in single mode.

The flag F2 indicates a floating-point instruction execution mode. The instruction processing unit that executes the floating-point instruction operates in the scalar mode when the flag F2 is "0", and the flag F2.
When 2 is "1", it operates in single mode.

[0012]

Therefore, depending on the states of the flags F1 and F2, as shown in FIG.
As shown in (B), the instruction processing unit that executes integer instructions and the instruction processing unit that executes floating point instructions can set four types of instruction execution modes.

The reading unit 2 reads the states of "0" and "1" of these flags F1 and F2, transmits the respective states to a processor control unit (not shown), and responds to them by an integer instruction processing unit, The floating point instruction processing unit operates in each instruction execution mode.

Since the setting of the flags F1 and F2 can be rewritten by the micro instruction using the writing unit 1, the setting can be dynamically changed by the macro instruction or the micro instruction. In the present invention, the flags F1 and F2 can be dynamically changed without stopping the operation of the processors (processor and coprocessor). Therefore, the execution mode can be set regardless of the operation modes of the two instruction processings of the processor. Further, since the normal scalar execution processor can be controlled in the single mode, the debugging work of the program for the scalar execution processor can be simplified and the hardware for exception handling can be simplified.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an operation explanatory diagram thereof.

In FIG. 2, the same symbols as in the other figures indicate the same parts, 1 is a writing part, 2 is a reading part, 3 is a decoding part, 4 is an integer instruction control part, 5 is a floating point instruction control part, and 6 is. table,
F1 is a flag for setting the execution mode of the integer instruction processing unit, F
Reference numeral 2 is a flag for setting the execution mode of the floating point instruction processing unit.

The writing unit 1 writes the flags F1 and F2, and each flag can be written individually or simultaneously. This writing can be enabled based on a macro instruction or a micro instruction.

The reading unit 2 reads the flags F1 and F2, and can read each flag individually. The decoding unit 3 determines which of the flags F1 and F2 is "0" or "1" based on the table 6 according to the operation mode of the integer instruction and the floating point instruction at the time of activation, or when an exception occurs, which instruction processing unit It decodes whether this has occurred, and instructs the writing unit 1 to write "0" in the flag of the instruction processing unit in which the exception occurred.

The integer instruction control unit 4 controls the processing mode of integer instructions. The floating point instruction controller 5 controls the floating point processing mode. The table 6 shows the states of the flags F1 and F2 set to “0” and “1” corresponding to the operation modes of the two instruction processes, and is a table as shown in FIG. 1B, for example. .

Next, the operation of the present invention will be described. 1. First, operate the integer instruction processing unit in scalar mode,
An instruction to operate the floating point instruction processing unit in the single mode is input. The decoding unit 3 decodes this, refers to the table 6, and sets the flag F1 to "0" for the writing unit 1.
To write the flag F2 to "1". As a result, the writing unit 1 sets the flag F1 to "0" and the flag F2.
Is written in "1".

2. The reading unit 2 reads these flags and notifies the integer instruction control unit 4 that the flag F1 is "0" and the floating point instruction control unit 5 that the flag F2 is "1". Based on this, the integer instruction control unit 4 operates the integer instruction processing unit in the scalar mode and executes a plurality of instructions. Further, the floating point instruction control unit 5 operates the floating point instruction processing unit in the single mode to execute one instruction.

3. In this way, the integer instruction processing unit operates in the scalar mode, and the floating point instruction processing unit operates in the single mode. 4. Now, as shown in the processing of FIG. 3A, when the integer instruction processing unit is executing the instruction 1, the instruction 2, and the instruction 3 in the scalar mode, the instruction 2 is divided by zero or overflows. When an exception such as “doing” occurs, an exception occurrence notification is input from the integer instruction processing unit to the decoding unit 3. At this time, the integer instruction processing unit suspends execution of instructions 1 to 3.

5. The decoding unit 3 decodes this, recognizes that the exception has occurred in the integer instruction processing unit, and sets the execution mode flag F of the integer instruction processing unit in which the exception has occurred.
The writing unit 1 is notified that 1 is written in "1". As a result, the writing unit 1 writes "1" in the flag F1 and notifies the reading unit 2 of the writing of the flag.

6. The reading unit 2 thereby detects the flag F1,
F2 is read and these are sent to the integer instruction control unit 4 and the floating point instruction control unit 5. Since the floating-point instruction control unit 5 does not change the flag F2, the single-mode operation continues as before, but the flag F1 is "1".
The integer instruction control unit 4 causes the integer instruction processing unit 4 to operate in the single mode by being written in.

7. As a result, the integer instruction processing unit
As shown in the process of (A), the process is re-executed from the instruction 1. Then, by re-executing the instruction 2 in the process, the exception occurrence is reproduced and the exception process is performed. The decoding unit 3 recognizes from the processing that the exception processing is performed and that the processing should be executed in the scalar mode, and sets the flag F1 to "0" again.
The writing unit 1 is instructed to do so. As a result, the writing unit 1 sets the flag F1 to "0". Since the writing of the flag is notified to the reading unit 2, the reading unit 2 again sets the flag F.
1 and F2 are read, and these are notified to the integer instruction control unit 4 and the floating point instruction control unit 5, and the integer instruction control unit 4 returns the integer instruction processing unit to the scalar mode. Thus, as shown in the processing, the instruction 3 is executed in the scalar mode, and the instruction 3, the instruction 4, and the instruction 5 are executed.

The operation of the present invention is as shown in FIG.
The case where multiple exceptions occur simultaneously will be described. 1. As shown in the process of FIG. 3B, when an exception occurs in the instruction 1 and the instruction 2 while the integer instruction processing unit is simultaneously executing the instruction 1, the instruction 2, and the instruction 3 in the scalar mode, the integer instruction processing unit is notified to the decoding unit 3. Exception notification is entered. At this time, the integer instruction processing unit suspends the execution of instructions 1 to 3.

2. The decoding unit 3 decodes this exception occurrence notification, recognizes that the exception has occurred in the integer instruction processing unit, and sets the execution mode setting flag F1 of the integer instruction processing unit.
The writing unit 1 is notified that the writing is to be performed in "1". As a result, the writing unit 1 sets the flag F1 to "1" and notifies the reading unit 2 of the writing of the flag.

3. The reading unit 2 thereby detects the flag F1,
F2 is read and these are sent to the integer instruction control unit 4 and the floating point instruction control unit 5. Since the flag F2 remains "1" without change, the operation continues in the single mode as before. However, since the flag F1 is written in "1", the integer instruction control unit 4 sets the integer instruction processing unit to a single state. Run in mode.

4. As a result, the integer instruction processing unit
As shown in the process of (B), it is re-executed from the instruction 1. Then, in the processing, exception processing of the instruction 1 is performed. 5. As a result, the decoding unit 3 recognizes from the processing that it should be executed in the scalar mode, instructs the writing unit 1 to set the flag F1 to "0" again, and the integer instruction processing unit executes the scalar processing in the same manner as described above. The operation is performed in the mode, and the instruction 2, the instruction 3, and the instruction 4 are simultaneously executed.

6. However, in this process, an exception is generated from the instruction 2, so that the flag F1 is again set as described above.
Is set to "1", the integer instruction processing unit is operated in the single mode, and the exception processing of the instruction 2 is performed in the processing.

7. As a result, as described above, the flag F is returned to again.
1 is set to "0", and as shown in the process, the integer instruction processing unit operates in the scalar mode, and the instruction 3, instruction 4, instruction 5
Are processed simultaneously.

Since the writing of the flags F1 and F2 can be rewritten by the microinstruction using the writing section, the setting can be dynamically changed by the macroinstruction or the microinstruction. In the above description, the case where the number of a plurality of instructions executed in the scalar mode is 3 has been described, but the present invention is not limited to this.

In the above description, the case where the writing unit 1 writes only the flag of the integer instruction processing unit (or the floating point instruction processing unit) on the side where the exception has occurred has been described, but in the present invention, two flags F1 and You can also write F2 together. In this case, the flag that is not changed is "0",
As for “1”, for example, it may be read out from the reading unit 2 prior to writing and notified to the writing unit.

In the above description, the case where the reading unit 2 reads the flag when notified by the writing unit 1 has been described, but the present invention is not limited to this.
The reading unit 2 can also be configured to read each flag at regular time intervals regardless of whether or not there is a notification.

In the above embodiment, the case where one processor processes an integer instruction and a floating point instruction has been described, but in the present invention, an integer instruction is processed as shown in FIG. 4 (A). The same control can be performed when a processor that processes floating-point instructions is connected to the processor.

Although the example of the single mode when the flag is "1" and the scalar mode when the flag is "0" has been described, the present invention is not limited to this.

[0037]

According to the present invention described in claim 1,
When the coprocessor for floating-point instructions is connected to the processor, the integer instruction execution mode of the processor can be set regardless of the instruction execution mode setting of the coprocessor.

According to the second aspect of the present invention, the execution mode can be set individually even when an integer instruction and a floating point instruction are processed by one processor. According to the present invention described in claim 1 or 2, it is possible to change the instruction execution mode without stopping each processor during program execution.

Since it is easy to switch the processor under scalar execution to the single mode, the debugging work can be simplified. According to the present invention described in claim 3, even when processing an integer instruction and a floating point instruction, the execution mode can be set individually.

According to the present invention described in claim 4, since a plurality of exceptions are not processed at the same time, the hardware structure for exception processing can be simplified.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Writing unit 2 Reading unit 3 Decoding unit 4 Integer instruction control unit 5 Floating point instruction control unit 6 Table

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Watanabe Inventor Toru Watanabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Maruyama 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 72) Inventor Shinya Kato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Takeno, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Pawnshai Chon Swan Napaisan 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Naka, 1015 Kamiotanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Katsunori Takeshita Nakahara-ku, Kawasaki, Kanagawa 1015 Kamiodanaka, Fujitsu Limited

Claims (4)

[Claims] 1. A processor controller for controlling a first processor executing a first instruction and a second processor executing a second instruction according to an operating state of the processor, the first processor and the first processor Flags F1 and F2 for instructing whether the two processors operate in the scalar mode or the single mode, respectively.
And a writing means (1) for writing the operating state of the processor to these flags F1 and F2, and a reading means (2) for reading the operating state of the processor from these flags F1 and F2. Control device. 2. A processor control device for controlling a processor for executing a first instruction and a second instruction according to an operating state of the processor, wherein the processor is operated in a scalar mode when the first instruction is executed. , A first flag F1 which indicates whether the processor operates in the single mode or the operating state of the processor, and whether the processor operates in the scalar mode or the single mode when the second instruction is executed. A second flag F2 for instructing, a writing means (1) for writing the operating state of the processor in the first and second flags F1, F2, and an operation of the processor in the first and second flags F1, F2. A processor control device comprising a reading means (2) for reading a state. 3. The processor control apparatus according to claim 1, wherein the first instruction is an integer instruction and the second instruction is a floating point instruction. 4. A decoding unit (3) is provided, and when an exception occurs when the instruction execution mode is the scalar mode, the value of the flag for the processor executing the scalar mode is changed to the value of the single mode instruction to generate the exception. 4. The processor control device according to claim 1, wherein the instruction execution mode is re-executed in the single mode from the beginning to reproduce the exception, and the instruction execution mode is returned to the scalar mode after the exception is processed.