JPS5922146A - Task scheduling circuit - Google Patents

Abstract

PURPOSE:To schedule task efficiently, by providing an interruption controlling circuit which causes an interruption to a CPU and an interruption address generating circuit which reports a jump destination address when an interruption takes place. CONSTITUTION:Signals A0, B0, C0, and D0 are specific operation ion condition signals of tasks A, B, C, and D. A signal INT is an interruption mask from a peripheral device. A task scheduler 10 includes FFs 11-19 and logical circuits 20-22 having logic corresponding to task structure. Output signals (i), (a), (b), (c), (d), (e), and (f) of this scheduler 10 are inputted to the controlling circuit 30 and interruption address generating circuit 40. Only one task applies an interruption signal P from the circuit 30 to a CPU according to predetermined priority. The circuit 40 is an encoder circuit and reports the jump destination address of an interruption to the CPU through a bus DB when the interruption occurs to the circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a task scheduling circuit that efficiently schedules tasks in real-time processing.

As is well known, a task is a unit of work that is processed by a computer managed by an operating system.In other words, a task has a certain purpose defined, and is executed by a computer to achieve a predetermined purpose. . A task is simply a program in the absence of a multiprogramming environment, but in a multiprogramming environment a task is a task controller (part of the operating system).
It is placed under the control of , and becomes the processing unit of multiple programming processing. Therefore, there are many tasks in the system, and these tasks execute their respective programs while alternately using the central processing unit and other system resources, realizing parallel processing of multiple programs as a whole. has been done.

Conventionally, task scheduling in a microcomputer system has been executed by a piece of computer software called a monitor.

Scheduling of tasks by this monitor involves 1) searching the status of each task in order and granting the right to use the central processing unit, etc. to a task that is found to be in an executable state (ready state); 11) completion of input/output; There is a system that inputs tasks into a queue in the order in which they move from a wait state such as waiting state to the above-mentioned ready state, and gives the right to use a central processing unit or the like to the tasks output from the queue in order.

However, since all of these conventional task scheduling methods are controlled by software, the scheduling speed is slow, which has a significant negative impact on improving the processing speed of the entire system. This tendency became particularly noticeable as the number of tasks to be managed increased.

Furthermore, if the software-based task scheduler is made general-purpose so that it can be used in other systems, the task scheduling or priority setting function for each task is degraded.

This invention has been made in view of the above circumstances, and provides a task scheduling circuit that achieves more efficient task scheduling in real-time processing by implementing all functions necessary for task scheduling using hardware. The purpose is to

That is, the present invention includes a task scheduler whose logic is configured to correspond to a predetermined task structure, and a task scheduler that selects only one of the outputs of the task scheduler based on a predetermined priority order among each task. An interrupt control circuit that interrupts the central processing unit according to the selected signal, and a task that is to be interrupted based on the output of the task scheduler when an interrupt by the interrupt control circuit occurs to the central processing unit. The above object can be achieved by providing an interrupt address generation circuit that forms a signal indicating the start address and applies the formed signal to the central processing unit to inform the central processing unit of the jump destination address due to the interrupt K. That is.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A task scheduling circuit according to the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

First, FIG. 1 shows an example of a task structure to be processed within the system. In addition, signal A. +BOrco and Do are operation condition signals for causing task A, task B, task C, and task D to respectively execute predetermined operations, and INT is a task caused by an interrupt from a peripheral device. That is,
Task A executes a predetermined operation when the operating condition signal Ao is input, task B executes a predetermined operation when the operating condition signal Bo is input, and task C executes a predetermined operation when the operating condition signal co is input. Task D executes a predetermined operation when the operation condition signal R is input and the operations of tasks B and C are completed, and task E executes a predetermined operation when the operation of task C is completed. Further, when an interrupt task signal INT is input from a peripheral device and the interrupt task signal INT is completed, a predetermined operation is executed, and when the operations of tasks D and E are completed, task F executes a predetermined operation. On the other hand, it is assumed that priorities are determined in advance among these tasks, and the priorities increase in the order of task F, task E1 task D1 task C1 task B, task A, and task INT.

Next, FIG. 2 shows an example of a circuit configuration when scheduling tasks having the structure shown in FIG. 1 is carried out by the task scheduling circuit according to the present invention.

In the figure, a task scheduler 1o has a logic corresponding to the task structure shown in FIG. 1 constructed by several D-type flip-flops (hereinafter simply referred to as flip-flops) and logic gates. The D terminals of the flip-flops 11 to 14 are respectively connected to an output buffer of a central processing unit (hereinafter referred to as CPU), not shown, as appropriate, and receive an operating condition signal A necessary for starting each task. +B(+
+CO+D.

is now entered. Of course, if the above operating condition signal output from the CPU is insufficient to be input to the flip 70 knobs 11 to 4, the logic is calculated by an appropriate logic circuit such as a decoder beforehand. The signal may be inputted to the flip-flops 11 to 14 after being made into a predetermined signal. On the other hand, in case an interrupt from a peripheral device is applied to the CPU, the task scheduler 10 has a peripheral device interrupt signal INT indicating this fact.
is now entered. The logic gate 20 is a logic for starting the task D, and its input terminal is connected to the output terminals of the flip 70 knobs 16 and 17 and the output terminal of the flip-flop 14 for the operating condition signal Do for starting the task D. has been done. Logic gate 21 is a logic for activating task E, and its input terminal is connected to the output terminal of flip-flop 17 and the output terminal of 7-lip 70-tub 15 for the peripheral device interrupt signal INT. Logic gate 22 is a logic for starting task F, and its input terminal is connected to flip-flop 18.
and 19 output terminals. The clock terminals C of the knobs 11 to 19 of the full control unit 70 are connected to an appropriate lock generation circuit (not shown), and operate in synchronization with the operation of the system. After the logical waves corresponding to the predetermined task structure are formed in this way, the output signals i, a, b, c, and d of the task scheduler 10 are generated.

e and f are input to an interrupt control circuit 30 and an interrupt address generation circuit 40, which will be described later.

The interrupt control circuit 30 is a logic circuit whose logic is configured according to the priority order described above, and its output terminal is connected to a C port (not shown).
Connected to the PH interrupt terminal.

An example of this logic is a logical expression as shown in block 30 in the figure. Therefore, even if multiple tasks are activated almost simultaneously, only one task can generate an interrupt by applying the interrupt signal P to the CPU according to the predetermined priority order. .

Note that the task scheduler 10 and the interrupt control circuit 30
By appropriately changing the connections between tasks, it is possible to easily change the priority settings between each task.

The interrupt address generation circuit 40 is constituted by an appropriate encoder circuit or the like that receives the output signals i, a, ... f of the task scheduler IO, and generates an interrupt to the CPU by the interrupt control circuit 30. In this case, by forming a signal indicating the start address of the task that caused the interrupt, converting this into data for the number of bits corresponding to the data bus DB connected to the CPU, and then adding the start address data to the CPU, It notifies the CPU of the jump destination address to which to jump due to the interrupt. Of course, the encoder circuit described above is an encoder circuit equipped with appropriate priority logic so that an output based on the above-mentioned priority order is made in case a plurality of tasks are activated substantially simultaneously.

Next, the overall operation of the embodiment circuit shown in FIG. 2 will be briefly explained.

The task scheduler 10 recognizes that a certain task is in an executable ready state by inputting a predetermined operating condition signal, performs a predetermined operation to determine an activatable task, and selects the activatable task. Activate the corresponding output signal. As a result, the interrupt control circuit 30 issues an interrupt to the CPU by outputting an interrupt signal P to the CPU. Additionally, the interrupt address generation circuit 40 generates a jump destination address to be jumped by the interrupt, and applies this to the CPU. When an interrupt occurs, the CPU temporarily suspends the processing it has been executing, performs predetermined interrupt preprocessing, and then uses the interrupt address generation circuit 40 to jump to the added address and process the interrupt. Perform task-specific processing. When the processing is completed, the CPU operates to apply the operating condition signal corresponding to the human operation to the scheduler again in the evening in order to carry out the next processing. The above operations are repeatedly executed.

The circuit configuration of the task scheduler 10 shown in FIG. 2 is configured to correspond to the task structure shown in FIG. Of course, it can be applied to rings. The same applies to other circuit configurations, and any circuit configuration may be used as long as it has the same function as that shown in the above-described embodiment.

Further, the task scheduling circuit f according to the present invention
, ROM (read, only, memory) or PLA (
If configured using programmable logic, arrays, etc., it is possible to easily create a task scheduling circuit with versatility that can be applied to other systems by appropriately changing the memory contents of the ROM or PLA without degrading the scheduling function. It becomes possible to realize it.

As explained above, according to the task scheduling circuit according to the present invention, all the functions necessary for task scheduling are realized using hardware, so the scheduling speed is faster than that of conventional software control. This makes it possible to schedule tasks more efficiently in real-time processing. Further, by configuring the task scheduling circuit using a PLA or ROM having reversibility, a general-purpose task scheduling circuit can be realized without deteriorating the scheduling function.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an example of a task structure, and FIG. 2 is a diagram showing an example of a circuit configuration when scheduling a task having the structure shown in FIG. 1 is performed by a task scheduling circuit according to the present invention. . 10... Task scheduler, 20... Interrupt control circuit, 30... Interrupt address generation circuit.

Claims (1)

[Claims] A first logic circuit section that receives a signal related to the operating conditions of each task as an input signal and outputs a signal for determining a task to be executed based on the input signal, and a predetermined priority order among each task. a second logic circuit section that selects only one of the output signals of the first logic circuit section based on the selected signal and generates an interrupt to the central processing unit according to the selected signal; a third logic circuit section that applies a signal indicating a start address of a task to be interrupted to the central processing unit based on the output signal.