JPS61143847A - Central processor - Google Patents

Abstract

PURPOSE:To increase the processing speed of a central processor by detecting the codes of instructions excluding a basic instruction to decode an extension instruction and selecting the branch control of software or the fault processing in the detection mode by means of the software. CONSTITUTION:An extension instruction decoding circuit 4 and an extension instruction executing circuit 5 are set between a basic instruction decoding circuit 1 and a software branch circuit 3. The circuit 1 detects a desired function that is not included in a basic instruction and sends the instruction code of said function to the circuit 4. The circuit 4 decodes the instruction code and starts the circuit 3 if said instruction is not included in an extension instruction. Thus a specific software instruction can be designated as an extension instruction according to the software processing condition.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a central processing unit, and particularly to the processing of instructions for which corresponding hardware is not defined by software instructions.

(Prior Art) Conventionally, in this type of central processing unit, instructions for which the corresponding hardware is not defined are executed by software branch control to make them dependent on software processing to add functionality or to handle abnormalities. The decision on whether to proceed was made by software.

Regarding such prior art, there is a well-known document titled "Design for a set configuration of always commutative instructions" published in 1988 in Signal Configuration Words, Vol. 11, No. 2.
Qn the Design of Always
Compatible In5tructionS
et Architecture / Sig, Ar
ch, '33 Vol, 11. No, 2).

However, in a small central processing unit that requires a small amount of hardware, it is important to determine which instructions the hardware can implement, but it is important to realize all functions. Therefore, it is impossible to change the above specifications as necessary, either to implement only the most commonly necessary instructions or to create a central processing unit for a specific purpose. there were.

Here, the details of the above-mentioned conventional technique will be explained in detail with reference to FIG.

In FIG. 8, 1 is a basic instruction decoding circuit for interpreting and decoding software instructions, and 2 is a basic instruction decoding circuit for starting a microprogram based on instructions from the basic instruction decoding circuit 1 to realize the functions of the software instructions. A basic instruction execution circuit 5 is a software branch circuit for receiving an undefined instruction code detected by the basic instruction decoding circuit 1 and controlling software branching. Basic instruction decoding circuit 1 is connected to basic instruction execution circuit 2 and software branch circuit 3 by basic instruction start instruction signal line 31 and external decode instruction signal line 32, respectively.

Now, when the basic instruction decoding circuit 1 receives an instruction that is defined to be implemented as hardware, the corresponding information is placed on the basic instruction start instruction signal line 111, and the basic instruction execution circuit 2 is activated to execute the instruction. do. However, when the basic instruction decoding circuit 1 receives an instruction that is not defined as hardware, the corresponding information is placed on the external decoding instruction signal line 52 and sent to the software branch circuit 1, and software branch control is executed to decode the instruction code. It was necessary to perform processing using software according to the situation.

(Problems to be Solved by the Invention) As explained above, when hardware processing is fixed, the proportion of instructions that are handled by hardware decreases, which leads to a decrease in processing speed. The disadvantage is that it is necessary to provide a dedicated central processing unit for special purposes.

An object of the present invention is to provide an extended instruction decoding circuit for decoding extended instructions between a basic instruction decoding circuit and a software branch circuit, and to solve the above-mentioned drawbacks by instructing and executing the extended instructions. The object of the present invention is to provide a central processing unit configured to achieve high processing speed.

(Means for Solving the Problems) A central processing unit according to the present invention includes a basic instruction decoding circuit, a basic instruction execution circuit, an extended instruction decoding circuit, an extended instruction execution circuit, and a software branch circuit, When an instruction code is decoded as an undefined instruction for the relevant hardware, do you not handle the error directly, but instead perform software branch control according to the instruction code to add functionality using software, or handle the error? This selection is configured to be executed by software.

The basic instruction decoding circuit is for decoding basic instructions, and the basic instruction execution circuit is for executing basic instructions using a microprogram.

The extended instruction decoding circuit is for decoding an extended instruction when an instruction code other than the basic instruction is detected in the basic instruction decoding circuit.

The extended instruction execution circuit is for executing extended instructions in the microprogram.

The software branch circuit is for passing control to software when an undefined instruction code of the corresponding hardware is detected by the extended instruction decoding circuit.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a central processing unit according to the present invention. In FIG. 1, 1 is a basic instruction decoding circuit for decoding basic instructions, 2 is a basic instruction execution circuit for executing basic instructions, 3 is a software branch circuit for passing control to software, and 4 is an extended instruction. The decoding circuit and 5 are extended instruction execution circuits.

In FIG. 1, a basic instruction decoding circuit 1 is connected to a basic instruction execution circuit 2 and an extended instruction decoding circuit 4 by a basic instruction start instruction signal line 11 and an extended section decoding instruction signal line 13, respectively. - Extended instruction decoding Circuit 4 includes software branch circuit 3 and extended instruction execution circuit 6.
, and the basic instruction execution circuit 2 by an external decode instruction signal line 12, an extended instruction start instruction signal line 14, and an extended control storage change instruction signal line 15, respectively.

First, the extended instruction decoding circuit 4 and the extended instruction execution circuit 5
In order to change the contents of the system bus 16, an extended control memory change command is issued as shown in FIG.
Write to extended instruction decoding circuit 4 and extended instruction execution circuit 5. This enables each circuit to operate.

Furthermore, assuming that an instruction that does not exist in either the basic instruction or the extended instruction is issued, if the basic instruction decoding circuit 1 finds that the required function does not exist in the basic instruction, the basic instruction decoding circuit 1 will issue an instruction that does not exist in the basic instruction. An instruction code is placed on a partial decode instruction signal line 15 and sent to the extended instruction decoding circuit 4. When the instruction given by the extended instruction decoding circuit 4 is decoded and it is determined that the function of this instruction is not included in the extended instruction, the software branch circuit 6 is activated by the external decode instruction signal line 12, and the software is given control. passed on. Additionally, it is possible to designate a specific software instruction as an extended instruction depending on the software processing situation, thereby increasing the processing speed and changing the content of the extended instruction depending on the situation. Therefore, it is possible to provide a central processing unit suitable for software processing.

(Effects of the Invention) As explained above, the present invention increases the processing speed by providing an extended instruction decoding circuit and an extended instruction execution circuit between the basic instruction decoding circuit and the software branch circuit. This has the effect of configuring an optimal command system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a central processing unit according to the present invention. FIG. 2 is an explanatory diagram showing an example of the formant of an instruction. FIG. 3 is a block diagram showing an example of a central processing unit according to the prior art. 1.Basic instruction decoding circuit 2...Basic instruction execution circuit 3...Software branch circuit 4...Extended instruction decoding circuit 5...Extended instruction execution circuit

Claims (1)

[Claims] A basic instruction decoding circuit for decoding a basic instruction, a basic instruction execution circuit for executing the basic instruction by a microprogram, and expansion when an instruction code other than the basic instruction is detected by the basic instruction decoding circuit. an extended instruction decoding circuit for decoding an instruction, an extended instruction execution circuit for executing the extended instruction by the microprogram, and an undefined instruction code of the corresponding hardware being detected by the extended instruction decoding circuit. and a software branch circuit for passing control to software when the instruction code is decoded as an undefined instruction of the corresponding hardware, without directly performing abnormal processing. 1. A central processing unit characterized in that the central processing unit is configured such that the selection of whether to add a function by software or to handle an abnormality is executed by software by performing software branch control.