JPS62100836A - Control system for control memory address - Google Patents

Abstract

PURPOSE:To attain a fault processing system with simple constitution by storing previously plural firm ware entry addresses into a part of an address stack for execution of the fault processing and designating an entry address of the firmware when the fault is detected to perform the corresponding fault processing in response to the pulse width of the fault detecting signal. CONSTITUTION:When a fault is detected by a fault detecting means (not shown here), the contents of the fault are set and then supplied to a fault entry address control circuit 10. The circuit 10 can designate the entry address corresponding to each fault and therefore controls the pulse width of the fault detecting signal in response to the type of the fault processing to supply this signal to a stack pointer register 51. As a result, the value of the register 51 is increased and reduced with reference to the pointer where the entry address of the microprogram corresponding to the fault of an address stack 4.

Description

[Detailed Description of the Invention] C Industrial Application Field] The present invention relates to a microprogram-controlled information processing device, and in particular, a firmware routine that branches to a fixed address in a control memory when a fault is detected to deal with the fault. This invention relates to a control memory address control method for transferring control to.

[Conventional technology]

Conventionally, this type of control memory address control system has been configured such that when a fault is detected, a firmware entry address corresponding to the fault is generated by hardware and sent to the control storage device.

[Problem that the invention seeks to solve]

The conventional control memory address control method described above requires an address generation circuit corresponding to a fault, and therefore has the disadvantage that the amount of hardware increases and the number of ink faces increases.

An object of the present invention is to store the entry addresses of a plurality of microprograms that handle faults in advance in a part of the address stack, and to designate the entry address corresponding to the fault when a fault is detected. An object of the present invention is to provide a control memory address control method that suppresses an increase in the number of interfaces.

[Means for solving problems]

The control memory address control method of the present invention includes a control memory for storing microinstructions, a microinstruction register for holding the microinstructions read from the control memory, and a decoding means for decoding the contents of the microinstruction register. , an address stack that stores a return address of a subroutine and an entry address of a microprogram that handles a fault; a switching unit that switches between a part of the microinstruction and an output of the address stack to set the address of the control memory; fault entry address control means for generating a fault detection signal having a pulse width corresponding to the type of fault processing when the fault processing is detected;
and stack pointer increasing/decreasing means for increasing/decreasing the stack pointer of the address stack so as to specify the entry address of the microprogram corresponding to the fault in accordance with the pulse width of the fault detection signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The control memory address control method of this embodiment is based on the control memory 1
, microinstruction register 2, increment register 3
, address stack 4, stack pointer control circuit 5,
It is composed of a switching circuit 6, a decoding circuit 7, an adding circuit 8, a fault status register 9, and a fault entry address control circuit 10.

Referring to FIG. 2, the stack pointer control circuit 5 includes a stack pointer register 51 and an increase/decrease circuit 52.

A control memory 1 storing a plurality of microinstructions is connected to a microinstruction register 2 via a signal line 101. A portion of the microinstruction register 2 indicates an address in the control memory 1 where a microinstruction to be executed next is stored, and is connected to the switching circuit 6 via a signal line 102. The remaining portion of the microinstruction register 2 controls the execution of operations and the execution order of microprograms, and is connected to the decoding circuit 7 via a signal line 103.

The address stack 4 can store multiple return addresses from subroutines, and also stores multiple entry addresses for microprograms that handle failures at system startup in an area separate from the area that stores the return addresses. It is stored. This address stack 4 has a signal line 107
It is connected to the switching circuit 6 via.

A part of the output signal of the decoding circuit 7 is supplied to the switching circuit 6 via the signal &% 106, and depending on the logical value of this signal, a part of the output of the microinstruction register 2, an output of the increment register 3, or The output of the address stack 4 is switched and output. The output of this switching circuit 6 is connected to the control memory 1 via a signal line 108 and also to the adding circuit 8.

The adder circuit 8 has a function of adding 1 to the output of the switching circuit 6, and is connected to the increment register 3 via a signal line 109.

Increment register 3 holds a value obtained by adding 1 to the address of the microinstruction currently being executed, and signal line 1
10 to the address stack 4. This increment register 3 indicates the return address of the subroutine when the subroutine is called.

The decode circuit 7 decodes a part of the output signal of the microinstruction register 2, and a part of the decoded output signal is sent to the switching circuit 106 via the signal line 106 as described above.
is supplied to Further, another part of the output signals of the decoding circuit 7 has functions of strobe of the address stack 4 and address control of the address stack 4, and is connected to the address stack 4 via the signal line 104. It is connected to the stack pointer control circuit 5 via signal lines 401 and 402. Furthermore, the decoding circuit 7
The remaining portion of the output signal controls an arithmetic execution unit (not shown).

The stack pointer control circuit 5 receives the output signal of the decoding circuit 7 as input and controls the increase/decrease of the stack pointer, etc., and is connected to the address stack 4 via a signal line 105.

FIG. 2 is a block diagram showing the configuration of the stack pointer control circuit 5 in more detail. A stack pointer register 51 indicating a free entry in the address stack 4 shown in FIG.

The increase/decrease circuit 52 connects the signal line 402, which is the output of the decode circuit 7 shown in FIG.
This circuit adds 1 to or subtracts 1 from the stack pointer register 51 according to the logical value of the signal line 302.
It is connected to the stack pointer register 51 via.

Returning to FIG. 1, fault status register 9 is connected to fault detection means (not shown) and signal line 1
11 to the fault entry address control circuit 10. Fault entry address control circuit 1
0 outputs a fault detection signal to the signal line 112 with the pulse width controlled according to the type of fault processing in order to enable specification of the entry address corresponding to each fault I. This fault entry address control circuit 10 has a signal line 11
2 to a stack pointer register 51 (see FIG. 2) of the stack pointer control circuit 5.

Next, the operation of the control memory address control system of this embodiment configured as described above will be explained.

When a fault is detected by a fault detection means (not shown), the contents of the fault are set in the fault status register 9, and the contents of the fault are inputted to the fault entry address control circuit 10 via the signal line 111. The fault entry address control circuit 10 outputs a fault detection signal to a signal line 112 by controlling the pulse width according to the type of fault processing in order to be able to specify an entry address corresponding to each fault. The signal line 112 is connected to the stack pointer register 51, and the fault detection signal increases or decreases the stack pointer register 51 to the pointer where the entry address of the microprogram corresponding to the fault in the address stack 4 is stored. As a result, the entry address of the microprogram that performs fault processing corresponding to the fault detected from the address stack 4 is output to the signal line 107, and the control memory 1 is accessed via the switched switching circuit 6 and the signal line 108. Ru.

Therefore, the system? Control is transferred to the microprogram stored at the entry address corresponding to 8 in 1'U memory 1,
Fault handling corresponding to the detected fault is executed.

〔Effect of the invention〕

As explained above, the present invention stores the entry addresses of a plurality of firmware that performs failure processing in a part of the address stack in advance, and controls the stack pointer according to the pulse width of the failure detection signal when a failure is detected. By specifying the entry address of the firmware that performs the corresponding failure processing, it is possible to reduce the amount of hardware and interfaces.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing the stack pointer control circuit shown in FIG. 1 in more detail. In the figure, 4 1... Control memory, 2... Micro instruction register, 3... Increment register, 4... Address stack, 5... Stack pointer control circuit, 6... Switching circuit, 7 . . . decoding circuit, 8 . . . addition circuit, 9 . . . fault status register, 10 .

Claims (1)

[Scope of Claims] A control memory that stores microinstructions, a microinstruction register that holds the microinstructions read from the control memory, decoding means that decodes the contents of the microinstruction register, and a return of a subroutine. an address stack that stores an address and an entry address of a microprogram that handles a fault; a switching means that switches between a portion of the microinstruction and an output of the address stack to set the address of the control memory; and a fault is detected. a fault entry address control means for generating a fault detection signal having a pulse width depending on the type of fault processing; and a fault entry address control means for specifying an entry address of a microprogram corresponding to the fault in accordance with the pulse width of the fault detection signal. A control memory address control system comprising: stack pointer increase/decrease means for increasing/decreasing the stack pointer of the address stack as shown in FIG.