JPS61118836A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce hardware quantity by controlling collectively both a return address stack for subroutine and a return address stack for processing. CONSTITUTION:A microprogram stored in a control memory 1 is read to a reading register 2 with designation of address done by an address control circuit 3. A part of the program in the register 2 is decoded by a decoder 6 as the subroutine calling and return signals and supplied to an address stack 4, etc. When the interruption conditions are produced, an interruption control circuit 5 supplies the control information on the interruption conditions to the stack 4, etc. The stack 4 is controlled by an LIFO (last-in/first-out) system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device in an information processing device, and particularly relates to a subroutine function and an interrupt processing function.

[Prior art and problems to be solved by the invention] Conventionally, in microprogram control devices.

When equipped with subroutine functions and interrupt processing functions, for controlling the return address of microinstructions.

Since it had a subroutine address stack and a means for storing the address of the microinstruction when an interrupt occurred for interrupt processing, it had the disadvantage of increasing the amount of hardware. Furthermore, since subroutine processing and interrupt processing using microinstructions generally occur non-simultaneously, there is a drawback that if there are a plurality of storage locations for return addresses, controlling the order becomes complicated.

An object of the present invention is to make the stack of the return address for microinstruction subroutine processing and the stack of the return address for interrupt processing the same.

It is an object of the present invention to provide a microprogram control device that reduces the amount of hardware in an address stack and facilitates control of return addresses by performing collective control.

[Means for solving problems]

According to the present invention, in a microprogram control device having a subroutine function and an interrupt processing function, a control memory for storing a microprogram and an address control circuit for determining the address of a microinstruction to be executed secondarily;
an address stack capable of storing a plurality of microinstruction return addresses; means for storing a return address in the address stack when a microinstruction subroutine is called; and means for storing a return address in the address stack when a microinstruction subroutine returns. means for storing the return address after interrupt processing in the address stack when a 9th interrupt occurs; and means for taking out the return address from the address stack when the 2nd interrupt processing is completed and inputting the return address to the address control circuit. A microprogram control device is obtained, characterized in that it includes:

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to nine drawings.

In a microprogram control device according to an embodiment of the present invention shown in FIG. 1, a microprogram is stored in a control memory 1. As shown in FIG.

The address is specified from the address control circuit 3 through the signal line 18 and read out to the read register 2.

A part of the read register 2 is supplied to the address control circuit 3 through the signal line 12 and used as the ninth microinstruction address. Also read.

The other part of register 2 is supplied to decoder 6 through signal line 13 to call a subroutine.

It is decoded as a return signal from the subroutine and sent to the address control circuit 3 through control lines 14 and 15, respectively. It is supplied to the address stack 4.

Further, when a 9-interrupt condition occurs, the 9-interrupt control circuit 5 detects it and sends the address control circuit 3. Supply control information of interrupt conditions to the address stack 4.

The address control circuit 3 uses the contents of the read register 2 and data from the address stack 4 to determine the address of the microinstruction to be executed next based on control information such as interrupt conditions and subroutine conditions. Read memory 1.

Address stack 4 is a stack of multiple words and L
Controlled by IFO (La5t In First Out).

When the result of decoding the contents of read register 2 by decoder 6 is a subroutine call instruction.

The address control circuit 3 determines the return address of the subroutine and instructs the address stack 4 to stack the return address through the signal line 19. The address stack 4 stores the data and increments the stack pointer by 1. Next, when a subroutine return microinstruction is specified in the read register 2, the address stack 4 reads the latest stack address in accordance with the output of the decoder 6 and decrements the stack pointer by 1.

The read return address is supplied to the address control circuit 3 through the signal line silver and used as the address of the microinstruction to be read out first.

The above is an explanation of the operation in the case of subroutine calling and return, but in the case of 2 interrupts, the address operation is also different, except that instead of reading and operating according to the contents of register 2, it operates according to the output of 1 interrupt control circuit 5. is carried out in the same way.

Furthermore, if the subroutine is called in multiple stages,
Also, if an interrupt occurs during the execution of a subroutine,
Alternatively, when a subroutine is called during 2-interrupt processing, the operation described above is performed in exactly the same way, except that the depth of the address stack becomes deeper. . In addition,
It is necessary that the stack depth of the address stack 4 be equal to the sum of the number of subroutine calls and the number of interrupt processing stages allowed in the microprogram control device in which the present invention is implemented.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by collectively controlling the return read address stack for subroutines and the return read address stack for one interrupt processing, it is possible to provide a microprogram control device that requires less hardware and is easy to control. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (1)

[Claims] 1. A microprogram control device equipped with a subroutine function and an interrupt function, which includes a control memory that stores a microprogram, an address control circuit that determines the address of the next microinstruction to be executed, and a plurality of microinstruction return addresses. means for storing a return address in the address stack when a microinstruction subroutine is called; means for inputting the return address, means for storing the return address after interrupt processing in the address stack when an interrupt occurs, and means for taking out the return address from the address stack at the end of the interrupt processing and inputting the return address to the address control circuit. A microprogram controller comprising: